256M GDDR SDRAM K4D553235F-GC 256Mbit GDDR SDRAM Revision 1.6 March 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC Revision History Revision 1.6 (May 26, 2005) • Added CL3 of MRS table Revision 1.5 (March 16, 2005) • Corrected the spec revision history from 1.1 ~ 1.4 as below. Revision 1.4 (March 10, 2005) • Added a tCK(min) value for -GC33@CL=3 Revision 1.3 (March 04, 2005) • Removed K4D553235F-GC22 from the datasheet Revision 1.2 (February 03, 2005) • Removed -GJ from the spec which is no longer valid. • Added a couple of note below AC timing table. Revision 1.1 (December 14, 2004) • Removed K4D553235F-GC20 from the specification. • Dualized the 400MHz part’s part number by its operating voltage. Newly added -GJ25 operating voltage is equal to 2.0V(typical) which is in mass production now. The 400MHz part with VDD & VDDQ= 1.8V(typical) which represented as -GC25 will be available by the 2nd quarter of ’05 • Added a couple of note below AC timing table. Revision 1.0 (September 21, 2004) • Defined DC specification Revision 0.1 (June 16, 2004) - Target Spec • Defined target specification Revision 0.0 (May 07, 2004) - Target Spec • Defined target specification - 2 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC 2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES • 1.8V ± 0.1V power supply for device operation • No Wrtie-Interrupted by Read Function • 1.8V ± 0.1V power supply for I/O interface • 4 DQS’s ( 1DQS / Byte ) • SSTL_18 compatible inputs/outputs • Data I/O transactions on both edges of Data strobe • 4 banks operation • DLL aligns DQ and DQS transitions with Clock transition • MRS cycle with address key programs • Edge aligned data & data strobe output -. Read latency 4, 5 and 6 (clock) • Center aligned data & data strobe input -. Burst length (2, 4 and 8) • DM for write masking only -. Burst type (sequential & interleave) • Auto & Self refresh • All inputs except data & DM are sampled at the positive going edge of the system clock • 32ms refresh period (4K cycle) • 144-Ball FBGA • Differential clock input • Maximum clock frequency up to 450MHz • Maximum data rate up to 900Mbps/pin ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4D553235F-GC25 400MHz 800Mbps/pin K4D553235F-GC2A 350MHz 700Mbps/pin K4D553235F-GC33 300MHz 600Mbps/pin Interface Package SSTL_18 144-Ball FBGA * K4D553235F-VC is the Lead Free package part number. GENERAL DESCRIPTION FOR 2M x 32Bit x 4 Bank DDR SDRAM The K4D553235F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 3.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. - 3 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC PIN CONFIGURATION (Top View) 2 3 4 5 6 7 8 9 10 11 12 13 B DQS0 DM0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ DM3 DQS3 C DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27 D DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 E DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24 F DQ17 DQ16 VDDQ VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ VDDQ DQ15 DQ14 G DQ19 DQ18 VDDQ VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ VDDQ DQ13 DQ12 H DQS2 DM2 NC VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ NC DM1 DQS1 J DQ21 DQ20 VDDQ VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ VDDQ DQ11 DQ10 K DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8 L CAS WE VDD VSS A10 VDD VDD RFU1 VSS VDD NC NC M RAS NC NC BA1 A2 A11 A9 A5 RFU2 CK CK MCL N CS NC BA0 A0 A1 A3 A4 A6 A7 A8/AP CKE VREF NOTE: 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. VSS Thermal balls are optional PIN DESCRIPTION CK,CK Differential Clock Input BA0, BA1 Bank Select Address CKE Clock Enable A0 ~A11 Address Input CS Chip Select DQ0 ~ DQ31 Data Input/Output RAS Row Address Strobe VDD Power CAS Column Address Strobe VSS Ground WE Write Enable VDDQ Power for DQ’s DQS Data Strobe VSSQ Ground for DQ’s DM Data Mask NC No Connection RFU Reserved for Future Use MCL Must Connect Low - 4 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function CK, CK*1 Input The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are sampled on both edges of the DQS. CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS Input CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. WE Input Enables write operation and row precharge. Latches data in starting from CAS, WE active. Input/Output Data input and output are synchronized with both edge of DQS. DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23, DQS3 for DQ24 ~ DQ31. DM0 ~ DM3 Input Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. DQ0 ~ DQ31 Input/Output Data inputs/Outputs are multiplexed on the same pins. BA0, BA1 Input Selects which bank is to be active. A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 Column address CA8 is used for auto precharge. VDD/VSS Power Supply Power and ground for the input buffers and core logic. VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Power Supply Reference voltage for inputs, used for SSTL interface. No connection/ Reserved for future use This pin is recommended to be left "No connection" on the device Must Connect Low Must connect low DQS0 ~ DQS3 NC/RFU MCL *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. - 5 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank) 32 Intput Buffer I/O Control CK, CK Data Input Register Serial to parallel Bank Select LWE LDMi 64 2Mx32 32 Output Buffer 2-bit prefetch Sense AMP 2Mx32 64 x32 DQi 2Mx32 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length Programming Register LRAS LCBR DLL Strobe Gen. LCKE Row Decoder Refresh Counter Row Buffer ADDR Address Register CK,CK 2Mx32 Data Strobe (DQS0~DQS3) LWE LCAS LWCBR CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE - 6 - DMi Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order 1st Auto Refresh 200 Clock min. Inputs must be stable for 200us ~ ~ tRFC 2nd Auto Refresh tMRD Mode Register Set ~ precharge ALL Banks tRFC ~ ~ MRS DLL Reset ~ ~ tRP ~ ~ tMRD ~ EMRS tMRD. ~ precharge ALL Banks ~ ~ tRP Command ~ ~ CK,CK ~ Power up & Initialization Sequence Any Command * When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL. - 7 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 RFU 0 A11 A10 A9 RFU DLL A8 A8 A7 DLL TM A6 A5 A3 CAS Latency A2 BT A1 A0 Burst Length Address Bus Mode Register Burst Type Test Mode DLL Reset A4 A7 mode A3 Type 0 No 0 Normal 0 Sequential 1 Yes 1 Test 1 Interleave 0 Burst Length CAS Latency BA0 A1 A0 Sequential Interleave Reserved 0 0 0 Reserved Reserved Reserved 0 0 1 2 2 1 0 4 4 A6 A5 A4 Latency 0 MRS 0 0 0 1 EMRS 0 0 1 * RFU(Reserved for future use) should stay "0" during MRS cycle. Burst Type A2 An ~ A0 0 1 0 Reserved 0 0 1 1 3 0 1 1 8 8 1 0 0 4 1 0 0 Reserved Reserved 1 0 1 5 1 0 1 Reserved Reserved 1 1 0 6 1 1 0 Reserved Reserved Reserved 1 1 1 Reserved Reserved 1 1 1 MRS Cycle 2 CK, CK Command NOP Precharge All Banks NOP NOP 6 MRS 10 ~~ 1 ~~ 0 NOP Any Command 11 12 NOP NOP tMRD=4 tCK tRP *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. - 8 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 RFU 1 BA0 A11 A10 A9 A8 A7 RFU A6 D.I.C An ~ A0 A6 A1 0 MRS 0 0 1 EMRS A5 A4 A3 RFU Output Driver Impedence Control Full A2 Address Bus A1 A0 D.I.C DLL A0 Extended Mode Register DLL Enable 100% 0 Enable 1 Disable 0 1 Weak 60% 1 0 N/A Do not use 1 1 Matched 30% *1 : RFU(Reserved for future use) should stay "0" during EMRS cycle. Figure 7. Extended Mode Register set - 9 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 3.3 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C) Symbol Min Typ Max Unit Note Device Supply voltage Parameter VDD 1.7 1.8 1.9 V 1 Output Supply voltage VDDQ 1.7 1.8 1.9 V 1 VREF 0.49*VDDQ - 0.51*VDDQ V 2 Reference voltage Vtt VREF-0.04 VREF VREF+0.04 V 3 Input logic high voltage VIH(DC) VREF+0.15 - VDDQ+0.30 V 4 Input logic low voltage VIL(DC) -0.30 - VREF-0.15 V 5 Output logic high voltage VOH Vtt+0.76 - - V IOH=-15.2mA, 7 Output logic low voltage VOL - - Vtt-0.76 V IOL=+15.2mA, 7 Input leakage current IIL -5 - 5 uA 6 Output leakage current IOL -5 - 5 uA 6 Termination voltage Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. Output logic high voltage and low voltage is depend on output channel condition. - 10 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C) Parameter Symbol Version Test Condition -25 -2A -33 Unit Operating Current (One Bank Active) ICC1 Burst Lenth=2 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) 270 242 238 mA Precharge Standby Current in Power-down mode ICC2P CKE ≤ VIL(max), tCC= tCC(min) 10 10 10 mA Precharge Standby Current in Non Power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) 57 52 47 mA Active Standby Current power-down mode ICC3P CKE ≤ VIL(max), tCC= tCC(min) 60 55 48 mA Active Standby Current in Non Power-down mode ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) 201 183 164 mA Operating Current ( Burst Mode) ICC4 IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. 368 342 314 mA Refresh Current ICC5 tRC ≥ tRFC(min) 314 286 274 mA Self Refresh Current ICC6 CKE ≤ 0.2V 7 7 7 mA Operating Current (4Bank interleaving) ICC7 Burst Length=4 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) 615 533 479 mA Note 1 Note : 1 Refresh period is 32ms AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C) Symbol Min Typ Max Unit Input High (Logic 1) Voltage ;DQ Parameter VIH VREF+0.35 - - V Note Input Low (Logic 0) Voltage; DQ VIL - - VREF-0.35 V Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V 1 Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same - 11 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC AC OPERATING TEST CONDITIONS (TA= 0 to 65°C) Parameter Value Unit Note Input reference voltage for CK(for single ended) 0.50*VDDQ V 1 1.5 V CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(VIH/VIL) 1.0 V/ns VREF+0.4/VREF-0.4 V VREF V Vtt V Input timing measurement reference level Output timing measurement reference level Output load condition See Fig.1 Note 1 : In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK’s crossing point. Vtt=0.5*VDDQ RT=50Ω Output Z0=50Ω VREF =0.5*VDDQ CLOAD=30pF (Fig. 1) Output Load Circuit CAPACITANCE (TA= 25°C, f=1MHz) Symbol Min Max Unit Input capacitance( CK, CK ) Parameter CIN1 1.0 5.0 pF Input capacitance(A0~A11, BA0~BA1) CIN2 1.0 4.0 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) CIN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ0~DQ31) COUT 1.0 6.5 pF Input capacitance(DM0 ~ DM3) CIN4 1.0 6.5 pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Symbol Value Unit Decoupling Capacitance between VDD and VSS Parameter CDC1 0.1 + 0.01 uF Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip. - 12 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC AC CHARACTERISTICS (I) Parameter -25 Symbol CL=3 CL=4 CL=5 CL=6 CK cycle time Min 2.5 0.45 0.45 -0.45 -0.45 0.9 0.4 0.85 0 0.35 0.4 0.45 0.45 0.6 0.6 0.3 0.3 tCLmin or tCHmin tHPtQHS tCK CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble DQS-In high level width DQS-In low level width Address and Control input setup Address and Control input hold DQ and DM setup time to DQS DQ and DM hold time to DQS tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH Clock half period tHP Data Hold skew factor tQHS Data output hold time from DQS tQH -2A Max Min 2.86 0.45 0.45 -0.55 -0.55 0.9 0.4 0.85 0 0.35 0.4 0.45 0.45 0.8 0.8 0.35 0.35 tCLmin or tCHmin tHPtQHS 10.0 0.55 0.55 0.45 0.45 0.28 1.1 0.6 1.15 0.6 0.55 0.55 0.4 - -33 Max Min 5 3.3 0.45 0.45 -0.55 -0.55 0.9 0.4 0.85 0 0.35 0.4 0.45 0.45 0.8 0.8 0.35 0.35 tCLmin or tCHmin tHPtQHS 10.0 0.55 0.55 0.55 0.55 0.35 1.1 0.6 1.15 0.6 0.55 0.55 0.4 - Unit Max 0.55 0.55 0.55 0.55 0.35 1.1 0.6 1.15 0.6 0.55 0.55 - ns ns ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns - ns 10.0 0.4 ns - ns Note 1 1 1 Simplified Timing @ BL=2, CL=4 tCH 0 1 2 tCL tCK 3 5 4 6 8 7 CK, CK tIS CS tIH tDQSCK tDQSS DQS tRPST tRPRE tWPRES tDQSQ tAC DQ Qa1 tDQSH tDQSL tWPREH tDS tDH Db0 Qa2 Db1 DM WRITEB COMMAND READA - 13 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax tQH Timing (CL4, BL2) tHP 3 2 1 0 4 5 CK, CK CS DQS tDQSQ(max) tQH tDQSQ(max) COMMAND Qa1 Qa0 DQ READA Power Down Timing CK, CK tIS CKE 3tCK tIS Command VALID NOP NOP Enter Power Down mode (Read or Write operation must not be in progress) NOP NOP NOP NOP VALID Exit Powr Down mode - 14 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC AC CHARACTERISTICS (II) Parameter Symbol -25 -2A -33 Unit Note ns ns ns ns ns ns 2,5 5 5 5 4,5 5 - ns 1,5 5 - tCK 1,3 33 3 2 1 3 200 3tCK+ tIS 7.8 - ns tCK tCK tCK tCK tCK 3,5 - ns - us Min 45 50 28.6 15 10 15 Max 100K - Min 45.8 51.5 28.6 16.5 11.4 16.5 Max 100K - Min 49.5 56.1 33 16.5 11.4 16.5 Max 100K - tWR 15 - 16.5 - 16.5 Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Precharge Auto precharge write recovery + Precharge Row active to Row active Last data in to Read command Col. address to Col. address Mode register set cycle time Exit self refresh to read command tRC tRFC tRAS tRCDRD tRCDWR tRP tWR_A 6 - 6 - tDAL tRRD tCDLR tCCD tMRD tXSR - Power down exit time tPDEX tREF 33 4 2 1 3 200 3tCK+ tIS 7.8 - Refresh interval time 30 4 2 1 4 200 3tCK+ tIS 7.8 - - 1 Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM 2. The number of clock of tRC is restricted by the number of clock of tRAS and tRP 3. The number of clock of tWR_A is fixed. It can’t be changed by tCK. tWR_A is related with CL. It is equal to CL+1tCK. 4. tRCDWR is equal to tRCDRD-2tCK and the number of clock can not be lower than 2tCK. 5. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer unconditionally. - 15 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC AC CHARACTERISTICS (II) (Unit : Number of Clock) K4D553235F-GC25 Frequency Cas Latency 400MHz ( 2.5ns ) 5 tRC 18 tRFC 20 tRAS 12 tRCDRD tRCDWR 6 4 tRP 6 tRRD 4 tDAL 12 Unit K4D553235F-GC2A Frequency Cas Latency 350MHz ( 2.86ns ) 5 300MHz ( 3.3ns ) 4 tRC 16 15 tRFC 18 17 tRAS 10 10 tRCDRD tRCDWR 6 4 5 3 tRP 6 5 tRRD 4 3 tDAL 12 10 Unit K4D553235F-GC33 Frequency Cas Latency 300MHz ( 3.3ns ) 4 tRC 15 tRFC 17 tRAS 10 tRCDRD tRCDWR 5 3 tRP 5 tRRD 3 tDAL 10 Unit - 16 - tCK tCK tCK tCK Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC Simplified Timing(2) @ BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BAa BAb BAa BAb Ra Rb Ra Rb Ca Cb 17 18 19 20 21 22 CK, CK BA[1:0] BAa BAa BAa Ra A8/AP Ra ADDR (A0~A7, Ra A9,A10) Ca WE DQS DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 DM COMMAND ACTIVEA PRECH WRITEA ACTIVEA ACTIVEB WRITEA WRITEB tRCD tRAS tRP tRC Normal Write Burst (@ BL=4) tRRD Multi Bank Interleaving Write Burst (@ BL=4) - 17 - Rev 1.6 (May 2005) 256M GDDR SDRAM K4D553235F-GC PACKAGE DIMENSIONS (144-Ball FBGA) A1 INDEX MARK 12.0 12.0 <Top View> 0.8x11=8.8 0.10 Max 0.8 0.8 0.40 0.8x11=8.8 0.45 ± 0.05 B C D E F G H J K L M N A1 INDEX MARK 13 12 11 10 9 8 7 6 5 4 3 2 0.35 ± 0.05 0.40 1.40 Max <Bottom View> Unit : mm - 18 - Rev 1.6 (May 2005)