Cypress CY2XF33FLXIT High-performance lvds oscillator with frequency margining â pin control Datasheet

CY2XF33
High-Performance LVDS Oscillator With
Frequency Margining – Pin Control
Features
Functional Description
■
Low jitter crystal oscillator (XO)
■
Less than 1 ps typical RMS phase jitter
■
Differential LVDS output
■
Output frequency from 50 MHz to 690 MHz
The CY2XF33 is a high-performance and high-frequency crystal
oscillator (XO). It uses a Cypress proprietary low-noise PLL to
synthesize the frequency from an integrated crystal. The output
frequency can be changed through two select pins, allowing
easy frequency margin testing in applications.
■
Two frequency margining control pins (FS0, FS1)
■
Factory configured or field programmable
■
Integrated phase-locked loop (PLL)
■
Supply voltage: 3.3 V or 2.5 V
■
Pb-free package: 5.0 × 3.2 mm LCC
■
Commercial and industrial temperature ranges
The CY2XF33 is available as a factory configured device or as
a field programmable device.
Logic Block Diagram
Crystal
Oscillator
FS1
4
CLK
5
CLK#
Output
Divider
Low-Noise PLL
1
Frequency Select
Decode
FS0
2
Pinouts
Figure 1. Pin Diagram – 6-Pin Ceramic LCC
FS1 1
6 VDD
FS0 2
5 CLK#
VSS 3
4 CLK
Table 1. Pin Definitions – 6-Pin Ceramic LCC
Pin
Name
I/O Type
Description
1, 2
FS1, FS0
CMOS input
Frequency select
4, 5
CLK, CLK#
LVDS output
Differential output clock
6
VDD
Power
Supply voltage: 2.5 V or 3.3 V
3
VSS
Power
Ground
Cypress Semiconductor Corporation
Document Number: 001-53148 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 13, 2011
CY2XF33
Contents
Pinouts .............................................................................. 1
Contents ............................................................................ 2
Functional Description ..................................................... 3
Programming Description ............................................... 3
Field Programmable CY2XF33F ................................. 3
Factory Configured CY2XF33 ..................................... 3
Application-Specific Factory Configurations ................ 4
Programming Variables ................................................... 4
Output Frequencies ..................................................... 4
Industrial Versus Commercial Device Performance .... 4
Phase Noise Versus Jitter Performance ..................... 4
Absolute Maximum Conditions ....................................... 5
Operating Conditions ....................................................... 5
DC Electrical Characteristics .......................................... 5
AC Electrical Characteristics ........................................... 6
Document Number: 001-53148 Rev. *E
Termination Circuits ......................................................... 6
Switching Waveforms ...................................................... 7
Ordering Information ........................................................ 8
Possible Configuration ................................................ 8
Ordering Code Definitions ........................................... 8
Package Drawings and Dimensions ............................... 9
.Acronyms ....................................................................... 10
Document Conventions ................................................. 10
Units of Measures ..................................................... 10
Document History Page ................................................. 11
Sales, Solutions, and Legal Information ...................... 11
Worldwide Sales and Design Support ....................... 11
Products .................................................................... 11
PSoC Solutions ......................................................... 11
Page 2 of 12
CY2XF33
Functional Description
Field Programmable CY2XF33F
The FS0 and FS1 pins select between four different output
frequencies, as shown in Table 3. Frequency margining is a
common application for this feature. One frequency is used for
the standard operating mode of the device, while the other
frequencies are available for margin testing, either during
product development or in system manufacturing test.
Table 2. Frequency Select
FS1
FS0
0
0
Frequency 0
Output Frequency
0
1
Frequency 1
1
0
Frequency 2
1
1
Frequency 3
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency
excursions beyond the start frequency and the new frequency.
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
Programming Description
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a printed circuit
board (PCB). Customers use CyberClocks™ Online Software to
specify the device configuration and generate a JEDEC
(extension .jed) programming file. Programming of samples and
prototype quantities is available using a Cypress programmer.
Third party vendors manufacture programmers for small to large
volume applications. Cypress’s value added distribution partners
also provide programming services. Field programmable
devices are designated with an “F” in the part number. They are
intended for quick prototyping and inventory reduction. The
CY2XF33 is one time programmable (OTP).
The software is located at CyberClocks(TM) Online Software.
Factory Configured CY2XF33
For customers wanting ready-to-use devices, the CY2XF33 is
available with no field programming required. All requests are
submitted to the local Cypress Field Application Engineer (FAE)
or sales representative. After the request is processed, the user
receives a new part number, samples, and data sheet with the
programmed values. This part number is used for additional
sample requests and production orders.
The CY2XF33 is a programmable device. Before being used in
an application, it must be programmed with the output
frequencies and other variables described in a later section. Two
different device types are available, each with its own
programming flow. They are described in the following sections.5
Document Number: 001-53148 Rev. *E
Page 3 of 12
CY2XF33
Application-Specific Factory Configurations
Part Number
VDD
CY2XF33LXC700T
3.3 V
FS1
FS0
Output Frequency
RMS Phase Jitter (Random)
Offset Range
Jitter (Typical)
12 kHz to 20 MHz
0.65 ps
0
0
100.00 MHz
0
1
125.00 MHz
0.61 ps
1
0
200.00 MHz
0.55 ps
1
1
250.00 MHz
0.53 ps
Programming Variables
Output Frequencies
The CY2XF33 is programmed with up to four independent output
frequencies, which are then selected using the FS0 and FS1
pins. The device can synthesize frequencies to a resolution of 1
part per million (ppm), but the actual accuracy of the output
frequency is limited by the accuracy of the integrated reference
crystal.
The CY2XF33 has an output frequency range of 50 MHz to
690 MHz, but the range is not continuous. The CY2XF33 cannot
generate frequencies in the ranges of 521 MHz to 529 MHz and
596 MHz to 617 MHz.
Table 3. Device Programming Variables
Variable
Output frequency 0 (Power on default)
Output frequency 1
Output frequency 2
Output frequency 3
Optimization (phase noise or jitter)
Temperature range (Commercial or industrial)
Industrial Versus Commercial Device Performance
Industrial and Commercial devices have different internal
crystals. This has a potentially significant impact on performance
levels for applications requiring the lowest possible phase noise.
CyberClocks Online Software displays expected performance
for both options.
Phase Noise Versus Jitter Performance
In most cases, the device configuration for optimal phase noise
performance is different from the device configuration for optimal
cycle to cycle or period jitter. CyberClocks Online Software
includes algorithms to optimize performance for either
parameter.
Document Number: 001-53148 Rev. *E
Page 4 of 12
CY2XF33
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply voltage
–
–0.5
4.4
V
VIN[1]
Input voltage, DC
Relative to VSS
–0.5
VDD + 0.5
V
TS
Temperature, storage
Non operating
–55
135
C
TJ
Temperature, junction
–
–40
135
C
ESDHBM
ESD protection (human body model)
JEDEC STD 22-A114-B
2000
JA[2]
Thermal resistance, junction to ambient 0 m/s airflow
–
V
C/W
64
Operating Conditions
Parameter
VDD
Min
Typ
Max
Unit
3.3 V supply voltage range
Description
3.135
3.3
3.465
V
2.5 V supply voltage range
2.375
2.5
2.625
V
TPU
Power up time for VDD to reach minimum specified voltage (power ramp is
monotonic)
0.05
–
500
ms
TA
Ambient temperature (commercial)
0
–
70
C
–40
–
85
C
Condition
Min
Typ
Max
Unit
VDD = 3.465 V, CLK = 150 MHz, output
terminated
–
–
120
mA
VDD = 2.625 V, CLK = 150 MHz, output
terminated
–
–
115
mA
Ambient temperature (industrial)
DC Electrical Characteristics
Parameter
IDD[3]
Description
Operating supply current
VOD
LVDS differential output voltage
VDD = 3.3 V or 2.5 V, defined in Figure 3
as terminated in Figure 2
247
–
454
mV
VOD
Change in VOD between
complementary output states
VDD = 3.3 V or 2.5 V, defined in Figure 3
as terminated in Figure 2
–
–
50
mV
VOS
LVDS offset output voltage
VDD = 3.3 V or 2.5 V, defined in Figure 4
as terminated in Figure 2
1.125
–
1.375
V
VOS
Change in VOS between
complementary output states
VDD = 3.3 V or 2.5 V, RTERM = 100 
between CLK and CLK#
–
–
50
mV
VIH
Input high voltage
–
0.7 ×
VDD
–
–
V
VIL
Input low voltage
–
–
–
0.3 ×
VDD
V
IIH0
Input high current, FS0 pin
Input = VDD
–
–
115
A
IIH1
Input high current, FS1 pin
Input = VDD
–
–
10
A
IIL0
Input low current, FS0 pin
Input = VSS
–50
–
–
A
IIL1
Input low current, FS1 pin
Input = VSS
–20
–
–
A
CIN0[4]
CIN1[4]
Input capacitance, FS0 pin
–
–
15
–
pF
Input capacitance, FS1 pin
–
–
4
–
pF
Notes
1. The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors.
4. Not 100% tested, guaranteed by design and characterization.
Document Number: 001-53148 Rev. *E
Page 5 of 12
CY2XF33
AC Electrical Characteristics[5]
Min
Typ
Max
Unit
FOUT
Parameter
Output frequency[6]
Description
–
Condition
50
–
690
MHz
FSC
Frequency stability, commercial
devices[7]
TA = 0 °C to 70 °C
–
–
±35
ppm
FSI
Frequency stability, industrial devices[7] TA = –40 °C to 85 °C
–
–
±55
ppm
AG
Aging, 10 years
–
–
–
±15
ppm
TDC
Output duty cycle
F 450 MHz, measured at zero crossing
45
50
55
%
F > 450 MHz, measured at zero
crossing
40
50
60
%
TR, TF
Output rise and fall time
20% and 80% of full output swing
–
0.35
1.0
ns
TLOCK
Startup time
Time for CLK to reach valid frequency
measured from the time VDD = VDD(min)
–
–
5
ms
TLFS
Re-lock time
Time for CLK to reach valid frequency
from FS0 or FS1 pin change
–
–
1
ms
TJitter()
RMS phase jitter (random)
fOUT = 106.25 MHz (12 kHz–20 MHz)
–
1
–
ps
Termination Circuits
Figure 2. LVDS Termination
CLK
100
CLK#
Notes
5. Not 100% tested, guaranteed by design and characterization.
6. This parameter is specified in CyberClocks Online software.
7. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.
Document Number: 001-53148 Rev. *E
Page 6 of 12
CY2XF33
Switching Waveforms
Figure 3. Output Voltage Swing
CLK#
VOD1
VOD2
CLK
VOD = VOD1 - VOD2
Figure 4. Output Offset Voltage
CLK
50
V OS
50
CLK#
Figure 5. Output Duty Cycle Timing
CLK
TDC =
TPW
TPERIOD
CLK#
TPW
TPERIOD
Figure 6. Output Rise and Fall Time
CLK#
CLK
80%
80%
20%
20%
TR
TF
Figure 7. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f1
RMS Jitter =
Document Number: 001-53148 Rev. *E
f2
Area Under the Masked Phase Noise Plot
Page 7 of 12
CY2XF33
Ordering Information
Part Number
Configuration
Package Description
Product Flow
Pb-free
CY2XF33FLXCT
Field programmable
6-pin ceramic LCC SMD – Tape and Reel
Commercial, 0 °C to 70 °C
CY2XF33FLXIT
CY2XF33LXC700T[8]
Field programmable
6-pin ceramic LCC SMD – Tape and Reel
Industrial, –40 °C to 85 °C
Factory-configured
6-pin ceramic LCC SMD – tape and reel
Commercial, 0 °C to 70 °C
Possible Configuration
Some product offerings are factory programmed customer specific devices with customized part numbers.The Possible Configurations
table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales Representative for
more information.
Part Number[9]
Configuration
Package Description
Product Flow
Pb-free
CY2XF33LXCxxxT
Factory configured
6-pin ceramic LCC SMD – Tape and Reel
Commercial, 0 °C to 70 °C
CY2XF33LXIxxxT
Factory configured
6-Pin ceramic LCC SMD – Tape and Reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY xx xxx L X X xxx T
T = Tape and Reel
Customer Specific Code
Temperature Range: C = Commercial, I = Industrial
Pb-free
Package type
Part identifier
Family
Company ID: CY = Cypress
Notes
8. Device configuration details are described in the “Application-Specific Factory Configurations” on page 4.
9. “xxx” is a factory assigned code that identifies the programming option.For more details, contact your local Cypress FAE or Sales Representative.
Document Number: 001-53148 Rev. *E
Page 8 of 12
CY2XF33
Package Drawings and Dimensions
Figure 8. 6-Pin 3.2 × 5.0 mm Ceramic LCC LZ06A
0.50
1.30 Max
2.54 TYP.
SIDE VIEW
0.64 TYP.
5
4
0.32 R
INDEX
6
7
9
8
3
2
0.45 REF.
TOP VIEW
1
0.10 REF.
3.2
TYP.
1.2 TYP.
10
1.27
5.0
TYP.
0.10 R REF.
TYP.
0.20 R REF.
BOTTOM VIEW
Dimensions in mm
General Tolerance: ± 0.15MM
Kyocera dwg ref KD-VA6432-A
001-10044-*A
Package Weight ~ 0.12 grams
.
Document Number: 001-53148 Rev. *E
Page 9 of 12
CY2XF33
Acronyms
Document Conventions
Acronym
Description
Units of Measure
CLKOUT
clock output
CMOS
complementary metal oxide semiconductor
°C
degrees Celsius
DPM
die pick map
kHz
kilohertz
EPROM
erasable programmable read only memory
k
kilohm
LVDS
low-voltage differential signaling
MHz
megahertz
NTSC
national television system committee
M
megaohm
OE
output enable
µA
microampere
PAL
phase alternate line
µs
microsecond
PD
power-down
µV
microvolt
PLL
phase-locked loop
µVrms
microvolts root-mean-square
PPM
parts per million
mA
milliampere
TTL
transistor-transistor logic
mm
millimeter
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
Document Number: 001-53148 Rev. *E
Symbol
Unit of Measure
nV
nanovolt

ohm
Page 10 of 12
CY2XF33
Document History Page
Document Title: CY2XF33 High-Performance LVDS Oscillator With Frequency Margining – Pin Control
Document Number: 001-53148
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
2704379
*A
2734005
WWZ
07/09/2009 Post to external web
*B
2764787
KVM
09/18/2009 Change VOD limits from 250/450 mV to 247/454 mV
Add max limit for TR, TF: 1.0 ns
Change TLOCK max from 10 ms to 5 ms
Change TLFS max from 10 ms to 1 ms
*C
2898472
KVM
03/24/2010 Moved ‘xxx’ parts to Possible Configurations table.
Updated package diagram.
*D
3165931
BASH
02/10/2011 Removed “Preliminary” tag from the document.
Added “Application Specific Factory Configurations” section.
Added application specific part numbers and note in Ordering Code
Information.
*E
3279652
BASH
06/13/2011 Swapped FS0 and FS1 in Logic Block Diagram, Pinouts and Pin Definition on
page 1.
Removed CY2XF33LXC533T from “Application Specific Factory
Configurations” and “Ordering Information table.”
KVM/PYRS 05/11/2009 New data sheet
Document Number: 001-53148 Rev. *E
Page 11 of 12
CY2XF33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53148 Rev. *E
Revised June 13, 2011
Page 12 of 12
CyberClocks is a trademark of Cypress Semiconductor Corporation. All other products and company names mentioned in this document may be the trademarks of their respective holders.
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