INA+ INA– INB+ INB– INC+ INC– IND+ IND– AAF LNA PGA AAF LNA PGA AAF RBIAS PGA VREF LNA DVDD33x AAF DVDD18x PGA MUXA LNA PDWN AVDD33x AVDD18x FUNCTIONAL BLOCK DIAGRAM REFERENCE DSYNC MUX 12-BIT ADC DRV D[0:11] INADC+ INADC– SPI NOTES 1. AVDD18x = AVDD18, AVDD18ADC. AVDD33x = AVDD33, AVDD33A, AVDD33B, AVDD33C, AVDD33D, AVDD33REF. DVDD18x = DVDD18, DVDD18CLK. DVDD33x = DVDD33, DVDD33SPI, DVDD33CLK, DVDD33DRV. 11952-001 CLK+ CLK– AUX SDIO AD8285 CS 4-channel LNA, PGA, and AAF 1 direct to ADC channel Programmable gain amplifier (PGA) Includes low noise preamplifier (LNA) Serial peripheral interface (SPI) programmable gain 16 dB to 34 dB in 6 dB steps Antialiasing filter (AAF) Programmable third order, low-pass elliptic filter (LPF) from 1.0 MHz to 12.0 MHz Analog-to-digital converter (ADC) 12 bits of accuracy up to 72 MSPS Signal-to-noise ratio (SNR): 68.5 dB Spurious-free dynamic range (SFDR): 68 dB at gain = 16 dB Low power: 185 mW per channel at 12 bits and 72 MSPS Low noise: 3.5 nV/√Hz maximum of input referred voltage noise Power-down mode 72-lead, 10 mm × 10 mm LFCSP package Specified from −40°C to +105°C Qualified for automotive applications ZSEL FEATURES SCLK Data Sheet Radar Receive Path AFE: 4-Channel LNA/PGA/AAF with ADC AD8285 Figure 1. APPLICATIONS Automotive radar Adaptive cruise control Collision avoidance Blind spot detection Self parking Electronic bumper GENERAL DESCRIPTION The AD8285 is designed for low cost, low power, compact size, flexibility, and ease of use. It contains four channels of a low noise preamplifier (LNA) with a programmable gain amplifier (PGA) and an antialiasing filter (AAF) plus one direct to ADC channel, all integrated with a single 12-bit analog-to-digital converter (ADC). Each channel features a gain range of 16 dB to 34 dB in 6 dB increments and an ADC with a conversion rate of up to 72 MSPS. The combined input referred noise voltage of the entire channel is 3.5 nV/√Hz at maximum gain. The channel is optimized for dynamic performance and low power in applications where a small package size is critical. Rev. B Fabricated in an advanced complementary metal oxide semiconductor (CMOS) process, the AD8285 is available in a 10 mm × 10 mm, RoHS compliant, 72-lead LFCSP that is specified over the automotive temperature range of −40°C to +105°C. Table 1. Related Devices Part No. AD8283 AD8284 ADA8282 Description 6-channel LNA/PGA/AAF, pseudo simultaneous channel sampling with ADC 4-channel LNA/PGA/AAF, sequential channel sampling with ADC 4-channel LNA/PGA Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedby Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8285* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DISCUSSIONS View a parametric search of comparable parts. View all ad8285 EngineerZone Discussions. EVALUATION KITS SAMPLE AND BUY • AD8283 and AD8285 Evaluation Board Visit the product page to see pricing options. DOCUMENTATION TECHNICAL SUPPORT Data Sheet Submit a technical question or find your regional support number. • AD8285: Radar Receive Path AFE: 4-Channel LNA/PGA/ AAF with ADC Data Sheet DOCUMENT FEEDBACK DESIGN RESOURCES Submit feedback for this data sheet. • ad8285 Material Declaration • PCN-PDN Information • Quality And Reliability • Symbols and Footprints This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. AD8285 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SDIO Pin...................................................................................... 17 Applications ....................................................................................... 1 SCLK Pin ..................................................................................... 17 Functional Block Diagram .............................................................. 1 CS Pin .......................................................................................... 17 General Description ......................................................................... 1 RBIAS Pin .................................................................................... 17 Revision History ............................................................................... 2 Voltage Reference ....................................................................... 18 Specifications..................................................................................... 3 Power and Ground Recommendations ................................... 18 AC Specifications.......................................................................... 3 Exposed Paddle Thermal Heat Slug Recommendations ...... 18 Digital Specifications ................................................................... 5 Serial Peripheral Interface (SPI) ................................................... 19 Switching Specifications .............................................................. 6 Hardware Interface..................................................................... 19 Absolute Maximum Ratings............................................................ 7 Memory Map .................................................................................. 21 ESD Caution .................................................................................. 7 Reading the Memory Map Table .............................................. 21 Pin Configuration and Function Descriptions ............................. 8 Logic Levels ................................................................................. 21 Typical Performance Characteristics ........................................... 10 Reserved Locations .................................................................... 21 Theory of Operation ...................................................................... 14 Default Values ............................................................................. 21 Radar Receive Path AFE ............................................................ 14 Application Diagrams .................................................................... 25 Channel Overview ...................................................................... 15 Outline Dimensions ....................................................................... 27 ADC ............................................................................................. 16 Ordering Guide .......................................................................... 27 Clock Input Considerations ...................................................... 16 Automotive Products ................................................................. 27 Clock Duty Cycle Considerations ............................................ 17 Clock Jitter Considerations ....................................................... 17 REVISION HISTORY 9/15—Rev. A to Rev. B Added Table 1; Renumbered Sequentially .................................... 1 10/14—Rev. 0 to Rev. A Changes to Addr. (Hex) 0x15, Table 8 ......................................... 23 Changes to Ordering Guide .......................................................... 27 5/14—Revision 0: Initial Version Rev. B | Page 2 of 27 Data Sheet AD8285 SPECIFICATIONS AC SPECIFICATIONS AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI = DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted. Table 2. Parameter2 ANALOG CHANNEL CHARACTERISTICS Gain Gain Range Gain Error Input Voltage Range Input Resistance Input Capacitance Input Referred Voltage Noise Noise Figure Output Offset AAF Low-Pass Filter Cutoff Tolerance AAF Attenuation in Stop Band Group Delay Variation Channel-to-Channel Phase Variation Channel-to-Channel Gain Matching 1 dB Compression Crosstalk POWER SUPPLY AVDD18, AVDD18ADC AVDD33, AVDD33x1, AVDD33REF DVDD18, DVDD18CLK DVDD33SPI, DVDD33CLK, DVDD33DRV IAVDD18 IAVDD33 IDVDD18 IDVDD33 Total Power Dissipation Per Channel Test Conditions/Comments LNA, PGA, and AAF channels Min Typ Max 16/22/28/34 18 −1.25 Channel gain = 16 dB Channel gain = 22 dB Channel gain = 28 dB Channel gain = 34 dB 200 Ω input impedance selected 200 kΩ input impedance selected Maximum gain at 1 MHz Minimum gain at 1 MHz Maximum gain, RS = 50 Ω, unterminated Maximum gain, RS = RIN = 50 Ω Gain = 16 dB Gain = 34 dB −3 dB, programmable After filter autotune Third-order elliptic filter 2× cutoff 3× cutoff Filter set at 2 MHz Frequencies up to −3 dB ¼ of −3 dB frequency Frequencies up to −3 dB ¼ of −3 dB frequency Relative to output 0.180 160 +1.25 0.25 0.125 0.0625 0.03125 0.230 200 22 1.85 6.03 7.1 12.7 −60 −250 −10 −5 −1 −0.5 −0.25 1.7 3.1 1.7 3.1 +60 +250 1.0 to 12.0 ±5 30 40 400 ±0.5 9.8 −70 −55 1.8 3.3 1.8 3.3 1.9 3.5 1.9 3.5 V V V V 130 130 22 2 185 mA mA mA mA mW ±0.1 Full channel mode, no signal, typical supply voltage × maximum supply current; excludes output current 5 1.6 Rev. B | Page 3 of 27 +10 dB dB dB V p-p V p-p V p-p V p-p kΩ kΩ pF nV/√Hz nV/√Hz dB dB LSB LSB MHz % dB dB ns Degrees Degrees dB dB dBm dBc Full channel mode Full channel mode Power-Down Dissipation Power Supply Rejection Ratio (PSRR) 0.280 240 Unit +5 +1 +0.5 +0.25 mW mV/V AD8285 Parameter2 ADC Resolution Maximum Sample Rate Signal-to-Noise Ratio (SNR) Signal-to-Noise and Distortion (SINAD) Signal-to-Noise Ratio Full Scale (SNRFS) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Effective Number of Bits (ENOB) ADC OUTPUT CHARACTERISTICS Maximum Capacitor Load IDVDD33 Peak Current with Capacitor Load ADC REFERENCE Output Voltage Error Load Regulation Input Resistance FULL CHANNEL CHARACTERISTICS SNRFS SINAD Spurious-Free Dynamic Range (SFDR) Harmonic Distortion Second Harmonic Third Harmonic IM3 Distortion Gain Response Time Overdrive Recovery Time 1 2 Data Sheet Test Conditions/Comments fIN = 1 MHz Min Typ Max 12 72 68.5 66 Bits MSPS dB dB 68 dB Guaranteed no missing codes 1 10 10.67 Per bit Peak current per bit when driving 20 pF load; can be programmed via the SPI port, if required VREF = 1.024 V At 1.0 mA, VREF = 1.024 V Unit 20 40 pF mA 2 6 mV mV kΩ 68 68 68 66 dB dB dB dB 67 68 67 66 dB dB dB dB Gain = 16 dB Gain = 22 dB Gain = 28 dB Gain = 34 dB 68 74 74 73 dB dB dB dB fIN = 1 MHz at −10 dBFS, gain = 16 dB fIN = 1 MHz at −10 dBFS, gain = 34 dB fIN = 1 MHz at −10 dBFS, gain = 16 dB fIN = 1 MHz at −10 dBFS, gain = 34 dB fIN1 = 1 MHz, fIN2 = 1.1 MHz, −1 dBFS, gain = 34 dB −70 −70 −66 −75 −69 600 200 dBc dBc dBc dBc dBc ns ns LNA, PGA, AAF, and ADC channels fIN = 1 MHz Gain = 16 dB Gain = 22 dB Gain = 28 dB Gain = 34 dB fIN = 1 MHz Gain = 16 dB Gain = 22 dB Gain = 28 dB Gain = 34 dB fIN = 1 MHz ±25 LSB LSB LSB x stands for A, B, C, or D. See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed. Rev. B | Page 4 of 27 Data Sheet AD8285 DIGITAL SPECIFICATIONS AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI = DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted. Table 3. Parameter2 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage3 Input Common-Mode Voltage Differential Input Resistance Input Capacitance LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CS) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO)4 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) LOGIC OUTPUT (Dx, DSYNC) Logic 1 Voltage (IOH = 2 mA) Logic 0 Voltage (IOL = 2 mA) Temperature Min Full Full 25°C 25°C 250 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 0 Full Full 3.0 Full Full 3.0 Typ Max Unit CMOS/LVDS/LVPECL mV p-p V kΩ pF 1.2 20 1.5 3.6 0.3 V V kΩ pF 3.6 0.3 V V kΩ pF DVDD33x + 0.3 0.3 V V kΩ pF 30 0.5 70 0.5 30 2 1 0.3 V V 0.05 V V x stands for A, B, C, or D. See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed. 3 Specified for LVDS and LVPECL only. 4 Specified for 13 SDIO pins sharing the same connection. 2 Rev. B | Page 5 of 27 AD8285 Data Sheet SWITCHING SPECIFICATIONS AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI = DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted. Table 4. Parameter2 CLOCK Clock Rate Clock Pulse Width High (tEH) at 72 MSPS Clock Pulse Width Low (tEL) at 72 MSPS Clock Pulse Width High (tEH) at 40 MSPS Clock Pulse Width Low (tEL) at 40 MSPS OUTPUT PARAMETERS Propagation Delay (tPD) at 72 MSPS Rise Time (tR)3 Fall Time (tF)3 Data Set-Up Time (tDS) at 72 MSPS Data Hold Time (tDH) at 72 MSPS Data Set-Up Time (tDS) at 40 MSPS Data Hold Time (tDH) at 40 MSPS Pipeline Latency 2 3 Min Full Full Full Full Full 10 Full Full Full Full Full Full Full Full 1.5 Typ Max Unit 72 MSPS ns ns ns ns 5.0 ns ns ns ns ns ns ns Clock cycles 6.94 6.94 12.5 12.5 2.5 1.9 1.2 10.0 4.0 22.5 4.0 7 9.0 1.5 21.5 1.5 11.0 5.0 23.5 5.0 x stands for A, B, C, or D. See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed. Not shown in Figure 2. N N –1 INAx CLK– tEL tEH CLK+ tDS tPD D[11:0] N–7 N–6 tDH N–5 N–4 N–3 Figure 2. Timing Definitions for Switching Specifications Rev. B | Page 6 of 27 N–2 N–1 N 11952-002 1 Temperature Data Sheet AD8285 ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 5. Parameter Electrical AVDD18x1 to GND AVDD33x2 to GND DVDD18x3 to GND DVDD33x4 to GND Analog Inputs INx+, INx− to GND Auxiliary Inputs INADC+, INADC− to GND Digital Outputs D[11:0], DSYNC, SDIO to GND CLK+, CLK− to GND PDWN, SCLK, CS, AUX, MUXA, ZSEL to GND RBIAS, VREF to GND Environmental Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Rating −0.3 V to +2.0 V −0.3 V to +3.5 V −0.3 V to +2.0 V −0.3 V to +3.5 V −0.3 V to +3.5 V ESD CAUTION −0.3 V to +2.0 V −0.3 V to +3.5 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +2.0 V −40°C to +105°C −65°C to +150°C 150°C 300°C 1 AVDD18x = AVDD18 and AVDD18ADC. AVDD33x = AVDD33A, AVDD33B, AVDD33C, AVDD33D, and AVDD33REF. 3 DVDD18x = DVDD18, DVDD18CLK. 4 DVDD33x = DVDD33, DVDD33SPI, DVDD33CLK, DVDD33DRV. 2 Rev. B | Page 7 of 27 AD8285 Data Sheet 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 NC DVDD33DRV NC NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DVDD33DRV NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD8285 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 NC TEST4 DVDD18CLK CLK+ CLK– DVDD33CLK AVDD33REF VREF RBIAS BAND APOUT ANOUT TEST3 AVDD18ADC AVDD18 INADC+ INADC– NC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. TIE THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE TO THE ANALOG/DIGITAL GROUND PLANE. 11952-003 NC NC AVDD33B INB– INB+ AVDD33C INC– INC+ AVDD33D IND– IND+ AVDD33 NC NC AVDD33 NC NC NC 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC DSYNC PDWN DVDD18 SCLK SDIO CS AUX MUXA ZSEL TEST1 TEST2 DVDD33SPI AVDD18 AVDD33A INA– INA+ NC Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 0 1 2 3 Mnemonic EPAD NC DSYNC PDWN 4 5 6 7 8 DVDD18 SCLK SDIO CS AUX 9 10 MUXA ZSEL 11 12 13 14 15 16 17 18 19 20 21 22 23 TEST1 TEST2 DVDD33SPI AVDD18 AVDD33A INA− INA+ NC NC NC AVDD33B INB− INB+ Description Exposed Pad. Tie the exposed pad on the bottom of the package to the analog/digital ground plane. No Connect. Do not connect to this pin. Data Output Synchronization. Full Power Down. Logic high overrides the SPI and powers down the device. Logic low allows selection of the power down option through the SPI. 1.8 V Digital Supply. Serial Clock. Serial Data Input/Output. Chip Select Bar. Auxiliary. A logic high on AUX switches the AUX channel (INADC+/INADC−) to the ADC. The AUX pin has a higher priority than the MUXA pin. Channel A Select. Logic high forces to Channel A unless AUX is asserted. Input Impedance Select. Logic high overrides the SPI and sets the input impedance to 200 kΩ. Logic low allows selection of the input impedance through the SPI. Test. Do not use the TEST1 pin; tie it to ground. Test. Do not use the TEST2 pin; tie it to ground. 3.3 V Digital Supply for SPI Port. 1.8 V Analog Supply. 3.3 V Analog Supply for Channel A. Negative LNA Analog Input for Channel A. Positive LNA Analog Input for Channel A. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. 3.3 V Analog Supply for Channel B. Negative LNA Analog Input for Channel B. Positive LNA Analog Input for Channel B. Rev. B | Page 8 of 27 Data Sheet Pin No. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Mnemonic AVDD33C INC− INC+ AVDD33D IND− IND+ AVDD33 NC NC AVDD33 NC NC NC NC INADC− INADC+ AVDD18 AVDD18ADC TEST3 ANOUT APOUT BAND RBIAS VREF AVDD33REF DVDD33CLK CLK− CLK+ DVDD18CLK TEST4 NC NC DVDD33DRV D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NC NC DVDD33DRV NC AD8285 Description 3.3 V Analog Supply for Channel C. Negative LNA Analog Input for Channel C. Positive LNA Analog Input for Channel C. 3.3 V Analog Supply for Channel D. Negative LNA Analog Input for Channel D. Positive LNA Analog Input for Channel D. 3.3 V Analog Supply. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. 3.3 V Analog Supply. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. Negative Analog Input for Alternate Channel D (ADC Only). Positive Analog Input for Alternate Channel D (ADC Only). 1.8 V Analog Supply. 1.8 V Analog Supply for ADC. Test. Do not use the TEST3 pin; tie it to ground. Analog Outputs. The ANOUT pin is for debug purposes only. Leave this pin floating. Analog Outputs. The APOUT pin is for debug purposes only. Leave this pin floating. Band Gap Voltage. The BAND pin is for debug purposes only. Leave this pin floating. External Resistor. The RBIAS pin sets the internal ADC core bias current. Voltage Reference Input/Output. 3.3 V Analog Supply for References. 3.3 V Digital Supply for Clock. Clock Input Complement. Clock Input True. 1.8 V Digital Supply for Clock. Test. Do not use the TEST4 pin; tie it to ground. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. 3.3 V Digital Supply for Output Driver. ADC Data Output 11 (MSB). ADC Data Output 10. ADC Data Output 9. ADC Data Output 8. ADC Data Output 7. ADC Data Output 6. ADC Data Output 5. ADC Data Output 4. ADC Data Output 3. ADC Data Output 2. ADC Data Output 1. ADC Data Output 0 (LSB). No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. 3.3 V Supply for Output Driver. No Connect. Do not connect to this pin. Rev. B | Page 9 of 27 AD8285 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 50 22dB 20 16dB 10 0 –10 –20 –40 0.1 1 10 100 FREQUENCY (MHz) 11952-014 –30 33.50 GAIN ERROR (dB) 0.6 34dB 28dB 22dB 16dB 0.4 0.2 0 –0.2 –0.4 –0.6 –15 10 35 60 85 TEMPERATURE (°C) 11952-038 –0.8 –1.0 –40 33.98 34.06 34.14 34.22 34.30 34.38 34.46 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 0.23 0.25 10 9 PERCENTAGE OF DEVICES (%) PERCENTAGE OF DEVICES (%) 33.90 Figure 8. Channel-to-Channel Gain Matching (Gain = 16 dB) 8 7 6 5 4 3 2 1 16.08 16.16 16.24 16.32 16.4 16.48 16.56 16.64 16.72 16.8 16.88 GAIN ERROR (dB) 16.96 0 11952-032 16.00 33.82 GAIN MATCHING (dB) Figure 5. Gain Error vs. Temperature at All Gains 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 33.74 Figure 7. Gain Error Histogram (Gain = 34 dB) PERCENTAGE OF DEVICES (%) 0.8 33.66 GAIN ERROR (dB) Figure 4. Channel Gain vs. Frequency 1.0 33.58 11952-034 CHANNEL GAIN (dB) PERCENTAGE OF DEVICES (%) 34dB 28dB 30 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 0.23 0.25 GAIN MATCHING (dB) Figure 6. Gain Error Histogram (Gain = 16 dB) Figure 9. Channel-to-Channel Gain Matching (Gain = 34 dB) Rev. B | Page 10 of 27 11952-035 40 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 11952-033 AVDD18 = AVDD18ADC = 1.8 V, AVDD33A = AVDD33B = AVDD33C = AVDD33D = AVDD33 = AVDD33REF = AVDD33CLK = 3.3 V, TA = 25°C, fS = 72 MSPS, RIN = 200 kΩ, VREF = 1.024 V. Data Sheet AD8285 12000 70 10000 65 SNR SNR/SINAD (dBFS) 6000 4000 2000 55 50 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 CODE 40 16 22 20 6000 10 5000 0 GAIN (dB) 7000 4000 3000 –10 –20 2000 –30 1000 –40 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 CODE 34 Figure 13. SNR/SINAD vs. Gain 12MHz 8MHz 4MHz 2MHz 1MHz –50 0.1 11952-016 NUMBER OF HITS Figure 10. Output Referred Noise Histogram (Gain = 16 dB) 0 28 GAIN (dB) 11952-017 45 11952-015 0 60 1 10 100 FREQUENCY (Hz) 11952-022 NUMBER OF HITS SINAD 8000 Figure 14. Filter Response Figure 11. Output Referred Noise Histogram (Gain = 34 dB) 15 200 180 160 NOISE (nV/√Hz) 16dB 5 100 28dB 40 34dB 20 1 28dB 80 22dB 10 FREQUENCY (MHz) 16dB 0 0.1 1 FREQUENCY (MHz) 10 Figure 15. Short-Circuit Output Referred Noise vs. Frequency Figure 12. Short-Circuit Input Referred Noise vs. Frequency Rev. B | Page 11 of 27 11952-031 0 0.1 120 60 22dB 11952-030 NOISE (nV/√Hz) 34dB 140 10 AD8285 Data Sheet 1000 900 800 1.0 700 AMPLITUDE (V) GROUP DELAY (ns) 1.5 1MHz 2MHz 4MHz 8MHz 12MHz 600 500 400 300 200 0.5 0 –0.5 –1.0 1 10 100 FREQUENCY (MHz) –1.5 11952-019 0 0.1 0 0.5 1.0 2.5 3.0 3.5 4.0 Figure 19. Overdrive Recovery SECOND HARMONIC, –1dBFS SECOND HARMONIC, –10dBFS THIRD HARMONIC, –1dBFS THIRD HARMONIC, –10dBFS –45 HARMONIC DISTORTION (dBc) 2.0 TIME (µs) Figure 16. Group Delay vs. Frequency –40 1.5 11952-041 100 –50 –55 SDO 3 –60 ANALOG OUTPUT –65 2 –70 1 2 3 4 5 6 7 INPUT FREQUENCY (MHz) CH3 1V 180k 400 160k 350 140k 120k 250 100k 200 80k 150 60k 25 NOISE FIGURE (dB) 450 40k 100 0 0.01 20 34dB, 50Ω TERMINATED 15 10 34dB, UNTERMINATED 5 IMPEDANCE = 200kΩ 50 800ps/pt 30 IMPEDANCE (Ω) 200k 20k 0.1 1 10 FREQUENCY (MHz) 0 100 11952-040 IMPEDANCE (Ω) 500 IMPEDANCE = 200Ω M1µs 1.25GS/s A CH2 560mV Figure 20. Gain Step Response Figure 17. Harmonic Distortion vs. Input Frequency 300 CH2 500mV Ω 11952-024 0 0 0.1 1 FREQUENCY (MHz) Figure 21. Noise Figure vs. Frequency Figure 18. RIN vs. Frequency Rev. B | Page 12 of 27 10 11952-042 –80 11952-039 –75 Data Sheet AD8285 10 12 11 PERCENTAGE OF DEVICES (%) 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 –44 –28 –12 4 20 36 52 60 OUTPUT OFFSET (LSB) 0 –200 Figure 22. Channel Offset Distribution (Gain = 16 dB) –150 –100 –50 0 50 100 OUTPUT OFFSET (LSB) 150 Figure 23. Channel Offset Distribution (Gain = 34 dB) Rev. B | Page 13 of 27 200 11952-037 1 0 –60 11952-036 PERCENTAGE OF DEVICES (%) 9 AD8285 Data Sheet THEORY OF OPERATION The AD8285 includes a multiplexer (mux) in front of the ADC as a cost saving alternative to having an ADC for each channel. The mux automatically switches between each active channel after each ADC sample. The DSYNC output indicates when Channel A data is at the ADC output and when data for each active channel follows sequentially with each clock cycle. RADAR RECEIVE PATH AFE The primary application for the AD8285 is a high speed ramp, frequency modulated, continuous wave radar (HSR-FMCW radar). Figure 24 shows a simplified block diagram of an HSR-FMCW radar system. The signal chain requires multiple channels, each including a LNA, a PGA, an AAF, and an ADC with a 12-bit parallel output. The AD8285 provides all of these key components in a single 10 × 10 LFCSP package. The effective sample rate for each channel is reduced by a factor equal to the number of active channels. The ADC resolution of 12 bits with up to 72 MSPS sampling satisfies the requirements for most HSR-FMCW approaches. The performance of each component is designed to meet the demands of an HSR-FMCW radar system. Some examples of these performance metrics are the LNA noise, PGA gain range, AAF cutoff characteristics, and ADC sample rate and resolution. SDIO SCLK AD8285 SPI INTERFACE MUX CONTROLLER DSYNC 200Ω/ 200kΩ LNA PGA 22dB –6dB, 0dB, 6dB, 12dB PIPELINE ADC MUX AAF THIRD-ORDER ELLIPTICAL FILTER PARALLEL 3.3V CMOS D11 TO D0 12-BIT 72MSPS 11952-005 INx– Figure 24. Simplified Block Diagram of a Single Channel REF. OSCILLATOR PA VCO CHIRP RAMP GENERATOR LNA PGA AAF LNA PGA AAF 12-BIT ADC MUX LNA PGA DSP AAF AD8285 ANTENNA Figure 25. Radar System Overview Rev. B | Page 14 of 27 11952-004 INx+ Data Sheet AD8285 CHANNEL OVERVIEW Antialiasing Filter (AAF) Each channel contains an LNA, a PGA, and an AAF in the signal path. The LNA input impedance can be either 200 Ω or 200 kΩ. The PGA has selectable gains that result in channel gains ranging from 16 dB to 34 dB. The AAF has a three-pole elliptical response with a selectable cutoff frequency. The mux is synchronized with the ADC and automatically selects the next active channel after the ADC acquires a sample. The filter that the signal reaches prior to the ADC is used to band limit the signal for antialiasing. The signal path is fully differential throughout to maximize signal swing and reduce even-order distortion including the LNA, which is designed to be driven from a differential signal source. Low Noise Amplifier (LNA) Good noise performance relies on a proprietary ultralow noise LNA at the beginning of the signal chain, which minimizes the noise contributions on the following PGA and AAF. The input impedance can be either 200 Ω or 200 kΩ and is selected through the SPI port or using the ZSEL pin. The LNA supports differential output voltages as high as 4.0 V p-p with positive and negative excursions of ±1.0 V from a commonmode voltage of 1.5 V. With the output saturation level fixed, the channel gain sets the maximum input signal before saturation. Low value feedback resistors and the current driving capability of the output stage allow the LNA to achieve a low input referred noise voltage of 3.5 nV/√Hz at a channel gain of 34 dB. The use of a fully differential topology and negative feedback minimizes second-order distortion. Differential signaling enables smaller swings at each output, further reducing third order distortion. Recommendation To achieve the best possible noise performance, it is important to match the impedances seen by the positive and negative inputs. Matching the impedances ensures that any common-mode noise is rejected by the signal path. The antialiasing filter uses a combination of poles and zeros to create a third order elliptical filter. An elliptical filter is used to achieve a sharp roll-off after the cutoff frequency. The filter uses on-chip tuning to trim the capacitors to set the desired cutoff frequency. This tuning method reduces variations in the cutoff frequency due to standard IC process tolerances of resistors and capacitors. The default −3 dB low-pass filter cutoff is 1/3 or 1/4 the ADC sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI. Tuning is normally off to avoid changing the capacitor settings during critical times. The tuning circuit is enabled and disabled through the SPI. Initializing the tuning of the filter must be performed after initial power-up and after reprogramming the filter cutoff scaling or ADC sample rate. Occasional retuning during an idle time is recommended to compensate for temperature drift. A cutoff range of 1.0 MHz to 12.0 MHz is possible. An example follows: Four channels selected: A, B, C, and AUX ADC clock: 30 MHz Per channel sample rate: 30/4 = 7.5 MSPS Default tuned cutoff frequency = 7.5/4 = 1.88 MHz Mux and Mux Controller The mux is designed to scan through each active channel automatically. The mux remains on each channel for one clock cycle, then switches to the next active channel. The mux switching is synchronized to the ADC sampling so that the mux switching and channel settling time do not interfere with ADC sampling. As shown in Table 9, Address 0x0C (FLEX_MUX_ CONTROL), Channel A is usually the first converted input; the only exception occurs when Channel AUX is the sole input (see Figure 26 for the timing). Channel AUX is always the last converted input. Unselected codes place the respective channels (LNA, PGA, and filter) in power-down mode unless Address 0x0C, Bit 6 is set to 1. Figure 26 shows the timing of the clock input and data/DSYNC outputs. Rev. B | Page 15 of 27 AD8285 Data Sheet N N+1 INAx CLK– CLK+ D[11:0] XXXX OUTAN – 1 OUTB OUTC OUTD OUTAN OUTB OUTC OUTD tPD DSYNC tDH NOTES 1. FOR THIS CONFIGURATION, ADDRESS 0x0C, BITS [3:0] IS SET TO 0110 (CHANNEL A, B, C, AND D ENABLED). 2. DSYNC IS ALWAYS ALIGNED WITH CHANNEL A UNLESS CHANNEL A OR CHANNEL AUX IS THE ONLY CHANNEL SELECTED, IN WHICH CASE DSYNC IS NOT ACTIVE. 3. THERE IS A SEVEN-CLOCK CYCLE LATENCY FROM SAMPLING A CHANNEL TO ITS DIGITAL DATA BEING PRESENT ON THE PARALLEL BUS PINS. 11952-006 tDS Figure 26. Data and DSYNC Timing The AD8285 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. If a low jitter clock is available, another option is to ac-couple a differential PECL or LVDS signal to the sample clock input pins as shown in Figure 28 and Figure 29. The AD9515/AD9520-0 device family of clock drivers offers excellent jitter performance. 3.3V 50Ω* VFAC3 OUT Figure 27 shows the preferred method for clocking the AD8285. A low jitter clock source, such as the Valpey Fisher oscillator VFAC3-BHL-50MHz, is converted from single ended to differential using an RF transformer. The back to back Schottky diodes across the secondary transformer limit clock excursions into the AD8285 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD8285, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 3.3V 0.1µF CLK+ ADC AD8285 0.1µF CLK– 0.1µF SCHOTTKY DIODES: HSM2812 11952-007 VFAC3 50Ω 100Ω 0.1µF CLK+ CLK 100Ω PECL DRIVER 0.1µF CLK 240Ω ADC AD8285 CLK– 240Ω 11952-008 For optimum performance, clock the AD8285 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or by using capacitors. These pins are biased internally and require no additional bias. OUT 0.1µF 0.1µF CLOCK INPUT CONSIDERATIONS MINI-CIRCUITS® ADT1-1WT, 1:1Z 0.1µF XFMR AD951x/AD952x FAMILY *50Ω RESISTOR IS OPTIONAL. Figure 28. Differential PECL Sample Clock 3.3V 50Ω* VFAC3 AD951x/AD952x FAMILY 0.1µF OUT 0.1µF CLK+ CLK 0.1µF LVDS DRIVER 100Ω 0.1µF CLK ADC AD8285 CLK– *50Ω RESISTOR IS OPTIONAL. Figure 29. Differential LVDS Sample Clock In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, drive CLK+ directly from a CMOS gate and bypass the CLK− pin to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 30). Although the CLK+ input circuit supply is AVDD18, this input is designed to withstand input voltages of up to 3.3 V, making the selection of the drive logic voltage very flexible. The AD9515/AD9520-0 device family can provide 3.3 V inputs (see Figure 31). In this case, 39 kΩ resistor is not needed. Figure 27. Transformer Coupled Differential Clock Rev. B | Page 16 of 27 11952-009 ADC Data Sheet AD8285 3.3V CLK 50Ω* 1.8V CMOS DRIVER OPTIONAL 0.1µF 100Ω CLK+ ADC AD8285 CLK 0.1µF CLK– 0.1µF 39kΩ 11952-010 VFAC3 OUT In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. Intermediate frequency undersampling applications are particularly sensitive to jitter. AD951x/AD952x FAMILY 0.1µF *50Ω RESISTOR IS OPTIONAL. Figure 30. Single-Ended 1.8 V CMOS Sample Clock 3.3V AD951x/AD952x FAMILY 0.1µF CLK 50Ω* 3.3V CMOS DRIVER OPTIONAL 0.1µF 100Ω CLK 0.1µF 0.1µF Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about how jitter performance relates to ADCs. CLK+ ADC AD8285 CLK– SDIO PIN 11952-011 VFAC3 OUT Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD8285. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source (by gating, dividing, or other methods), retime it by the original clock during the last step. *50Ω RESISTOR IS OPTIONAL. Figure 31. Single-Ended 3.3 V CMOS Sample Clock CLOCK DUTY CYCLE CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD8285 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. The DCS allows a wide range of clock input duty cycles without affecting the performance of the AD8285. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operating in this mode. See Table 9 for more information about using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. The SDIO pin is required to operate the SPI. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V tolerant. If applications require that this pin be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. SCLK PIN The SCLK pin is required to operate the SPI port interface. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant. CS PIN The CS pin is required to operate the SPI port interface. It has an internal 70 kΩ pull-up resistor that pulls this pin high and is both 1.8 V and 3.3 V tolerant. RBIAS PIN To set the internal core bias current of the ADC, place a resistor nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using anything other than the recommended 10.0 kΩ resistor for RBIAS degrades the performance of the device. Therefore, it is imperative that at least a 1.0% tolerance on this resistor be used to achieve consistent performance. CLOCK JITTER CONSIDERATIONS High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR Degradation = 20 × log 10[1/2 × π × fA × tJ] Rev. B | Page 17 of 27 AD8285 Data Sheet VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD8285. This is gained up internally by a factor of 2, setting VREF to 1.024 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. However, this device does not support ADC full-scale ranges below 2.0 V p-p. When applying the decoupling capacitors to the VREF pin, use ceramic low ESR capacitors. These capacitors must be close to the reference pin and on the same layer of the printed circuit board (PCB) as the AD8285. The VREF pin must have both a 0.1 μF capacitor and a 1 μF capacitor connected in parallel to the analog ground. These capacitor values are recommended for the ADC to properly settle and acquire the next valid sample. POWER AND GROUND RECOMMENDATIONS When connecting power to the AD8285, it is recommended that two separate 1.8 V supplies and two separate 3.3 V supplies be used: one supply each for analog 1.8 V (AVDD18x), digital 1.8 V (DVDD18x), analog 3.3 V (AVDD33x), and digital 3.3 V (DVDD33x). If only one supply is available for both analog and digital, for example, AVDD18x and DVDD18x, route the supply to the AVDD18x first and then tap off and isolate it with a ferrite bead or a filter choke preceded by decoupling capacitors for the DVDD18x. The same is true for the analog and digital 3.3 V supplies. Use several decoupling capacitors on all supplies to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close to the device, with minimal trace lengths. When using the AD8285, a single PCB ground plane is sufficient. With proper decoupling and smart partitioning of the analog, digital, and clock sections of the PCB, optimum performance can be achieved easily. EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS It is required that the exposed paddle on the underside of the device be connected to a quiet analog ground to achieve the best electrical and thermal performance of the AD8285. Mate an exposed continuous copper plane on the PCB to the AD8285 exposed paddle, Pin 0. The copper plane must have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Fill or plug these vias with nonconductive epoxy. To maximize the coverage and adhesion between the device and the PCB, partition the continuous copper pad by overlaying a silkscreen or solder mask to divide the copper pad into several uniform sections. Dividing the copper pad ensures several tie points between the PCB and the EPAD during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the AD8285 and the PCB. For more detailed information on packaging, and for more PCB layout examples, see the AN-772 Application Note. Rev. B | Page 18 of 27 Data Sheet AD8285 SERIAL PERIPHERAL INTERFACE (SPI) The AD8285 serial peripheral interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. The SPI offers added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Three pins define the serial peripheral interface (SPI): SCLK, SDIO, and CS. The SCLK (serial clock) pin is used to synchronize the read and write data presented to the device. The SDIO (serial data input/output) pin is a dual purpose pin that allows data to be sent to and read from the internal memory map registers of the device. The CS (chip select bar) pin is an active low control that enables or disables the read and write cycles (see Table 7). Table 7. Serial Port Pins Pin SCLK SDIO CS Function Serial clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin. The typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame. Chip select bar (active low). This control gates the read and write cycles. The falling edge of the CS in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 32 and Table 8. In normal operation, CS signals to the device that SPI commands are to be received and processed. When CS is brought low, the device processes SCLK and SDIO to process instructions. Normally, CS remains low until the communication cycle is complete. However, if connected to a slow device, CS can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CS can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CS is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructions. Regardless of the mode, if CS is taken high in the middle of any byte transfer, the SPI state machine is reset, and the device waits for a new instruction. In addition to the operation modes, the SPI port can be configured to operate in different modes. For applications that do not require a control port, the CS line can be tied and held high. This places the remainder of the SPI pins in their secondary mode, as is defined in the SDIO Pin section and the SCLK Pin section. The CS pin can also be tied low to enable 2-wire mode. When CS is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CS line. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CS line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 7 constitute the physical interface between the programming device of the user and the serial port of the AD8285. The SCLK and CS pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. This interface is flexible enough to be controlled by either serial PROMs or PIC microcontrollers. This flexibility provides the user with an alternative method, other than a full SPI controller, for programming the device (see the AN-812 Application Note). If the user chooses not to use the SPI interface, these pins serve a dual function and are associated with secondary functions when the CS is strapped to AVDD33 during device power-up. See the SDIO Pin section and SCLK Pin section for details on which pin strappable functions are supported on the SPI pins. Rev. B | Page 19 of 27 AD8285 Data Sheet tDS tS tHI tCLK tDH CS tH tLO SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 32. Serial Timing Details Table 8. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO Minimum Timing (ns) 5 2 40 5 2 16 16 10 tDIS_SDIO 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CS and SCLK Hold time between CS and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 32) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 32) Rev. B | Page 20 of 27 11952-012 SCLK DON’T CARE Data Sheet AD8285 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration registers map (Address 0x00 and Address 0x01), the device index and transfer registers map (Address 0x05 and Address 0xFF), and the ADC channel functions registers map (Address 0x04 and Address 0x08 to Address 0x2C). The leftmost column of the memory map indicates the address (hex) number, and the default value is shown in the second rightmost column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Address 0x09, the GLOBAL_CLOCK register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this address followed by a 0x01 to the SW transfer bit in Register 0xFF, the duty cycle stabilizer turns off. It is important to follow each writing sequence with a write to the SW transfer bit to update the SPI registers. Note that all registers except Register 0x00, Register 0x04, Register 0x05, and Register 0xFF are buffered with a master slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. LOGIC LEVELS An explanation of various registers follows: “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” RESERVED LOCATIONS Do not write to undefined memory locations except when writing the default values suggested in this data sheet. Consider addresses marked as 0 as reserved, and these addresses must have a 0 written into their registers during power-up. DEFAULT VALUES After a reset, critical registers are automatically loaded with default values. These values are indicated in Table 9, where an X refers to an undefined feature. Rev. B | Page 21 of 27 AD8285 Data Sheet Table 9. Memory Map Register Addr. (Hex) Register Name Bit 7 (MSB) 0x00 CHIP_PORT_CONFIG 0 0x01 CHIP_ID 0x05 DEVICE_INDEX X X 0xFF DEVICE_UPDATE X X 0x04 FLEX_RES X X X 0x08 GLOBAL_MODES X X X X X 0x09 GLOBAL_CLOCK X X X X X 0x0C FLEX_MUX_CONTROL X Powerdown of unused channels, 0 = PD (powerdown; default), 1= power-on X X Bit 6 LSB first, 1 = on, 0 = off, (default) Bit 5 Bit 4 Bit 3 Chip Configuration Registers 1 1 Soft reset, 1 = on, 0 = off (default) Bit 2 Bit 1 Soft reset, 1 = on, 0 = off (default) LSB first, 1 = on, 0 = off (default) Bit 0 (LSB) 0 Chip ID, Bits[7:0] (AD8285 = 0xA2, default) Rev. B | Page 22 of 27 0x18 Read only Device Index and Transfer Registers Data X X Data ChanChannel C, nel D, 1 = on 1 = on (def(default), ault), 0 = off 0 = off X X X X Channel Functions Registers X X Default Value Data Channel B, 1 = on (default), 0 = off Data Channel A, 1 = on (default), 0 = off 0x0F X SW transfer, 1 = on, 0 = off (default) 0x00 Reserved Reserved 0x0F Internal powerdown mode, 00 = chip run (default), 01 = full powerdown, 11 = reset X X Duty cycle stabilizer, 1 = on (default), 0 = off Mux input active channels, 0000 = A, 0001 = AUX, 0010 = A and B, 0011 = A and AUX, 0100 = A, B, and C, 0101 = A, B, and AUX, 0110 = A, B, C, and D, 0111 = A, B, C, and AUX 0x00 X X Default Notes/ Comments Mirror the nibbles so that LSB- or MSB-first mode is set correct regardless of shift mode. The default value is the chip ID assigned to the AD8285. This is a readonly register. Bits are set to determine which onchip device receives the next write command. Synchronously transfers data from the master shift register to the slave. Reserved. Bits must be set to 0x00. Determines the powerdown mode (global). 0x01 Turns the internal duty cycle stabilizer on and off (global). 0x00 Selects the mux input channels to use and specifies whether to power down unused channels. Data Sheet Addr. (Hex) 0x0D Register Name FLEX_TEST_IO AD8285 Bit 7 (MSB) Bit 6 User test mode, 00 = off (default), 01 = on, single alternate, 10 = on, single once, 11 = on, alternate once Bit 5 Reset PN long gen, 1 = on, 0 = off (default) Bit 4 Reset PN short gen, 1 = on, 0 = off (default) 0x0F FLEX_CHANNEL_INPU T Filter cutoff frequency control, 0000 = 1.3 × 1/4 × fSAMPLECH, 0001 = 1.2 × 1/4 × fSAMPLECH, 0010 = 1.1 × 1/4 × fSAMPLECH, 0011 = 1.0 × 1/4 × fSAMPLECH (default), 0100 = 0.9 × 1/4 × fSAMPLECH, 0101 = 0.8 × 1/4 × fSAMPLECH, 0110 = 0.7 × 1/4 × fSAMPLECH, 0111 = not applicable, 1000 = 1.3 × 1/3 × fSAMPLECH, 1001 = 1.2 × 1/3 × fSAMPLECH, 1010 = 1.1 × 1/3 × fSAMPLECH, 1011 = 1.0 × 1/3 × fSAMPLECH, 1100 = 0.9 × 1/3 × fSAMPLECH, 1101 = 0.8 × 1/3 × fSAMPLECH, 1110 = 0.7 × 1/3 × fSAMPLECH, 1111 = not applicable X 0x10 FLEX_OFFSET X 0x11 FLEX_GAIN_1 X X X X 0x12 FLEX_BIAS_CURRENT X X X X 0x14 FLEX_OUTPUT_MODE X X X X 0x15 FLEX_OUTPUT_ ADJUST 0= enable Data Bits[11:0], 1= disable Data Bits[11:0] X X X Bit 0 Bit 3 Bit 2 Bit 1 (LSB) Output test mode—see Table 10, 0000 = off (default,) 0001 = midscale short, 0010 = +full-scale short, 0011 = −full-scale short, 0100 = checkerboard output, 0101 = PN sequence long, 0110 = PN sequence short, 0111 = one-/zero-word toggle, 1000 = user input, 1001 = 1-bit/0-bit toggle, 1010 = 1× sync, 1011 = one bit high, 1100 = mixed bit frequency (format determined by the OUTPUT_MODE register) X X X X 6-bit LNA offset adjustment, 00 0000 for LNA bias high, 01 1111 for LNA mid to high, 10 0000 for LNA mid to low (default), 10 0001 for LNA bias low X 010 = 16 dB (default), 011 = 22 dB, 100 = 28 dB, 101 = 34 dB X X LNA bias, 00 = high, 01 = mid to high (default), 10 = mid to low, 11 = low 0 = offset binary X 1= (default), output invert 1 = twos (local) complement (global) Typical output drive Typical output rise strength time and fall time, 00 = 45 mA respectively 01 = 30 mA 00 = 2.6 ns, 3.4 ns 10 = 60 mA 01 = 1.1 ns, 1.6 ns 11 = 60 mA (default) 10 = 0.7 ns, 0.9 ns 11 = 0.7 ns, 0.7 ns (default) Rev. B | Page 23 of 27 Default Value 0x00 Default Notes/ Comments When this register is set, the test data is placed on the output pins in place of normal data (local, except for PN sequence). 0x30 Low-pass filter cutoff (global). fSAMPLECH = ADC sample rate/ number of active channels. Note that the absolute range is limited to 1.0 MHz to 12.0 MHz. 0x20 LNA force offset correction (local). 0x02 Total LNA + PGA gain adjustment (local) LNA bias current adjustment (global). 0x09 0x00 Configures the outputs and the format of the data. 0x0F Used to adjust output rise and fall times and select output drive strength, limiting the noise added to the channels by output switching. AD8285 Addr. (Hex) 0x18 0x19 Data Sheet Bit 7 (MSB) X Register Name FLEX_VREF Bit 0 Bit 1 (LSB) 00 = 0.625 V, 01 = 0.750 V, 10 = 0.875 V, 11 = 1.024 V (default) Default Value 0x03 Bit 6 0= internal reference, 1= external reference Bit 5 X Bit 4 X Bit 3 X Bit 2 X B7 B6 B5 B4 B3 B2 B1 B0 0x00 B15 B14 B13 B12 B11 B10 B9 B8 0x00 B7 B6 B5 B4 B3 B2 B1 B0 0x00 B15 B14 B13 B12 B11 B10 B9 B8 0x00 0x2B FLEX_USER_PATT1_ LSB FLEX_USER_PATT1_ MSB FLEX_USER_PATT2_ LSB FLEX_USER_PATT2_ MSB FLEX_FILTER X X X X X X X 0x00 0x2C CH_IN_IMP X Enable automatic low-pass tuning, 1 = on (selfclearing) X X X X X X 0= 200 Ω (default), 1= 200 kΩ 0x00 0x1A 0x1B 0x1C Default Notes/ Comments Select internal reference (recommended default) or external reference (global); adjust internal reference. User-defined Pattern 1, LSB User-defined Pattern 1, MSB User-defined Pattern 2, LSB User-defined Pattern 2, MSB Refer to the Antialiasing Filter (AAF) section. Input impedance adjustment (global). Table 10. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Pattern Name Off (default) Midscale short +Full-scale short −Full-scale short Checkerboard output PN sequence long PN sequence short One-/zero-word toggle User input 1-bit/0-bit toggle 1× sync One bit high Mixed bit frequency Digital Output Word 1 Not applicable 1000 0000 0000 1111 1111 1111 0000 0000 0000 1010 1010 1010 Not applicable Not applicable 1111 1111 1111 Register 0x19 to Register 0x1A 1010 1010 1010 0000 0011 1111 1000 0000 0000 1010 0011 0011 Rev. B | Page 24 of 27 Digital Output Word 2 Not applicable Same Same Same 0101 0101 0101 Not applicable Not applicable 0000 0000 0000 Register 0x1B to Register 0x1C Not applicable Not applicable Not applicable Not applicable Subject to Data Format Select Not applicable Yes Yes Yes No Yes Yes No No No No No No Data Sheet AD8285 APPLICATION DIAGRAMS The typical application diagrams for the AD8285 are shown in Figure 33 and Figure 34. As discussed in the Channel Overview section, the maximum signal swing and the minimum third-order distortion can be achieved when the AD8285 is driven with a fully differential source. The typical connections for this configuration are shown in Figure 33. AVDD33REF 0.1µF 3.3V DVDD33SPI 0.1µF 3.3V AVDD33A 0.1µF DVDD33CLK 0.1µF AVDD33B 0.1µF DVDD33DRV 0.1µF AVDD33C 0.1µF DVDD33DRV 0.1µF DVDD18 0.1µF 1.8V 1.8V AVDD18 0.1µF AVDD18 0.1µF DVDD18CLK 0.1µF AVDD18ADC 0.1µF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 AVDD33D 0.1µF SDIO CS AUX MUXA ZSEL INA– 0.1µF NC DSYNC PDWN DVDD18 SCLK SDIO CS AUX MUXA ZSEL TEST1 TEST2 DVDD33SPI AVDD18 AVDD33A INA– INA+ NC NC TEST4 DVDD18CLK CLK+ CLK– DVDD33CLK AVDD33REF VREF RBIAS BAND APOUT ANOUT TEST3 AVDD18ADC AVDD18 INADC+ INADC– NC AD8285 TOP VIEW (Not to Scale) 0.1µF 54 53 52 51 CLK+ 50 CLK– 49 48 47 46 10kΩ 0.1µF 45 44 1% 0.1µF 43 42 41 40 39 38 37 0.1µF 0.1µF INADC+ INADC– 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 INA+ 10kΩ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NC NC AVDD33B INB– INB+ AVDD33C INC– INC+ AVDD33D IND– IND+ AVDD33 NC NC AVDD33 NC NC NC NC DSYNC PDWN SCLK NC DVDD33DRV NC NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DVDD33DRV NC 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 0.1µF 0.1µF 0.1µF INC– INB+ 0.1µF INC+ 0.1µF IND+ 0.1µF 0.1µF IND– NOTES 1. ALL CAPACITORS FOR SUPPLIES AND REFERENCES MUST BE PLACED CLOSE TO THE DEVICE. Figure 33. Differential Inputs Application Diagram Rev. B | Page 25 of 27 11952-029 INB– AD8285 Data Sheet The AD8285 can also be driven with a single-ended source, as shown in Figure 34. In this configuration, the negative analog input of each channel is grounded through a resistor and a 0.1 μF capacitor. For optimal operation, this resistor must match the output impedance of the input driver. AVDD33REF 0.1µF 3.3V DVDD33SPI 0.1µF 3.3V AVDD33A 0.1µF DVDD33CLK 0.1µF AVDD33B 0.1µF DVDD33DRV 0.1µF AVDD33C 0.1µF DVDD33DRV 0.1µF 1.8V DVDD18 0.1µF AVDD18 0.1µF 1.8V AVDD18 0.1µF DVDD18CLK 0.1µF AVDD18ADC 0.1µF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 AVDD33D 0.1µF SDIO CS AUX MUXA ZSEL 10kΩ R 0.1µF NC DSYNC PDWN DVDD18 SCLK SDIO CS AUX MUXA ZSEL TEST1 TEST2 DVDD33SPI AVDD18 AVDD33A INA– INA+ NC AD8285 TOP VIEW (Not to Scale) NC TEST4 DVDD18CLK CLK+ CLK– DVDD33CLK AVDD33REF VREF RBIAS BAND APOUT ANOUT TEST3 AVDD18ADC AVDD18 INADC+ INADC– NC 0.1µF 54 53 52 51 CLK+ 50 CLK– 49 48 47 46 10kΩ 0.1µF 45 44 1% 0.1µF 43 42 41 40 39 38 37 0.1µF 0.1µF INADC+ INADC– 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 INA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NC NC AVDD33B INB– INB+ AVDD33C INC– INC+ AVDD33D IND– IND+ AVDD33 NC NC AVDD33 NC NC NC NC DSYNC PDWN SCLK NC DVDD33DRV NC NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DVDD33DRV NC 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 0.1µF INB 0.1µF INC 0.1µF IND NOTES 1. RESISTOR R (INx– INPUTS) MUST MATCH THE OUTPUT IMPEDANCE OF THE INPUT DRIVER. 2. ALL CAPACITORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLOSE TO THE DEVICE. Figure 34. Single-Ended Inputs Application Diagram Rev. B | Page 26 of 27 11952-100 0.1µF Data Sheet AD8285 OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 0.60 0.42 0.24 9.85 9.75 SQ 9.65 55 54 72 0.50 BSC 18 19 BOTTOM VIEW 0.25 MIN 8.50 REF 0.70 0.65 0.60 0.05 MAX 0.01 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 37 36 TOP VIEW 12° MAX 1 8.60 8.50 SQ 8.40 EXPOSED PAD 0.50 0.40 0.30 0.90 0.85 0.80 0.30 0.23 0.18 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 11-06-2013-C PIN 1 INDICATOR 0.60 0.42 0.24 Figure 35. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-5) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 AD8285WBCPZ-RL AD8285WBCPZ AD8285CP-EBZ 1 2 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 72-Lead LFCSP_VQ, 13” Tape and Reel 72-Lead LFCSP_VQ Evaluation Board Package Option CP-72-5 CP-72-5 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD8285WBCPZ models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11952-0-9/15(B) Rev. B | Page 27 of 27