Fujitsu MBM29LV001BC-55PD 1m (128k x 8) bit Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20861-3E
FLASH MEMORY
CMOS
1M (128K × 8) BIT
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ FEATURES
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
32-pin PLCC (Package suffix: PD)
• Minimum 100,000 program/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
One 8K byte, two 4K bytes, and seven 16K bytes
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Hardware RESET pin
Resets internal state machine to the read mode
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set function by Extended sector protection command
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ PACKAGE
32-pin plastic TSOP (I)
(FPT-32P-M24)
32-pin plastic TSOP (I)
Marking Side
(FPT-32P-M25)
32-pin plastic QFJ (PLCC)
Marking Side
(LCC-32P-M02)
2
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ GENERAL DESCRIPTION
The MBM29LV001TC/BC are a 1M-bit, 3.0 V-only Flash memory organized as 128K bytes of 8 bits each. The
MBM29LV001TC/BC are offered in a 32-pin TSOP(I) and 32-pin PLCC packages. These devices are designed
to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required
for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV001TC/BC offer access times 55 ns and 70 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29LV001TC/BC are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV001TC/BC are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
Any individual sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV001TC/BC are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the devices
internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29LV001TC/BC memories electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte
at a time using the EPROM programming mechanism of hot electron injection.
3
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
•
•
•
•
One 8K byte, two 4K bytes, and seven 16K bytes.
Individual-sector, multiple-sector, or bulk-erase capability.
Individual or multiple-sector protection is user definable.
Device is available in top or bottom boot sector architecture.
16K byte
16K byte
16K byte
16K byte
16K byte
16K byte
16K byte
4K byte
4K byte
8K byte
(×8)
00000H to 03FFFH
04000H to 07FFFH
08000H to 0BFFFH
0C000H to 0FFFFH
10000H to 13FFFH
14000H to 17FFFH
18000H to 1BFFFH
1C000H to 1CFFFH
1D000H to 1DFFFH
1E000H to 1FFFFH
00000H to 00000H
MBM29LV001TC Top Boot
Sector Architecture
4
8K byte
4K byte
4K byte
16K byte
16K byte
16K byte
16K byte
16K byte
16K byte
16K byte
(×8)
00000H to 01FFFH
02000H to 02FFFH
03000H to 03FFFH
04000H to 07FFFH
08000H to 0BFFFH
0C000H to 0FFFFH
10000H to 13FFFH
14000H to 17FFFH
18000H to 1BFFFH
1C000H to 1FFFFH
00000H to 00000H
MBM29LV001BC Bottpm Boot
Sector Architecture
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ PRODUCT LINE UP
Part No.
MBM29LV001TC/MBM29LV001BC
VCC = 3.3 V
+0.3 V
–0.3 V
-55
—
VCC = 3.0 V
+0.6 V
–0.3 V
—
-70
Max. Address Access Time (ns)
55
70
Max. CE Access Time (ns)
55
70
Max. OE Access Time (ns)
25
30
Ordering Part No.
■ BLOCK DIAGRAM
DQ 0 to DQ 7
VCC
VSS
Erase Voltage
Generator
Input/Output
Buffers
WE
State
Control
RESET
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
STB
Data Latch
OE
STB
Low VCC Detector
Timer for
Program/Erase
Address
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0 to A16
5
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ CONNECTION DIAGRAMS
TSOP (I)
A11
A9
A8
A13
A14
N.C.
WE
VCC
RESET
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Marking Side
MBM29LV001TC/BC
Standard Pinout
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
V SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
FPT-32P-M24
A4
A5
A6
A7
A12
A15
A16
RESET
VCC
WE
N.C.
A14
A13
A8
A9
A11
Marking Side
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MBM29LV001TC/BC
Reverse Pinout
FPT-32P-M25
A12
A15
A16
RESET
V CC
WE
N.C.
PLCC
4
3
2
1
32
31
30
A13
A5
7
27
A8
A4
8
26
A9
A3
9
25
A11
A2
10
24
OE
A1
11
23
A10
A0
12
22
CE
DQ0
13
21
DQ7
14
15
16
17
18
19
20
DQ6
28
DQ 5
6
DQ 4
A6
DQ3
A14
VSS
29
DQ 2
5
DQ1
A7
LCC-32P-M02
6
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
CE
A10
OE
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ LOGIC SYMBOL
Table 1
MBM29LV001TC/001BC Pin Configuration
Pin
Function
A0 to A16
Address Inputs
DQ0 to DQ7
17
A0 to A16
8
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
DQ 0 to DQ 7
CE
OE
WE
Hardware Reset Pin/Temporary Sector
Unprotection
RESET
RESET
Table 2
N.C.
No Internal Connection
VSS
Device Ground
VCC
Device Power Supply
MBM29LV001TC/001BC User Bus Operations
Operation
CE
OE
WE
A0
A1
A6
A9
DQ0 to DQ7
RESET
Auto-Select Manufacturer Code (1)
L
L
H
L
L
L
VID
Code
H
Auto-Select Device Code (1)
L
L
H
H
L
L
VID
Code
H
Read (3)
L
L
H
A0
A1
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
HIGH-Z
H
Output Disable
L
H
H
X
X
X
X
HIGH-Z
H
Write (Program/Erase)
L
H
L
A0
A1
A6
A9
DIN
H
Enable Sector Protection (2), (4)
L
VID
L
H
L
VID
X
H
Verify Sector Protection (2), (4)
L
L
H
L
H
L
VID
Code
H
Temporary Sector Unprotection (5)
X
X
X
X
X
X
X
X
VID
Reset (Hardware)/Standby
X
X
X
X
X
X
X
HIGH-Z
L
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 6.
2. Refer to the section on Sector Protection.
3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
4. VCC = 3.3 V ± 10%
5. It is also used for the extended sector protection.
7
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29LV001
T
C
-55
PFTN
PACKAGE TYPE
PFTN = 32-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 32-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
PD =
32-Pin Rectangular Plastic Leaded
Chip Carrier (PLCC)
SPEED OPTION
See Product Selector Guide
Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29LV001
1Mega-bit (128K × 8-Bit) CMOS Flash Memory
3.0 V-only Read, Program, and Erase
8
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29LV001TC/BC have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or change CE pin from “H” or “L”
Standby Mode
There are two ways to implement the standby mode on the MBM29LV001TC/BC devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA. The device can be read with standard access time
(tCE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is
required even CE = “H”.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE
= “H” or “L”). Under this condition the current is consumed is less than 5 µA. Once the RESET pin is taken high,
the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29LV001TC/BC data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29LV001TC/BC automatically switch themselves to low power mode when
MBM29LV001TC/BC addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29LV001TC/BC read-out the data for changed addresses.
Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, and A6. (See Table 3.1.)
9
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29LV001TC/BC are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 6. (Refer to Autoselect Command section.)
Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04H) and (A0 = VIH) represents the device identifier
code (MBM29LV001TC = EDH and MBM29LV001BC = 6DH). These two bytes/words are given in the tables 3.1
and 3.2. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In
order to read the proper device codes when executing the autoselect, A1 must be VIL. (See Tables 3.1 and 3.2.)
Table 3 .1 MBM29LV001TC/001BC Sector Protection Verify Autoselect Codes
A12 to A16
A6
A1
A0
Code (HEX)
X
VIL
VIL
VIL
04H
MBM29LV001TC
X
VIL
VIL
VIH
EDH
MBM29LV001BC
X
VIL
VIL
VIH
6DH
Sector
Addresses
VIL
VIH
VIL
01H*
Type
Manufacture’s Code
Device Code
Sector Protection
* : Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
Table 3 .2 Expanded Autoselect Code Table
Code
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
04H
0
0
0
0
0
1
0
0
MBM29LV001TC
EDH
1
1
1
0
1
1
0
1
MBM29LV001BC
6DH
0
1
1
0
1
1
0
1
01H
0
0
0
0
0
0
0
1
Type
Manufacture’s Code
Device Code
Sector Protection
10
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Table 4
Sector Address Tables (MBM29LV001TC)
Sector
Address
A16
A15
A14
A13
A12
Address Range
SA0
0
0
0
X
X
00000H to 03FFFH
SA1
0
0
1
X
X
04000H to 07FFFH
SA2
0
1
0
X
X
08000H to 0BFFFH
SA3
0
1
1
X
X
0C000H to 0FFFFH
SA4
1
0
0
X
X
10000H to 13FFFH
SA5
1
0
1
X
X
14000H to 17FFFH
SA6
1
1
0
X
X
18000H to 1BFFFH
SA7
1
1
1
0
0
1C000H to 1CFFFH
SA8
1
1
1
0
1
1D000H to 1DFFFH
SA9
1
1
1
1
X
1E000H to 1FFFFH
Table 5
Sector Address Tables (MBM29LV001BC)
Sector
Address
A16
A15
A14
A13
A12
Address Range
SA0
0
0
0
0
X
00000H to 01FFFH
SA1
0
0
0
1
0
02000H to 02FFFH
SA2
0
0
0
1
1
03000H to 03FFFH
SA3
0
0
1
X
X
04000H to 07FFFH
SA4
0
1
0
X
X
08000H to 0BFFFH
SA5
0
1
1
X
X
0C000H to 0FFFFH
SA6
1
0
0
X
X
10000H to 13FFFH
SA7
1
0
1
X
X
14000H to 17FFFH
SA8
1
1
0
X
X
18000H to 1BFFFH
SA9
1
1
1
X
X
1C000H to 1FFFFH
11
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29LV001TC/BC feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 9). The sector protection feature is enabled using programming
equipment at the user’s site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may
program and protect sectors in the factory prior to shiping the device.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL, and A6 = VIL. The sector addresses (A16, A15, A14, A13 and A12) should be set to the sector
to be protected. Tables 4 and 5 define the sector address for each of the ten (10) individual sectors. Programming
of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of
the same. Sector addresses must be held constant during the WE pulse. See Figures 13 and 21 for sector
protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses ( A16, A15, A14, A13 and A12) while (A6, A1,
A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the devices
will read 00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T
CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
It is also possible to determine if a sector is protected in the system by writing an Autoselect com and. Performing
a read operation at the address location XX02H, where the higher order addresses (A16, A15, A14, A13 and A12)
are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See Tables 3.1 and 3.2
for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29LV001TC/BC devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected
again. See Figures 14 and 22.
12
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Table 6
Command
Sequence
MBM29LV001TC/001BC Standard Command Definitions
Bus
First Bus Second Bus Third Bus Fourth
Fifth Bus
Sixth Bus
Bus
Read/Write Write
Cycle Write Cycle
Write Write Cycle Write Cycle Write Cycle
Cycle
Cycles
Req’d
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset *1
1
XXXH F0H
—
—
—
—
—
—
—
—
—
—
Read/Reset *1
3
555H AAH
2AAH
55H
555H
F0H
RA
RD
—
—
—
—
Autoselect
3
555H AAH
2AAH
55H
555H
90H
—
—
—
—
—
—
Program
4
555H AAH
2AAH
55H
555H
A0H
PA
PD
—
—
—
—
Chip Erase
6
555H AAH
2AAH
55H
555H
80H
555H AAH
2AAH
55H
555H
10H
Sector Erase
6
555H AAH
2AAH
55H
555H
80H
555H AAH
2AAH
55H
SA
30H
Set to
Fast Mode
3
555H AAH
2AAH
55H
555H
20H
—
—
—
—
—
—
Fast Program *2
2
XXXH A0H
PA
PD
—
—
—
—
—
—
—
—
Reset from Fast
Mode
*2
2
XXXH 90H XXXH F0H
—
—
—
—
—
—
—
—
Extended
*3
Sector Protect
4
XXXH 60H
SPA
40H
SPA
SD
—
—
—
—
SPA
60H
Sector Erase Suspend
Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0H)
Sector Erase Resume
Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30H)
Notes: 1. Address bits A11 to A16 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA)
2. Bus operations are defined in Table 2.
3. RA =Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA =Address of the sector to be erased. The combination of A16, A15, A14, A13 and A12 will
uniquely select any sector.
4. RD =Data read from location RA during read operation.
PD =Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
5. SPA =Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD =Sector protection verify data. Output 01H at protected sector addresses and output 00H at
unprotected sector addresses.
*1:Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2:This command is valid while Fast Mode.
*3:This command is valid while RESET=VID.
13
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. Table 6 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both
Read/Reset commands are functionally equivalent, resetting the device to the read mode.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The devices remain enabled for reads until the command
register contents are altered.
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address XX01H returns the device code (MBM29LV001TC = EDH and MBM29LV001BC = 6DH).
(See Tables 3.1 and 3.2.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity
bit. Sector state (protection or unprotection) will be informed by address XX02H.
Scanning the sector addresses (A16, A15, A14, A13 and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1”
at device output DQ0 for a protected sector. The programming verification should be perform margin mode on
the protected sector. (See Tables 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
14
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Byte Programming
The devices are programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are
two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses
are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge
of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins
programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required
to provide further controls or timings. The device will automatically provide adequate internally generated
program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 8, Hardware
Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 17 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the last write pulse in the command sequence and terminates
when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the
mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
15
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of write pulse, while the
command (Data=30H) is latched on the rising edge of write pulse. After time-out of 50 µs from the rising edge
of the last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs
from the rising edge of the last write pulse will initiate the execution of the Sector Erase command(s). If another
falling edge of the write pulse occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine
if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than
Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the
previous command string. Resetting the devices once execution has begun will corrupt the data in the sector.
In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status
section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and
with any number of sectors (0 to 9).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the write pulse pulse for the
last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status
section.) at which time the devices return to the read mode. Data polling must be performed at an address within
any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time
(Preprogramming)] × Number of Sector Erase
Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
16
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when
writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the DQ7
bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading
DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend
command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by Data polling of DQ7, or by the Toggle Bit I (DQ6) which is the same
as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read
from any address.
To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
17
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Extended Command
(1) Fast Mode
MBM29LV001TC/BC has Fast Mode function. This mode dispenses with the initial two unclock cycles
required in the standard program command sequence by writing Fast Mode command into the command
register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in
standard program command. (Do not write erase command in this mode.) The read operation is also executed
after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. (Refer to the Figure 24 Extended algorithm.) The VCC active current is required even CE = VIH during
Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to
the Figure 24 Extended algorithm.)
(3) Extended Sector Protection
In addition to normal sector protection, the MBM29LV001TC/BC has Extended Sector Protection as extended
function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence.
Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only
RESET pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET
pin. With this condition, the operation is initiated by writing the set-up command (60H) into the command
register. Then, the sector addresses pins (A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set
to the sector to be protected (recommend to set VIL for the other addresses pins), and write extended sector
protect command (60H). A sector is typically protected in 150 µs. To verify programming of the protection
circuitry, the sector addresses pins (A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and
write a command (40H). Following the command write, a logical “1” at device output DQ0 will produce for
protected sector in the read operation. If the output data is logical “0”, please repeat to write extended sector
protect command (60H) again. To terminate the operation, it is necessary to set RESET pin to VIH.
18
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Write Operation Status
Table 8
Hardware Sequence Flags
Status
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle
1
1
0
0
Toggle
Data
Data
DQ7
Toggle
(Note 1)
0
0
1
(Note 2)
Embedded Program Algorithm
DQ7
Toggle
1
0
1
Embedded Erase Algorithm
Exceeded
Time Limits Erase
Erase Suspend Program
Suspended
(Non-Erase Suspended Sector)
Mode
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
Embedded Program Algorithm
Embedded Erase Algorithm
In Progress
Erase Suspend Read
(Erase Suspended Sector)
Erase
Erase Suspend Read
Suspended
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Data Data
Data
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to
toggle.
3. DQ0 and DQ1 are reserve pins for future use.
4. DQ4 is Fujitsu internal use only.
19
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
DQ7
Data Polling
The MBM29LV001TC/BC devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in Figure 19.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV001TC/BC data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant
of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm
operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0
to DQ7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 8.)
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29LV001TC/BC also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
20
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling DQ7, DQ6 is the only operating function of the devices under
this condition. The CE circuit will partially power down the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in Table 2.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
Refer to Table 8: Hardware Sequence Flags.
DQ2
Toggle Bit II
This Toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also Table 8 and Figure 15.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
21
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
Toggle
DQ7
Toggle (Note 1)
1 (Note 2)
Mode
Program
Erase-Suspend Program
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to
toggle.
RESET
Hardware Reset
The MBM29LV001TC/BC devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. See
Figure 12 for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
Data Protection
The MBM29LV001TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
22
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of write
pulse. The internal state machine is automatically reset to the read mode on power-up.
23
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................................................................................. –55°C to +125°C
Ambient Temperature with Power Applied .................................................................. –40°C to +85°C
Voltage with respect to Ground All pins except A9, OE and RESET (Note 1) ............. –0.5 V to VCC+0.5 V
VCC (Note 1) ................................................................................................................ –0.5 V to +5.5 V
A9, OE, and RESET (Note 2) ...................................................................................... –0.5 V to +13.0 V
Notes: 1. Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative
overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCC
+0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE and RESET pins are –0.5 V. During voltage transitions, A9, OE
and RESET pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input
voltage on A9, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of
up to 20 ns. Voltage difference between input voltage and supply voltage (VIN – VCC) do not exceed 9 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES
Ambient Temperature (TA)
MBM29LV001TC/BC-55................................................................. –20°C to +70°C
MBM29LV001TC/BC-70................................................................. –40°C to +85°C
VCC Supply Voltages
MBM29LV001TC/BC-70................................................................. +2.7 V to +3.6 V
MBM29LV001TC/BC-55................................................................. +3.0 V to +3.6 V
Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
24
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ MAXIMUM OVERSHOOT
20 ns
20 ns
+0.6 V
–0.5 V
–2.0 V
20 ns
Figure 1
Maximum Negative Overshoot Waveform
20 ns
V CC +2.0 V
V CC +0.5 V
+2.0 V
20 ns
Figure 2
20 ns
Maximum Positive Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
V CC +0.5 V
20 ns
20 ns
*: This waveform is applied for A9, OE, and RESET.
Figure 3
Maximum Positive Overshoot Waveform 2
25
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
Min.
Max.
Unit
ILI
Input Leakage Current
VIN = VSS to VCC, VCC = VCC Max.
–1.0
+1.0
µA
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max.
–1.0
+1.0
µA
ILIT
A9, OE, RESET Inputs Leakage
Current
VCC = VCC Max.
A9, OE, RESET = 12.5 V
—
35
µA
CE = VIL, OE = VIH, f=10 MHz
—
30
mA
ICC1
VCC Active Current (Note 1)
CE = VIL, OE = VIH, f=5 MHz
—
16
mA
ICC2
VCC Active Current (Note 2)
CE = VIL, OE = VIH
—
35
mA
ICC3
VCC Current (Standby)
VCC = VCC Max., CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V
—
5
µA
ICC4
VCC Current (Standby, Reset)
VCC = VCC Max.,
RESET = VSS ± 0.3 V
—
5
µA
ICC5
VCC = VCC Max., CE = VSS ± 0.3 V,
VCC Current
RESET = VCC ± 0.3 V
(Automatic Sleep Mode) (Note 3)
VIN = VCC ± 0.3 V or VSS ± 0.3 V
—
5
µA
VIL
Input Low Level
—
–0.5
0.6
V
VIH
Input High Level
—
2.0
VCC + 0.3
V
VID
Voltage for Autoselect, Sector
Protection,and Temporary Sector
Unprotection
(A9, OE, RESET)
(Note 4, 5)
—
11.5
12.5
V
VOL
Output Low Voltage Level
IOL = 4.0 mA, VCC = VCC Min.
—
0.45
V
IOH = –2.0 mA, VCC = VCC Min.
2.4
—
V
VCC – 0.4
—
V
2.3
2.5
V
VOH1
Output High Voltage Level
VOH2
VLKO
Notes: 1.
2.
3.
4.
5.
26
Test Conditions
Low VCC Lock-Out Voltage
IOH = –100 µA
—
The ICC current listed includes both the DC operating current and the frequency dependent component.
ICC active while Embedded Algorithm (program or erase) is in progress.
Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
Applicable to sector protection function.
(VID – VCC) do not exceed 9 V.
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Parameter
Symbols
Description
-55
(Note)
-70
(Note)
Unit
Min.
55
70
ns
Test Setup
JEDEC
Standard
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
CE = VIL
Max.
OE = VIL
55
70
ns
tELQV
tCE
Chip Enable to Output Delay
OE = VIL Max.
55
70
ns
tGLQV
tOE
Output Enable to Output Delay
—
Max.
30
30
ns
tEHQZ
tDF
Chip Enable to Output High-Z
—
Max.
15
25
ns
tGHQZ
tDF
Output Enable to Output High-Z
—
Max.
15
25
ns
tAXQX
tOH
Output Hold Time From
Addresses,
CE or OE, Whichever Occurs First
—
Min.
0
0
ns
—
tREADY
RESET Pin Low to Read Mode
—
Max.
20
20
µs
—
Note: Test Conditions:
Output Load: 1 TTL gate and 30 pF (MBM29LV001TC/BC-55)
1 TTL gate and 100 pF (MBM29LV001TC/BC-70)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output:1.5 V
3.3 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Notes: CL = 30 pF including jig capacitance (MBM29LV001TC/BC-55)
CL = 100 pF including jig capacitance (MBM29LV001TC/BC-70)
Figure 4
Test Conditions
27
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
• Write/Erase/Program Operations
Parameter Symbols
Description
-55
-70
Unit
Min.
55
70
ns
Address Setup Time
Min.
0
0
ns
tAH
Address Hold Time
Min.
45
45
ns
tDVWH
tDS
Data Setup Time
Min.
20
35
ns
tWHDX
tDH
Data Hold Time
Min.
0
0
ns
—
tOES
Output Enable Setup Time
Min.
0
0
ns
0
0
ns
tOEH
Output
Read
Enable Hold
Toggle and Data Polling
Time
Min.
—
Min.
10
10
ns
JEDEC
Standard
tAVAV
tWC
Write Cycle Time
tAVWL
tAS
tWLAX
tGHWL
tGHWL
Read Recover Time Before Write
Min.
0
0
ns
tGHEL
tGHEL
Read Recover Time Before Write
Min.
0
0
ns
tELWL
tCS
CE Setup Time
Min.
0
0
ns
tWLEL
tWS
WE Setup Time
Min.
0
0
ns
tWHEH
tCH
CE Hold Time
Min.
0
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
0
ns
tWLWH
tWP
Write Pulse Width
Min.
30
35
ns
tELEH
tCP
CE Pulse Width
Min.
30
35
ns
tWHWL
tWPH
Write Pulse Width High
Min.
30
30
ns
tEHEL
tCPH
CE Pulse Width High
Min.
30
30
ns
tWHWH1
tWHWH1
Byte Programming Operation
Typ.
8
8
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 1)
Typ.
1
1
sec
—
tEOE
Delay Time from Embedded Output
Enable
Max.
55
70
µs
—
tVCS
VCC Setup Time
Min.
50
50
µs
—
tVIDR
Rise Time to VID (Note 2)
Min.
500
500
ns
—
tVLHT
Voltage Transition Time (Note 2)
Min.
4
4
µs
—
tWPP
Write Pulse Width (Note 2)
Min.
100
100
µs
—
tOESP
OE Setup Time to WE Active (Note 2)
Min.
4
4
µs
—
tCSP
CE Setup Time to WE Active (Note 2)
Min.
4
4
µs
—
tRH
RESET Hold Time Before Read
Min.
200
200
ns
—
tRP
RESET Pulse Width
Min.
500
500
ns
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Protection operation.
28
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ SWITCHING WAVEFORMS
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
t RC
Addresses
Addresses Stable
t ACC
CE
t OE
t DF
OE
t OEH
WE
t CE
Outputs
High-Z
Figure 5.1
Output Valid
High-Z
AC Waveforms for Read Operations
29
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
t RC
Addresses
Addresses Stable
t ACC
t RH
RESET
t OH
High-Z
Outputs
Figure 5.2
30
Output Valid
AC Waveforms for Hardware Reset/Read Operations
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Data Polling
3rd Bus Cycle
Addresses
555H
t WC
PA
t AS
PA
t RC
t AH
CE
t CH
t CS
t CE
OE
t GHWL
t WP
t WPH
t OE
t WHWH1
WE
t OH
t DS
t DH
A0H
Data
Notes: 1.
2.
3.
4.
5.
PD
DQ 7
D OUT
D OUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
Figure 6
AC Waveforms for Alternate WE Controlled Program Operations
31
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
3rd Bus Cycle
Addresses
Data Polling
PA
555H
t WC
t AS
PA
t AH
WE
t WS
t WH
OE
t GHEL
t CP
t CPH
t WHWH1
CE
t DS
t DH
Data
Notes: 1.
2.
3.
4.
5.
PD
DQ 7
D OUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
Figure 7
32
A0H
AC Waveforms for Alternate CE Controlled Program Operations
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Addresses
2AAH
555H
t WC
t AS
555H
555H
2AAH
SA*
t AH
CE
t CS
t CH
OE
t GHWL
t WP
t WPH
WE
t DS
AAH
Data
t DH
55H
80H
AAH
55H
10H/
30H
t VCS
V CC
* : SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase.
Figure 8
AC Waveforms Chip/Sector Erase Operations
33
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
CE
t CH
t OE
t DF
OE
t OEH
WE
t CE
*
DQ7
Data
High-Z
DQ7 =
Valid Data
DQ7
t WHWH1 or 2
DQ0 to DQ6
Data
DQ0 to DQ6 = Output Flag
High-Z
DQ0 to DQ6
Valid Data
t EOE
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 9
AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
*
DQ 6
Data
DQ 6 = Toggle
DQ 6 =
Stop Toggling
DQ 6 = Toggle
Valid
tOE
* : DQ6 stops toggling. (The device has completed the Embedded operation.)
Figure 10
34
AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
A16, A15, A14
A13, A12
SAX
SAY
A0
A1
A6
12 V
3V
A9
t VLHT
12 V
3V
OE
t VLHT
t VLHT
t VLHT
t WPP
WE
t OESP
t CSP
CE
Data
01H
t VCS
t OE
VCC
SAX : Sector Address for initial sector
SAY : Sector Address for next sector
Figure 11
AC Waveforms for Sector Protection Timing Diagram
35
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
VCC
tVIDR
tVCS
tVLHT
VID
3V
3V
RESET
CE
WE
tVLHT
tVLHT
Figure 12
Enter
Embedded
Erasing
WE
Erase
Suspend
Erase
Temporary Sector Unprotection Timing Diagram
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE
Note: DQ2 is read from the erase-suspended sector.
Figure 13
36
DQ2 vs. DQ6
Erase
Erase
Complete
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
VCC
tVCS
RESET
tVLHT
tVIDR
Add
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE
TIME-OUT
WE
Data
60H
60H
40H
01H
60H
tOE
SPAX: Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 150 µs (min)
Figure 14
Extended Sector Protection Timing Diagram
37
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
EMBEDDED ALGORITHMS
Start
Write Program Command
Sequence
(See below)
Data Polling Device
Increment Address
No
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
Figure 15
38
Embedded ProgramTM Algorithm
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
EMBEDDED ALGORITHMS
Start
Write Erase Command
Sequence
(See below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional.
Sector Address/30H
Figure 16
Embedded EraseTM Algorithm
39
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Start
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 7 = Data?
VA = Address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple
erases operation.
= Any of the sector addresses within
the sector not being protected
during sector erase or multiple
sector erases operation.
Yes
No
No
DQ 5 = 1?
Yes
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 7 = Data?
Yes
No
Fail
Pass
Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 17
40
Data Polling Algorithm
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Start
Read
(DQ 0 to DQ 7)
Addr. = “H” or “L”
DQ 6 = Toggle
?
No
Yes
No
DQ 5 = 1?
Yes
Read
(DQ 0 to DQ 7)
Addr. = “H” or “L”
DQ 6 = Toggle
?
No
Yes
Fail
Pass
Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as
DQ5 changing to “1”.
Figure 18
Toggle Bit Algorithm
41
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Start
Setup Sector Addr.
(A16, A15, A14, A13, A12)
PLSCNT = 1
OE = V ID, A 9 = V ID,
A 6 = CE = V IL, RESET = V IH
A 0 = V IL, A 1 = V IH
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = V IH, CE = OE = V IL
(A 9 should remain V ID)
Read from Sector
(Addr. = SA, A 0 = V IL, A 1 = V IH,
A 6 = V IL)*
No
No
PLSCNT = 25?
Yes
Remove V ID from A 9
Write Reset Command
Data = 01H?
Yes
Yes
Protect Another Sector?
No
Device Failed
Remove V ID from A 9
Write Reset Command
Sector Protection
Completed
Figure 19
42
Sector Protection Algorithm
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
Start
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed
(Note 2)
Notes: 1. All protected sectors are unprotected.
2. All previously protected sectors are protected once again.
Figure 20
Temporary Sector Unprotection Algorithm
43
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
FAST MODE ALGORITHM
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXH/60H
PLSCNT = 1
To Sector Protection
Write SPA/60H
(A0 = VIL, A1 = VIH, A6 = VIL)
Time Out 150 µs
Increment PLSCNT
To Verify Sector Protection
Write SPA/40H
(A0 = VIL, A1 = VIH, A6 = VIL)
Setup Next Sector Address
Read from Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
No
No
PLSCNT = 25?
Yes
Data = 01H?
Yes
Remove VID from RESET
Write Reset Command
Protection Other Sector
?
No
Yes
Remove VID from RESET
Write Reset Command
Device Failed
Sector Protection
Completed
Figure 21
44
Extended Sector Protection Algorithm
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
FAST MODE ALGORITHM
Start
555H/AAH
Set Fast Mode
2AAH/55H
555H/20H
XXXH/A0H
Program Address/Program Data
Data Polling Device
Verify Byte?
No
In Fast Program
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
XXXH/90H
Reset Fast Mode
XXXH/F0H
Figure 22
Embedded ProgramTM Algorithm for Fast Mode
45
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
Min.
Typ.
Max.
Sector Erase Time
—
1
10
sec
Excludes programming time
prior to erasure
Byte Programming Time
—
8
300
µs
Excludes system-level
overhead
Chip Programming Time
—
1.0
3.1
sec
Excludes system-level
overhead
100,000
—
—
cycles
Erase/Program Cycle
—
■ TSOP(I) PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0
7
8
pF
COUT
Output Capacitance
VOUT = 0
8
10
pF
CIN2
Control Pin Capacitance
VIN = 0
8
10
pF
Typ.
Max.
Unit
Note: Test conditions TA = 25°C, f = 1.0 MHz
■ PLCC PIN CAPACITANCE
Parameter
Symbol
Parameter Description
CIN
Input Capacitance
VIN = 0
7
8
pF
COUT
Output Capacitance
VOUT = 0
8
10
pF
CIN2
Control Pin Capacitance
VIN = 0
8
10
pF
Note: Test conditions TA = 25°C, f = 1.0 MHz
46
Test Setup
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ PACKAGE DIMENSIONS
32-pin plastic TSOP(I)
(FPT-32P-M24)
LEAD No.
1
Details of "A" part
32
0.15(.006)
MAX
0.35(.014)
MAX
INDEX
"A"
16
17
0.15(.006)
0.25(.010)
0.15±0.05
(.006±.002)
20.00±0.20
(.787±.008)
18.40±0.20
(.724±.008)
8.00±0.20
(.315±.008)
0.50(.0197)
TYP
0.10(.004)
19.00±0.20
(.748±.008)
C
0.50±0.10
(.020±.004)
7.50(.295)
REF.
0.20±0.10
(.008±.004)
0.05(.002)MIN
(STAND OFF)
+0.10
+.004
1.10 –0.05 .043 –.002
(Mounting height)
0.10(.004)
M
Dimensions in mm(inches)
1994 FUJITSU LIMITED F32035S-2C-1
32-pin plastic TSOP(I)
(FPT-32P-M25)
LEAD No.
1
32
Details of "A" part
0.15(.006)
MAX
0.35(.014)
MAX
INDEX
"A"
16
17
0.15(.006)
0.20±0.10
(.008±.004)
0.15±0.05
(.006±.002)
19.00±0.20
(.748±.008)
0.10(.004)
0.50±0.10
(.020±.004)
0.50(.0197)
TYP
7.50(.295)
REF.
0.25(.010)
0.10(.004)
M
0.05(.002)MIN
(STAND OFF)
+0.10
18.40±0.20
(.724±.008)
8.00±0.20
(.315±.008)
+.004
1.10 –0.05 .043 –.002
(Mounting height)
20.00±0.20
(.787±.008)
C
1997 FUJITSU LIMITED F32036S-2C-2
Dimensions in mm(inches)
47
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
■ PACKAGE DIMENSIONS
32-pin plastic QFJ(PLCC)
(LCC-32P-M02)
3.40±0.16
(.134±.006)
2.25±0.38
(.089±.015)
12.37±0.13
(.487±.005)
11.43±0.08
(.450±.003)
4
1
32
0.64(.025)
MIN
30
5
7.62(.300)REF
1.27±0.13
(.050±.005)
29
INDEX
13.97±0.08 14.94±0.13
(.550±.003) (.588±.005)
13
12.95±0.51
(.510±.020)
10.16(.400)
REF
21
14
20
R0.95(.037)
TYP
0.66(.026)
TYP
+0.05
0.20 –0.02
+.002
.008 –.001
0.43(.017)
TYP
10.41±0.51
(.410±.020)
0.10(.004)
No
C
48
1994 FUJITSU LIMITED C32021S-2C-4
: LEAD No.
Dimensions in mm(inches)
MBM29LV001TC-55/-70/MBM29LV001BC-55/-70
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inhereut chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
http://www.fmap.com.sg/
F9904
 FUJITSU LIMITED Printed in Japan
49