BSI Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable BS616LV2025 DESCRIPTION FEATURES • Very low operation voltage : 4.5 ~ 5.5V • Very low power consumption : Vcc = 5.0V C-grade: 40mA (Max.) operating current I -grade: 45mA (Max.) operating current 0.6uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc = 5.0V -55 55ns (Max.) at Vcc = 5.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE1, CE2 and OE options • I/O Configuration x8/x16 selectable by CIO, LB and UB pin The BS616LV2025 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 words by 16 bits or 262,144 bytes by 8 bits selectable by CIO pin and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.6uA and maximum access time of 70/55 ns in 5V operation. Easy memory expansion is provided by active HIGH chip enable2(CE2), active LOW chip enable1(CE1), active LOW output enable(OE) and three-state output drivers. The BS616LV2025 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV2025 is available in DICE form and 48-pin BGA type. PRODUCT FAMILY PRODUCT FAMILY BS616LV2025DC BS616LV2025AC BS616LV2025DI BS616LV2025AI OPERATING TEMPERATURE Vcc RANGE SPEED ( ns ) POWER DISSIPATION STANDBY Operating ( ICCSB1, Max ) ( ICC, Max ) Vcc=5.0V Vcc=5.0V Vcc=5.0V O O 4.5V ~ 5.5V 70 / 55 6uA 40mA O O 4.5V ~ 5.5V 70 / 55 25uA 45mA +0 C to +70 C -40 C to +85 C PIN CONFIGURATION PKG TYPE DICE BGA-48-0608 DICE BGA-48-0608 BLOCK DIAGRAM A15 A14 A13 A12 Address A11 A10 Input A9 A8 Buffer 20 1024 Row Memory Array Decoder 1024 x 2048 A7 A6 2048 16(8) D0 . . . . . . . . Data Input Buffer 16(8) Column I/O Write Driver Sense Amp 16(8) 16(8) 128(256) Data Output Buffer D15 Column Decoder CE1 CE2 WE OE UB LB CIO 14(16) Control Address Input Buffer A16 A0 A1 A2 A3 A4 A5 (SAE) Vdd Vss Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS616LV2025 1 Revision 2.4 April 2002 BSI BS616LV2025 PIN DESCRIPTIONS Name Function A0-A16 Address Input These 17 address inputs select one of the 131,072 x 16-bit words in the RAM. SAE Address Input This address input incorporates with the above 17 address input select one of the 262,144 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH. CIO x8/x16 select input This input selects the organization of the SRAM. 131,072 x 16-bit words configuration is selected if CIO is HIGH. 262,144 x 8-bit bytes configuration is selected if CIO is LOW. CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. The chip is deselected when both LB and UB pins are HIGH. D0 - D15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground R0201-BS616LV2025 2 Revision 2.4 April 2002 BSI BS616LV2025 TRUTH TABLE MODE CE1 CE2 H X OE WE CIO X X X Fully Standby Output Disable Read from SRAM X L L H L H H L H X H H ( WORD mode ) LB UB SAE D0~7 D8~15 VCC Current X X X X X High-Z High-Z ICCSB, ICCSB1 X X X High-Z High-Z ICC L H Dout High-Z H L High-Z Dout L L Dout Dout L H Din X H L X Din L L Din Din X ICC Write to SRAM L H X L H ( WORD mode ) X ICC Read from SRAM L H L H L X X A-1 Dout High-Z ICC L H X L L X X A-1 Din X ICC ( BYTE Mode ) Write to SRAM ( BYTE Mode ) ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER OPERATING RANGE RATING UNITS -0.5 to Vcc+0.5 V V TERM Terminal Voltage with Respect to GND T BIAS Temperature Under Bias -40 to +125 O T STG Storage Temperature -60 to +150 O PT Power Dissipation 1.0 W I OUT DC Output Current 20 mA C AMBIENT TEMPERATURE Vcc Commercial 0 O C to +70 O C 4.5V ~ 5.5V Industrial O O -40 C to +85 C 4.5V ~ 5.5V C CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. R0201-BS616LV2025 RANGE 3 CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. Revision 2.4 April 2002 BSI BS616LV2025 DC ELECTRICAL CHARACTERISTICS (TA = 0oC to +70oC) PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNITS V IH Guaranteed Input Low Voltage (2) Guaranteed Input High Voltage (2) I IL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA I OL Output Leakage Current Vcc = Max, CE1 = VIHor CE2=V IL or OE = VIH, VI/O = 0V to Vcc -- -- 1 uA V OL Output Low Voltage Vcc = Max, I OL= 2mA Vcc=5.0V -- -- 0.4 V V OH Output High Voltage Vcc = Min, IOH = -1mA Vcc=5.0V 2.4 -- -- V I CC Operating Power Supply Current Vcc = Max, CE1= VIL , CE2=VIH IDQ = 0mA, F = Fmax (3) Vcc=5.0V -- -- 40 mA I CCSB Standby Current-TTL Vcc = Max, CE1 = V IH or CE2=VIL IDQ = 0mA Vcc=5.0V -- -- 1 mA Standby Current-CMOS Vcc = Max, CE1ЊVcc-0.2V or CE2Љ0.2V, Other inputs Њ Vcc - 0.2V or VINЉ0.2V Vcc=5.0V -- 0.6 6 uA V IL I CCSB1 Vcc=5.0V -0.5 -- 0.8 V Vcc=5.0V 2.2 -- Vcc+0.2 V 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . R0201-BS616LV2025 4 Revision 2.4 April 2002 BSI BS616LV2025 DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC ) SYMBOL PARAMETER TEST CONDITIONS VDR Vcc for Data Retention CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V or VIN Њ Vcc - 0.2V or VIN Љ 0.2V ICCDR Data Retention Current CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V VIN Њ Vcc - 0.2V or VIN Љ 0.2V tCDR Chip Deselect to Data Retention Time MIN. TYP. (1) MAX. UNITS 1.5 -- -- V -- 0.05 1.5 uA 0 -- -- ns TRC (2) -- -- ns See Retention Waveform tR Operation Recovery Time 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode Vcc VDR Њ 1.5V Vcc CE1 Vcc tR t CDR CE1 Њ Vcc - 0.2V VIH VIH LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) Data Retention Mode Vcc VDR Њ 1.5V Vcc CE2 R0201-BS616LV2025 VIL Vcc tR t CDR CE2 Љ 0.2V 5 VIL Revision 2.4 April 2002 BSI BS616LV2025 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level KEY TO SWITCHING WAVEFORMS Vcc/0V 5ns WAVEFORM 0.5Vcc AC TEST LOADS AND WAVEFORMS 1928 Ω 5.0V 1928 Ω 5.0V OUTPUT OUTPUT 100PF INCLUDING JIG AND SCOPE 1020 Ω 1020 Ω FIGURE 1A FIGURE 1B THEVENIN EQUIVALENT 667 Ω OUTPUT OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , 5PF INCLUDING JIG AND SCOPE INPUTS DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE 1.73V ALL INPUT PULSES Vcc GND → 10% 90% 90% 10% ← → ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V ) READ CYCLE JEDEC PARAMETER PARAMETER NAME NAME DESCRIPTION BS616LV2025-70 MIN. TYP. MAX. BS616LV2025-55 MIN. TYP. MAX. UNIT tAVAX tRC Read Cycle Time 70 -- -- 55 -- ns tAVQV tAA Address Access Time -- -- 70 -- 55 ns t E1LQV t ACS1 Chip Select Access Time (CE1) -- -- 70 -- -- 55 ns t E2LQV t ACS2 Chip Select Access Time (CE2) -- -- 70 -- -- 55 ns tBA tBA Data Byte Control Access Time (LB,UB) -- -- 35 -- -- 30 ns tGLQV tOE Output Enable to Output Valid -- -- 35 -- -- 30 ns tELQX tCLZ Chip Select to Output Low Z (CE1,CE2) 10 -- -- 10 -- -- ns tBE tBE Data Byte Control to Output Low Z (LB,UB) 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output in Low Z 10 -- -- 10 -- -- ns tEHQZ tCHZ Chip Deselect to Output in High Z (CE1,CE2) 0 -- 35 0 -- 30 ns tBDO tBDO Data Byte Control to Output High Z (LB, UB) 0 -- 35 0 -- 30 ns tGHQZ tOHZ Output Disable to Output in High Z 0 -- 30 0 -- 25 ns tAXOX tOH Output Disable to Address Change 10 -- -- 10 -- -- ns NOTE : 1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle . tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle . R0201-BS616LV2025 6 Revision 2.4 April 2002 BSI BS616LV2025 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE2 t ACS2 t ACS1 CE1 t (5) t (5) CLZ CHZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t CE2 t t CE1 t t t OE OH ACS2 OLZ t ACS1 (5) CLZ OHZ (5) (1,5) t CHZ t BDO LB, UB t BE t BA D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low and CE2 transition high. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 30pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS616LV2025 7 Revision 2.4 April 2002 BSI BS616LV2025 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION BS616LV2025-70 MIN. TYP. MAX. BS616LV2025-55 MIN. TYP. MAX. UNIT tAVAX tWC Write Cycle Time 70 -- -- 55 -- -- ns t E1LWH tCW Chip Select to End of Write 70 -- -- 55 -- -- ns tAVWL tAS Address Setup Time tAVWH tAW Address Valid to End of Write tWLWH tWP Write Pulse Width tWHAX tWR Write recovery Time tBW tBW Date Byte Control to End of Write tWLQZ tWHZ Write to Output in High Z tDVWH tDW tWHDX 0 -- -- 0 -- -- ns 70 -- -- 55 -- -- ns 35 -- -- 30 -- -- ns 0 -- -- 0 -- -- ns 30 -- -- 25 -- -- ns 0 -- 30 0 -- 25 ns Data to Write Time Overlap 30 -- -- 25 -- -- ns tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z 0 -- 30 0 -- 25 ns tWHOX tOW End of Write to Output Active 5 -- -- 5 -- -- ns (CE2, CE1,WE) (LB,UB) NOTE : 1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle . SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS t (3) WR OE CE2 (5) (11) t CW (5) CE1 t t WE BW (5) LB,UB (3) AW t WP t AS (2) (4,10) t OHZ D OUT t t DH DW D IN R0201-BS616LV2025 8 Revision 2.4 April 2002 BSI BS616LV2025 WRITE CYCLE2 (1,6) t WC ADDRESS CE2 (11) t (5) CE1 t BW (5) LB,UB t WE CW AW t t WP WR (3) (2) t DH t AS (4,10) t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 30pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write. R0201-BS616LV2025 9 Revision 2.4 April 2002 BSI BS616LV2025 ORDERING INFORMATION BS616LV2025 X X -- Y Y SPEED 70: 70ns 55: 55ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE A :BGA - 48 PIN(6x8mm) D :DICE PACKAGE DIMENSIONS (continued) NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.4 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. BALL PITCH e = 0.75 D E N D1 E1 8.0 6.0 48 5.25 3.75 E1 e D1 VIEW A 48 mini-BGA (6 x 8mm) R0201-BS616LV2025 10 Revision 2.4 April 2002 BSI BS616LV2025 REVISION HISTORY Revision Description Date 2.2 2001 Data Sheet release Apr. 15, 2001 2.3 Modify Standby Current (Typ. and Jun. 29, 2001 Max.) 2.4 Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 10uA to 25uA. R0201-BS616LV2025 11 Note April,15,2002 Revision 2.4 April 2002