MC10LVEP11, MC100LVEP11 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer Description The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single-ended CLK input operation is limited to a VCC w 3.0 V in PECL mode, or VEE v −3.0 V in NECL mode. The 100 Series contains temperature compensation. Features • 240 ps Typical Propagation Delay • Maximum Frequency > 3.0 GHz Typical • PECL Mode Operating Range: 8 8 1 1 SOIC−8 NB D SUFFIX CASE 751−07 TSSOP−8 DT SUFFIX CASE 948R−02 DFN−8 MN SUFFIX CASE 506AA MARKING DIAGRAMS* ♦ HVP11 ALYW G 1 1 8 8 KVP11 ALYW G 1 1 H K 5X 4K = MC10 = MC100 = MC10 = MC100 5X MG G • • Q Output Will Default LOW with Inputs Open or at VEE • LVDS Input Compatible • These Devices are Pb-Free, Halogen Free and are RoHS Compliant 8 8 HU11 ALYWG G 1 KU11 ALYWG G 1 4 4K MG G • VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: ♦ VCC = 0 V with VEE = −2.375 V to −3.8 V Open Input Default State www.onsemi.com 4 A = Assembly Location L = Wafer Lot Y= Year W = Work Week M = Date Code G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2016 August, 2016 − Rev. 14 1 Publication Order Number: MC10LVEP11/D MC10LVEP11, MC100LVEP11 Table 1. PIN DESCRIPTION Q0 Q0 Q1 1 8 2 7 3 PIN VCC D 6 FUNCTION D*, D** ECL Data Inputs Q0, Q0, Q1, Q1 ECL Data Outputs VCC Positive Supply VEE Negative Supply EP (DFN−8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. D *Pins will default to 2/3 VCC when left open. **Pins will default LOW when left open. Q1 4 5 VEE Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC−8 NB TSSOP−8 DFN−8 Pb-Free Pkg Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 110 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2 MC10LVEP11, MC100LVEP11 Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V Iout Output Current Continuous Surge 50 100 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−8 NB 190 130 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm TSSOP−8 185 140 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm DFN−8 129 84 °C/W Tsol Wave Solder (Pb-Free) <2 to 3 sec @ 260°C 265 °C qJC Thermal Resistance (Junction-to-Case) (Note 1) DFN−8 35 to 40 °C/W VI v VCC VI w VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) www.onsemi.com 3 MC10LVEP11, MC100LVEP11 Table 4. 10LVEP DC CHARACTERISTICS, PECL (VCC = 2.5 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 25 33 40 29 33 40 32 34 42 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VOL Output LOW Voltage (Note 2) 565 740 865 630 805 930 690 865 990 mV Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) 1.2 2.5 1.2 2.5 1.2 2.5 V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current D D 150 150 0.5 −150 0.5 −150 mA 0.5 −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V. 2. All loading with 50 W to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Single-Ended input CLK pin operation is limited to VCC w 3.0 V in PECL mode. Table 5. 10LVEP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 25 33 40 29 33 40 32 34 42 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 2) 1365 1540 1665 1430 1605 1730 1490 1665 1790 mV VIH Input HIGH Voltage (Single-Ended) (Note 3) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single-Ended) (Note 3) 1365 1690 1430 1755 1490 1815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 1.2 3.3 1.2 3.3 1.2 3.3 V 150 mA IIH Input HIGH Current IIL Input LOW Current D D 150 0.5 −150 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. 2. All loading with 50 W to VCC − 2.0 V. 3. Single-Ended input CLK pin operation is limited to VCC w 3.0 V in PECL mode. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 4 MC10LVEP11, MC100LVEP11 Table 6. 10LVEP DC CHARACTERISTICS, NECL (VCC = 0 V, VEE = −3.8 V to −2.375 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 25 33 40 29 33 40 32 34 42 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 2) −1935 −1760 −1635 −1870 −1695 −1570 −1810 −1635 −1510 mV VIH Input HIGH Voltage (Single-Ended) (Note 3) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single-Ended) (Note 3) −1935 −1610 −1870 −1545 −1810 −1485 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 0.0 V 150 mA IIH Input HIGH Current IIL Input LOW Current D D VEE+1.2 0.0 VEE+1.2 0.0 150 0.5 −150 VEE+1.2 150 0.5 −150 mA 0.5 −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. 2. All loading with 50 W to VCC − 2.0 V. 3. Single-Ended input CLK pin operation is limited to VEE v −3.0 V in NECL mode. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 7. 100LVEP DC CHARACTERISTICS, PECL (VCC = 2.5 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 25 35 42 29 38 46 32 41 50 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VOL Output LOW Voltage (Note 2) 555 730 900 555 730 900 555 730 900 mV VIH Input HIGH Voltage (Single-Ended) 1335 1620 1335 1620 1335 1620 mV VIL Input LOW Voltage (Single-Ended) 555 900 555 900 555 900 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) 1.2 2.5 1.2 2.5 1.2 2.5 V 150 mA IIH Input HIGH Current IIL Input LOW Current D D 150 0.5 −150 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V. 2. All loading with 50 W to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Single-Ended input CLK pin operation is limited to VCC w 3.0 V in PECL mode. www.onsemi.com 5 MC10LVEP11, MC100LVEP11 Table 8. 100LVEP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 25 35 42 29 38 46 32 41 50 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 2) 1355 1530 1700 1355 1530 1700 1355 1530 1700 mV VIH Input HIGH Voltage (Single-Ended) (Note 3) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single-Ended) (Note 3) 1355 1700 1355 1700 1355 1700 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 1.2 3.3 1.2 3.3 1.2 3.3 V 150 mA IIH Input HIGH Current IIL Input LOW Current D D 150 0.5 −150 150 0.5 −150 mA 0.5 −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. 2. All loading with 50 W to VCC − 2.0 V. 3. Single-Ended input CLK pin operation is limited to VCC w 3.0 V in PECL mode. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 9. 100LVEP DC CHARACTERISTICS, NECL (VCC = 0 V; VEE = −3.8 V to −2.375 V (Note 1)) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 25 35 42 29 38 46 32 41 50 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 2) −1945 −1770 −1600 −1945 −1770 −1600 −1945 −1770 −1600 mV VIH Input HIGH Voltage (Single-Ended) (Note 3) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single-Ended) (Note 3) −1945 −1600 −1945 −1600 −1945 −1600 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 0.0 V 150 mA IIH Input HIGH Current IIL Input LOW Current D D −1425 VEE+1.2 0.0 VEE+1.2 150 0.5 −150 −1425 0.0 VEE+1.2 150 0.5 −150 −1425 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. 2. All loading with 50 W to VCC − 2.0 V. 3. Single-Ended input CLK pin operation is limited to VEE ≤ −3.0 V in NECL mode. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 6 MC10LVEP11, MC100LVEP11 Table 10. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.8 V to −2.375 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 1)) −40°C Symbol Min Characteristic fmax Maximum Frequency (Figure 2) tPLH, tPHL Propagation Delay (Differential Configuration) CLK to Q, Q tSKEW Within Device Skew Device to Device Skew (Note 2) tJITTER CLOCK Random Jitter (RMS) @ v1.0 GHz @ v1.5 GHz @ v2.0 GHz @ v2.5 GHz @ v3.0 GHz VPP tr tf 25°C Max Min Typ 3 170 Q, Q 85°C Max Min 3 230 300 5.0 180 Typ Max 3 240 310 20 130 5.0 0.126 0.112 0.111 0.112 0.155 0.3 0.2 0.3 0.2 0.2 150 800 1200 70 110 170 Q, Q Input Voltage Swing (Differential Configuration) Output Rise/Fall Times (20% − 80%) Typ 210 Unit GHz 270 360 ps 20 130 5.0 20 150 ps 0.142 0.162 0.122 0.172 0.217 0.4 0.3 0.2 0.3 0.3 0.209 0.162 0.170 0.235 0.368 0.3 0.2 0.3 0.3 0.6 150 800 1200 150 800 1200 mV 80 120 180 100 140 200 ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 2. Skew is measured between outputs under identical transitions. 1000 3.3 V VOUTpp (mV) 900 2.5 V 800 700 600 500 400 300 200 100 0 0 1000 2000 FREQUENCY (MHz) Figure 2. Fmax Typical www.onsemi.com 7 3000 4000 MC10LVEP11, MC100LVEP11 Figure 3. Typical Phase Noise Plot at fcarrier = 156.25 MHz Figure 4. Typical Phase Noise Plot at fcarrier = 311.04 MHz Figure 5. Typical Phase Noise Plot at fcarrier = 1.5 GHz Figure 6. Typical Phase Noise Plot at fcarrier = 2 GHz device (integrated between 12 kHz and 20 MHz; as shown in the shaded region of the plot) at each of the frequencies is 66 fs, 37 fs, 14 fs and 13 fs respectively. The input source used for the phase noise measurements is Agilent E8663B. The above phase noise plots captured using Agilent E5052A show additive phase noise of the MC100LVEP11 device at frequencies 156.25 MHz, 311.04 MHz, 1.5 GHz and 2 GHz respectively at an operating voltage of 3.3 V in room temperature. The RMS Phase Jitter contributed by the www.onsemi.com 8 MC10LVEP11, MC100LVEP11 Zo = 50 W Q D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 7. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† MC10LVEP11DG SOIC−8 NB (Pb-Free) 98 Units / Rail MC10LVEP11DR2G SOIC−8 NB (Pb-Free) 2500 / Tape & Reel MC10LVEP11DTG TSSOP−8 (Pb-Free) 100 Units / Rail MC10LVEP11DTR2G TSSOP−8 (Pb-Free) 2500 / Tape & Reel MC100LVEP11DG SOIC−8 (Pb-Free) 98 Units / Rail MC100LVEP11DR2G SOIC−8 (Pb-Free) 2500 / Tape & Reel MC100LVEP11DTG TSSOP−8 (Pb-Free) 100 Units / Rail MC100LVEP11DTR2G TSSOP−8 (Pb-Free) 2500 / Tape & Reel MC100LVEP11MNR4G DFN−8 (Pb-Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 9 MC10LVEP11, MC100LVEP11 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices www.onsemi.com 10 MC10LVEP11, MC100LVEP11 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 11 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC10LVEP11, MC100LVEP11 PACKAGE DIMENSIONS TSSOP−8 CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF M T U V S 0.25 (0.010) B −U− 4 M A −V− S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E www.onsemi.com 12 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC10LVEP11, MC100LVEP11 PACKAGE DIMENSIONS DFN−8 2x2, 0.5P CASE 506AA ISSUE F D PIN ONE REFERENCE 2X 0.10 C 2X A B L1 ÇÇ ÇÇ ÇÇ 0.10 C DETAIL A E OPTIONAL CONSTRUCTIONS ÉÉ ÉÉ ÇÇ EXPOSED Cu TOP VIEW A DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉ ÉÉ ÇÇ A3 MOLD CMPD A1 DETAIL B 0.08 C (A3) NOTE 4 SIDE VIEW DETAIL A ALTERNATE CONSTRUCTIONS A1 D2 1 4 C 8X SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 RECOMMENDED SOLDERING FOOTPRINT* L 1.30 PACKAGE OUTLINE 8X 0.50 E2 0.90 K 8 5 e/2 e 8X b 1 0.10 C A B 0.05 C 2.30 8X NOTE 3 0.30 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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