ALSC ASM5CVF857 2.5v wide-range frequency clock driver (60mhz - 200mhz) Datasheet

August 2004
ASM5CVF857
rev 1.2
2.5V Wide-Range Frequency Clock Driver (60MHz – 200MHz)
condition and perform the same low power features as
Features
and when the PDB input is low. When the input
•
Low skew; low jitter PLL clock driver.
frequency increases to greater than approximately
•
1 to 10 differential clock distribution (SSTL_2).
20MHz, the PLL will be turned back on, the inputs and
•
Feedback pins for input to output synchronization.
outputs will be enabled, and the PLL will obtain phase
•
PDB for power management.
lock between the feedback clock pair (FB_INT,
•
Spread spectrum tolerant inputs.
FB_INC) and the input clock pair (CLK_INT, CLK_INC).
•
Auto-PD when input signal removed.
•
Choice of static phase offset for easy board tuning:
The PLL in the ASM5CVF857 clock driver uses the
• -XXX = device pattern number for options listed
input clocks (CLK_INT, CLKINC) and the feedback
below:
clocks (FB_INT, FB_INC) to provide high-performance,
• PCV857-025 - 0 ps
low-skew, low-jitter output differential clocks (CLKT[0:9],
• PCV857-1300 - +50 ps
CLKC[0:9]). ASM5CVF857 is also able to track spread
spectrum clock (SSC) for reduced EMI.
Product Description
This PLL clock buffer is designed for a VDD of 2.5V,
AVDD of 2.5V and differential data input and output
levels.
ASM5CVF857 is a zero-delay buffer that
ASM5CVF857 is characterized for operation from 0°C
to 85°C.
Applications
distributes a differential clock input pair (CLK_INT,
CLK_INC) to ten differential pairs of clock outputs
(CLKT[0:9], CLKC[0:9]) and one differential
•
Out.
pair
feedback clock output (FB_OUT, FB_OUTC). The clock
DDR Memory Modules / Zero Delay Board Fan
•
Provides complete DDR DIMM logic solution with
outputs are controlled by the input clocks (CLK_INT,
ASM4SSTVF16857, ASM4SSTVF16859 &
CLKINC), the feedback clocks (FB_INT, FB_INC), the
ASM4SSTVF32852.
2,5V LVCMOS input (PDB), and the analog power input
(AVDD). When input (PDB) is low while power is applied,
Specifications
the receivers are disabled, the PLL is turned off, and
•
Meets PC3200 specification for DDR-I 400 support.
the differential clock outputs are tri-stated. When AVDD
•
Covers all DDRI speed grades.
is grounded, the PLL is turned off and bypassed for test
purposes.
Switching Characteristics
When the input frequency is less than the operating
•
CYCLE-CYCLE jitter : <50ps.
frequency of the PLL, approximately 20MHz, the device
•
OUT-OUTPUT skew: <40ps.
will enter a low power mode. An input frequency
•
Period jitter: ±30ps.
detection circuit on the differential inputs, independent
from the input buffers, will detect the low frequency
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
1 of 15
August 2004
ASM5CVF857
rev 1.2
Block Diagram
F B_O UTT
F B_O UTC
AVDD
PDB
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
Control
Logic
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
C L KC 9
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_IN T
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ASM5CVF857
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
PDB
FB_INT
FB_INC
VDD
FB_OUT C
FB_OUT T
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
2 of 15
August 2004
ASM5CVF857
rev 1.2
GND
CLKC2
CLKT2
VDD
CLK_IN
CLK_INC
VDD
AVDD
AGND
GND
CLKT6
CLKC7
CLKT7
VDD
PDB
FB_INT
FB_INC
VDD
VDD
FB_OUTC
FB_OUTT
ASM5CVF857
CLKC3
CLKT3
56-BALL BGA
(SEE TABLE BELOW)
CLKT8
A
B
C
D
E
F
G
H
J
K
CLKC5
CLKT5
VDD
CLKC6
6
CLKC9
CLKT9
VDD
CLKC8
5
VDD
4
CLKT0
CLKC0
3
VDD
2
CLKT4
CLKC4
1
CLKC1
CLKT1
56-BALL BGA
40-PIN MLF
1
2
3
4
5
6
A
CLKT0
CLKC0
GND
GND
CLKC5
CLKT5
B
CLKC1
CLKT1
VDD
VDD
CLKT6
CLKC6
C
GND
GND
NC
NC
GND
GND
D
CLKT2
CLKC2
NC
NC
CLKC7
CLKC7
E
VDD
VDD
NB
NB
VDD
PDB
F
CLK_INT
CLK_INC
NB
NB
FB_INC
FB_INT
G
VDD
AVDD
NC
NC
FB_OUTC
VDD
H
AGND
GND
NC
NC
GND
FB_OUTT
J
CLKC3
CLKT3
VDD
VDD
CLKT8
CLKC8
K
CLKT4
CLKC4
GND
GND
CLKC9
CLKT9
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
3 of 15
August 2004
ASM5CVF857
rev 1.2
Pin Description
Pin Number
Pin Name
Pin
Type
4, 11, 12, 15, 21, 28, 34, 38, 45
VDD
P
Power supply, 2.5V
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
GND
P
Ground.
16
AVDD
P
Analog power supply, 2.5V.
17
AGND
P
Analog ground.
27, 29, 39, 44, 46, 22, 20, 10, 5, 3
CLKT(9:0)
O
“True” clock of differential pair outputs.
26, 30, 40, 43, 47, 23, 19, 9, 6, 2
CLKC(9:0)
O
“Complementary” clocks of differential pair outputs.
14
CLK_INC
I
“Complementary” reference clock input.
13
CLK_INT
I
“True” reference clock input.
33
FB_OUTC
O
“Complementary” feedback output dedicated for external
feedback. It switches at the same frequency as the CLK. This
output must be wired to FB_INC.
32
FB_OUTT
O
“True” feedback output dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be
wired to FB_INT.
36
FB_INT
I
“True” feedback input provides feedback signal to the internal
PLL for synchronization with CLK_INT to eliminate phase error.
35
FB_INC
I
“Complementary” feedback input provides signal to the internal
PLL for synchronization with CLK_INC to eliminate phase error.
37
PDB
I
Power down. LVCMOS input.
Pin Description
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
4 of 15
August 2004
ASM5CVF857
rev 1.2
Functionality
Inputs
Outputs
PLL State
AVDD
PDB
CLK_INT
CLK_INC
CLKT
CLKC
FB_OUTT
FB_OUTC
GND
H
L
H
L
H
L
H
Bypassed/Off
GND
H
H
L
H
L
H
L
Bypassed/Off
2.5V (nom)
L
L
H
Z
Z
Z
Z
off
2.5V (nom)
L
H
L
Z
Z
Z
Z
off
2.5V (nom)
H
L
H
L
H
L
H
on
2.5V (nom)
H
H
L
H
L
H
L
on
2.5V (nom)
X
Z
Z
Z
Z
off
<20 MHz
Absolute Maximum Ratings
Parameter
Supply voltage (VDD and AVDD)
Logic Inputs
Ambient Operating Temperature
Storage Temperature
Min
Max
Unit
-0.5
3.6
V
GND - 0.5
VDD + 0.5
V
0
85
ûC
-65
150
ûC
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for
prolonged periods may affect device reliability.
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
5 of 15
August 2004
ASM5CVF857
rev 1.2
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0°76C to 85°C. Supply voltage AVDD and VDD=2.5V ± 0.2V (unless otherwise stated).
Parameter
Symbol
Conditions
Input high current
IIH
VI = VDD or GND
Input low current
IIL
VI = VDD or GND
IDDQ
CL = 0pF, RL = 120, FCLK_IN = 200MHz
IDDPD
PDB = GND, FCLK_IN=0MHz
Supply Current on
AVDD
IADD
FCLK_IN = 200MHz
Input clamp voltage
VIK
VDDQ=2.3V IIN = -18mA
High-level output
voltage
VOH
Operating supply
current
Low-level output
voltage
Min
Typ
Max
5
Units
µA
5
µA
310
mA
100
200
µA
9
12
mA
-1.2
V
IOH = -100µA
VDD-0.1
V
IOH = -12mA
1.7
V
IOL = 100µA
0.1
V
IOL = 12mA
0.6
V
2
3.5
pF
-0.25
0.25
pF
VOL
Input capacitance*
CIN
VI = GND or VDD
Input capacitance
variation
CI(
VOUT = GND or VDD
* Guaranteed by design at 200MHz; not 100% tested in production.
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
6 of 15
August 2004
ASM5CVF857
rev 1.2
Recommended Operating Conditions
TA = 0°C to 85°C. Supply voltage AVDD and VDD=2.5V ± 0.2V (unless otherwise stated).
Parameter**
Symbol
Conditions
Supply Voltage
VDD, AVDD
Low level input
voltage
VIL
CLK_INT, CLK_INC, FB_INT,
FB_INC
VIH
CLK_INT, CLK_INC, FB_INT,
FB_INC
High level input
voltage
PDB
DC input signal
voltage#
Differential input
signal voltage$
Typ
Max
Unit
2.3
2.5
2.7
V
0.4
VDD/2 - 0.18
V
VDD/2 + 0.18
2.1
V
1.7
VDD + 0.3
V
-0.3
VDD + 0.3
V
DC: CLK_INT, CLK_INC, FB_INT,
FB_INC
0.36
VDD + 0.6
V
AC: CLK_INT, CLK_INC, FB_INT,
FB_INC
0.7
VDD + 0.6
V
VIN
VID
Min
Output differential
@
cross voltage
VOX
VDD/2 - 0.15
VDD/2 + 0.15
V
Input differential
cross voltage
VIX
VDD/2 - 0.2
VDD/2 + 0.2
V
High-level output
current
IOH
-12
mA
Low-level output
current
IOL
12
mA
Operating free-air
temperature
TA
85
°C
0
**: Unused inputs must be held high or low to prevent them from floating.
#: DC input signal voltage specifies the allowable DC execution of differential
$: Differential inputs signal voltages specify the differential voltage [VTR-VCP] required for switching where VTR is the true input
level and VCT is the complementary input level.
@: Differential cross-point voltage is expected to track variations of V DD and is the voltage at which the differential signal must be
crossing.
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
7 of 15
August 2004
ASM5CVF857
rev 1.2
Timing Requirements**
Parameter
Symbol
Conditions
Min
Max
Units
Operating clock frequency
freqop
2.5V ± 0.2V
60
220
MHz
Application Frequency Range
freqapp
2.5V ± 0.2V
95
220
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
100
µs
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
8 of 15
August 2004
ASM5CVF857
rev 1.2
Switching Characteristics**
Parameter
Symbol
Low-to-high level propagation delay time
tPLH
High-to-low level propagation delay time
tPHL
Conditions
Min
Typ
Max
Units
*
CLK_IN to any output
3.5
ns
*
CLK_IN to any output
3.5
ns
Output enable time
ten
PDB to any output
3
ns
Output disable time
tdis
PDB to any output
3
ns
Period Jitter
tjit(per)
100MHz to 200MHz
-30
30
ps
Half-period jitter
tjit(hper)
100MHz to 200MHz
-75
75
ps
1
4
v/ns
Input clock slew rate
tsl(I)
Output clock slew rate
tsl(o)
100/133/167/200 MHz
1
2
v/ns
Cycle-to-cycle jitter
tcyc-tcyc
100 MHz to 200MHz
-50
50
ps
Static phase offset
t(phase error)#
0
50
ps
40
60
ps
Output-to-output skew
-50
tskew
The PLL on the ASM5CVF857 is capable of meeting all the above parameters while supporting SSC synthesizers with
the following parameters.
SSC modulation frequency
30.00
50.00
kHz
SSC clock input frequency deviation
0.00
-0.50
%
PLL loop bandwidth
2
Phase angle
MHz
-0.031
*: Refers to transition on non-inverting output in PLL bypass mode.
#: Static phase offset does not include jitter.
** TA = 0 û 85úC. Supply voltage AVDD, VDD=2.5V ± 0.2V (unless otherwise stated).
Note: While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This
is due to the formula: duty cycle = tWH/tC where the cycle (tC) decreases as the frequency goes up.
Note: Switching characteristics guaranteed for application frequency range.
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
9 of 15
°
August 2004
ASM5CVF857
rev 1.2
Parameter Measurement Information
V DD
V( C L K T )
R = 60
R = 60
VDD /2
V( C L K C )
ASM5CVF857
GND
Figure 1: IBIS Model Output Load
VDD /2
SCOPE
ASM5CVF857
Z=60
C = 14 pF
-VDD /2
R = 10 
Z=50
R = 10 
Z=60
R = 50 
V TT
Z=50
R = 50 
C = 14 pF
VTT
-VDD /2
-VDD /2
Note: V TT = GND
Figure 2: Output Load Test Circuit
VDD
SCOPE
ASM5CVF857
C = 14 pF
GND
Z=60
R = 1 M
Z=120
VTT
Z=60
C = 14 pF
VTT
GND
GND
C = 1 pF
R = 1 M
C = 1 pF
Note: V TT = GND
Figure 3: Output Load Test Circuit for Crossing Point
YX , FB_OUTC
YX , FB_OUTT
tc(n)
tc(n+1)
tjit(cc) = tc(n) ± tc(n+1)
Figure 4: Cycle-to-Cycle Jitter Period
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
10 of 15
August 2004
ASM5CVF857
rev 1.2
CLK_INC
CLK_INT
FB_INC
FB_INT
t(  n
t(  n+1
(N > 1000 samples)
Figure 5: Static Phase Offset
YX
YX
YX , FB_OUTC
YX, FB_OUTT
t (skew)
Figure 6: Output Skew
YX, FB_OUTC
YX, FB_OUTT
tc(n)
YX, FB_OUTC
YX, FB_OUTT
fo= average input frequency measured at CLK_INT/CLK_INC
Figure 7: Period Jitter
YX , FB_OUTC
YX , FB_OUTT
t half period n
thalf period n+1
n = any half cycle
fo= average input frequency measured at CLK_INT/CLK_INC
Figure 8: Half-Period Jitter
80%
80%
VID ,VOD
Clock inputs and outputs
20%
tr(i) , tr(o)
20%
tf(i) , tf(o)
Figure 9: Input and Output Slew rates
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
11 of 15
August 2004
ASM5CVF857
rev 1.2
Package Dimensions (6.10mm (240 mil) body, 0.50mm (0.020 mil) pitch TSSOP)
C
N
L
E1
E
Index Area
1 2
D

A2
A1
A
D
Seating
Plane
e
aaa C
b
Dimensions (mm)
Dimensions (inches)
Symbol
Min
Max
Min
Max
A
-
1.20
-
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.32
0.041
b
0.17
0.27
0.007
0.011
c
0.09
0.20
0.0035
0.008
D
See Variations
E
E1
8.10 Basic
6.00
e
L
0.319 Basic
6.20
0.236
0.50 Basic
0.45
0.244
0.20 Basic
0.75
0.018
0.030
D (MM)
N
D(inch)
See Variations

0°
8°
0°
8°
aaa
-
0.10
-
0.004
48
Min
Max
Min
Max
12.40
12.60
0.488
0.496
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
12 of 15
August 2004
ASM5CVF857
rev 1.2
Package Dimensions (4.40mm (1713 mil) body, 0.40 mm (16 mil) pitch TVSOP)
C
N
L
E1
E
Index Area
1 2
D

A2
A1
A
Seating Plane
D
e
aaa
C
b
Symbol
Dimensions (mm)
Dimensions (inches)
Min
Max
Min
Max
A
-
1.20
-
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.32
0.041
b
0.17
0.27
0.007
0.011
c
0.09
0.20
0.0035
0.008
D
See Variations
E
E1
8.10 Basic
6.00
e
L
0.319 Basic
6.20
0.236
0.50 Basic
0.45
N
0.244
0.20 Basic
0.75
0.018
0.030
N
See Variations

0°
8°
0°
8°
aaa
-
0.10
-
0.004
48
D (MM)
D(inch)
Min
Max
Min
Max
12.40
12.60
0.488
0.496
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
13 of 15
August 2004
ASM5CVF857
rev 1.2
Ordering Codes
Ordering Number
Marking
Package Type
ASM5CVF857-48TT
AS5CVF857T
48-pin TSSOP, tube
ASM5CVF857-48TR
AS5CVF857T
48-pin TSSOP, tape & reel
ASM5CVF857-48VT
AS5CVF857V
48-pin TVSOP, tube
ASM5CVF857-48VR
AS5CVF857V
48-pin TVSOP, tape & reel
ASM5CVF857-56BT
AS5CVF857B
56-pin Ball BGA, tube
ASM5CVF857-56BR
AS5CVF857B
56-pin Ball BGA, tape & reel
ASM5CVF857-40QT
AS5CVF857M
40-pin QFN, tube
ASM5CVF857-40QR
AS5CVF857M
40-pin QFN, tape & reel
Quantity Per Reel
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
Temperature
0°C to 70°C
2500
0°C to 70°C
0°C to 70°C
2500
0°C to 70°C
0°C to 70°C
2500
0°C to 70°C
0°C to 70°C
2500
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0°C to 70°C
August 2004
ASM5CVF857
rev 1.2
Alliance Semiconductor Corporation
2595, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright ÿ Alliance Semiconductor
All Rights Reserved
Advance Information
Part Number: ASM5CVF857
Document Version: v1.1
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and
Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective companies. Alliance reserves the right to make changes to this document and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this
document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance.
Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is
under development, significant changes to these specifications are possible. The information in this product data
sheet is intended to be general descriptive information for potential customers and users, and is not intended to
operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any
responsibility or liability arising out of the application or use of any product described herein, and disclaims any
express or implied warranties related to the sale and/or use of Alliance products including liability or warranties
related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as
express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance
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intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
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manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
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