AS1710/AS1712 D a ta S he e t High-Output-Drive, 10MHz, 10V/µs, Rail-to-Rail I/O O p A m ps w i t h S h u td o w n 1 General Description 2 Key Features The AS1710/AS1712 are low-offset, high-output CMOS op amps that deliver 200mA of peak output current from a single supply (2.7 to 5.5V). These devices were specifically designed to drive typical headset levels (32Ω), as well as bias RF power amplifiers for wireless handset applications. The devices are available as the standard products shown in Table 1. See also Ordering Information on page 16. Table 1. Standard Products Model Description Package AS1710A Single Op Amp with Shutdown SC70-6 AS1710B Single Op Amp SC70-5 AS1712A Quad Op Amp w/Shutdown TQFN-16 3x3mm ! Constant Output Drive Capability: 50mA ! Rail-to-Rail Input and Output ! Supply Current: 1.6mA ! Single-Supply Operation: 2.7 to 5.5V ! Gain-Bandwidth Product: 10MHz ! High Slew Rate: 10V/µs ! Voltage Gain: 100dB (RLOAD = 100kΩ) ! Power-Supply Rejection Ratio: -85dB ! No Phase Reversal for Overdriven Inputs ! Unity-Gain Stable for Capacitive Loads: Up to 100pF ! Shutdown Mode (AS1710A) Current: 1nA typ ! Package Types: - SC70-6 - SC70-5 - TQFN-16 3x3mm These rail-to-rail I/O, wide-bandwidth amplifiers exhibit a high slew rate of 10V/µs and a gain-bandwidth product of 10MHz. The integrated shutdown feature (not included in B versions) drives the output low. These devices operate over the entire automotive temperature range (-40°C to +125°C). 3 Applications The devices are ideal for portable/battery-powered audio applications, portable headphone speaker drivers (32Ω), hands-free mobile phone kits, TFT panels, sound ports/cards, set-top boxes, biasing controls, DAC converter buffers, transformer/line drivers, motor drivers, and any other battery-operated audio device. Figure 1. Typical Application RF Audio In Left CIN RIN – AS1710 COUT + Headphone Jack to 32Ω Stereo Headset + VBIAS + AS1710 Audio In Right CIN COUT + – RIN RF www.austriamicrosystems.com Revision 1.04 1 - 17 AS1710/AS1712 Data Sheet - P i n o u t 4 Pinout Pin Assignments Figure 2. Pin Assignments (Top View) IN+ 1 AS1710-A SC70-6 5 SHDNN VSS 2 IN1+ 1 VDD 2 IN2+ 3 5 VDD AS1710-B SC70-5 4 OUT 13 IN4- IN- 3 14 OUT4 4 OUT 16 IN1- IN- 3 IN+ 1 15 OUT1 VSS 2 6 VDD 12 IN4+ AS1712-A TQFN-16 3x3mm 10 IN3+ OUT3 8 SHDNN3/4 7 SHDNN1/2 6 9 IN3OUT2 5 IN2- 4 11 VSS Pin Descriptions Table 2. Pin Descriptions Pin Number See Figure 2 Pin Name IN+ INVDD VSS SHDNN OUT www.austriamicrosystems.com Description Non-inverting Input Inverting Input Positive Supply Input Negative Supply Input. This pin must be connected to ground in single-supply applications. Active Low Shutdown Control Amplifier Output Revision 1.04 2 - 17 AS1710/AS1712 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Parameter Min Supply Voltage (VDD to VSS) Supply Voltage (All Other Pins) VSS - 0.3 Output Short-Circuit Duration to VDD or VSS Max Units +7 V VDD + 0.3 V 1 s Continuous Power Dissipation SC70-5 247 SC70-6 245 Thermal Resistance ΘJA TQFN-16 3x3mm 33 ºC/W +125 ºC +150 ºC +150 ºC Operating Temperature Range -40 Storage Temperature Range -65 Junction Temperature Package Body Temperature www.austriamicrosystems.com +260 mW ºC Revision 1.04 Comments Derate at 31mW/ºC above 70ºC Derate at 31mW/ºC above 70ºC on PCB The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). 3 - 17 AS1710/AS1712 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics DC Electrical Characteristics VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RLOAD = Infinite, VSHDNN = VDD, TAMB = -40 to +125ºC. Typical values at TAMB = 25°C. Table 4. DC Electrical Characteristics Symbol Parameter Condition Min VDD Supply Voltage Range Inferred from Power Supply Rejection Ratio Test 2.7 VOFFSET Input Offset Voltage -3 Typ 0.6 Max Unit 5.5 V +3 mV 1 pA 1 pA IBIAS Input Bias Current VCM = VSS to VDD 50 IOFFSET Input Offset Current VCM = VSS to VDD 50 RIN Input Resistance VCM Common Mode Input Voltage Range Inferred from Common Mode 1 Rejection Ratio VSS CMRR Common Mode Rejection Ratio VSS < VCM < VDD -45 -70 dB PSRR Power Supply Rejection Ratio VDD = 2.7 to 5.5V -70 -85 dB 1000 VSHDNN = 0V (A-Versions) 130 VOUT-SHDNN Shutdown Output Voltage VSHDNN = 0V, RLOAD = 2kΩ to VDD (A-Versions) 170 VOUT Large Signal Voltage Gain Output Voltage Swing Output Voltage IOUT Output Source/Sink Current IDD Quiescent Supply Current per OpAmp Output IDD-SHDNN Shutdown Supply Current per OpAmp (A-Versions) SHDNN Logic Threshold (A-Versions) SHDNN Input Bias Current VDD - VOH or VOL - VSS VDD - VOH or VOL - VSS V Ω 1 Shutdown Output Impedance AVOL MΩ VDD ROUT VSS + 0.20V < VOUT < VDD - 0.20V 1 RLOAD = 100kΩ 85 100 RLOAD = 2kΩ 79 92 RLOAD = 200Ω 69 80 300 mV dB RLOAD = 32Ω 350 650 RLOAD = 200Ω 70 120 RLOAD = 2kΩ 9 20 ILOAD = 10mA, VDD = 2.7V 55 100 ILOAD = 30mA, VDD = 5V 100 180 mV mV VDD = 2.7V, V- = VCM, V+ = VCM±100mV 100 VDD = 5.0V, V- = VCM, V+ = VCM±100mV 200 VDD = 2.7V, VCM = VDD/2 1.6 3.2 VDD = 5.0V, VCM = VDD/2 2.3 4.6 1 2000 VSHDNN = 0V VDD = 2.7V mA mA 1 Shutdown Mode VSS + 0.3 Normal Operation VDD 0.3 VSS < VSHDNN < VDD (A-Versions) 50 1 nA V pA 1. Guaranteed by design. www.austriamicrosystems.com Revision 1.04 4 - 17 AS1710/AS1712 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s AC Electrical Characteristics VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RLOAD = Infinite, VSHDNN = VDD, TAMB = -40 to +125ºC. Typical values at TAMB = 25°C. Table 5. AC Electrical Characteristics Symbol Parameter Conditions GBWP Gain-Bandwidth Product VCM = VDD/2 10 MHz FPBW Full-Power Bandwidth VOUT = 2VP-P, VDD = 5V 2.5 MHz SR Slew Rate 10 V/µs PM Phase Margin 70 deg GM Gain Margin 1 15 dB 0.05 % 6 pF THD+N Total Harmonic Distortion Plus Noise CIN Input Capacitance en Voltage-Noise Density 1 Capacitive-Load Stability f = 10kHz, VOUT = 2VP-P, AVCL = 1V/V Min Typ Max Units f = 1kHz 15 f = 10kHz 10 √Hz AVCL = 1V/V, no sustained oscillations 100 pF nV/ tSHDN Shutdown Time (AS1710A) 1 µs tENABLE Enable Time from Shutdown (AS1710A) 7 µs tON Power-Up Time 20 ns 1. Guaranteed by design. www.austriamicrosystems.com Revision 1.04 5 - 17 AS1710/AS1712 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics VDD = 2.7V; VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RLOAD = ∞, VSHDNN = VDD TAMB = +25ºC (unless otherwise specified). Figure 3. Gain and Phase vs. Frequency Figure 4. Gain and Phase vs. Frequency, CLOAD = 100pF 120 320 120 320 Gain 280 80 240 80 240 60 200 Phase 40 160 20 120 0 -20 -40 0.001 0.1 10 1000 Gain (dB) . 100 Phase (deg) 280 Gain (dB) . 100 60 200 Phase 40 160 20 120 80 0 80 40 -20 40 0 100000 -40 0.001 0.1 Frequency (kHz) 0 -10 -10 -20 -20 -30 -30 CMRR (dB) . PSRR (dB) . 0 100000 Figure 6. CMRR vs. Frequency 0 -40 -50 -60 -70 -40 -50 -60 PSRR neg -80 -90 PSRR pos -90 10 CMRR -70 -80 0.1 1000 Frequency (kHz) Figure 5. PSRR vs. Frequency -100 0.001 10 Phase (deg) Gain -100 0.001 1000 0.1 Frequency (kHz) 10 1000 Frequency (kHz) Figure 7. Supply Current vs. Temperature Figure 8. Shutdown Current vs. Temperature 1000 4 Shutdown Current (nA) Supply Current (mA) . . 3.5 3 5V 2.5 2 2.7V 1.5 1 100 10 1 0.5 0 -45 -20 5 30 55 80 105 130 0.1 -45 www.austriamicrosystems.com -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) Revision 1.04 6 - 17 AS1710/AS1712 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 9. Supply Current vs. Common-Mode Voltage 3 Figure 10. Input Voltage Noise vs. Frequency 2.5 Input Voltage Noise (nV/Hz) Supply Current (mA) . . 1000 5V 2 1.5 2.7V 1 0.5 100 10 0 0 1 2 3 4 1 0.001 5 0.1 Common-Mode Voltage (V) 10 1000 Frequency (kHz) Figure 11. Output Voltage vs. Output Current, sourcing Figure 12. Output Voltage vs. Output Current, sinking 5 1.75 5V 4.5 1.5 t>10s 3.5 3 2.7V 2.5 2 1.5 Output Voltage (V) . Output Voltage (V) . t<1s 4 t>10s 1.25 1 50 100 t<1s 0.75 0.5 0.25 t>10s 0 t<1s 2.7V t<1s 1 0.5 t>10s 5V 0 150 200 250 0 50 Output Current (mA) Figure 13. Output Swing High vs. Temperature 90 VOUT - VSS (mV) . 90 VOUT - VSS (mV) . 100 80 200Ω 70 10mA 50 40 -45 150 200 Figure 14. Output Swing Low vs. Temperature 100 60 100 Output Current (mA) 80 200Ω 70 60 10mA 50 -20 5 30 55 80 105 130 40 -45 Temperature (°C) www.austriamicrosystems.com -20 5 30 55 80 105 130 Temperature (°C) Revision 1.04 7 - 17 AS1710/AS1712 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s OUT OUT 50mV/DIV IN Figure 16. Transient Response, 100mV, 100pF load 50mV/DIV IN Figure 15. Transient Response, 100mV, 10pF load 500ns/Div 500ns/Div Figure 18. Transient Response, 1V, 100pF load 500mV/DIV OUT OUT 500mV/DIV IN IN Figure 17. Transient Response, 1V, 10pF load 500ns/Div 500ns/Div Figure 20. Transient Response, 2V, 100pF load 1V/DIV OUT OUT 1V/DIV IN IN Figure 19. Transient Response, 2V, 10pF load 500ns/Div www.austriamicrosystems.com 500ns/Div Revision 1.04 8 - 17 AS1710/AS1712 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 8 Application Information Package Power Dissipation Caution: Due to the high output current drive, this op amp can exceed the absolute maximum power-dissipation rating. Normally, when peak current is less than or equal to 40mA the maximum package power dissipation is not exceeded for any of the package types offered. The absolute maximum power-dissipation rating of each package should always be verified. (EQ 1) gives an approximation of the package power dissipation: PPACKAGEDISS ≅ VRMS IRMS COSθ (EQ 1) Where: VRMS is the RMS voltage from VDD to VOUT when sourcing current, and from VOUT to VSS when sinking current. IRMS is the RMS current flowing in or out of the op amp and the load. θ is the phase difference between the voltage and the current. For resistive loads, COSθ = 1. Figure 21. Typical AS1710/AS1712 Single-Supply Application 3.6V R C + VIN = 2VP-P R AS1710 – 32Ω VRMS can be calculated as: VRMS ≅ (VDD - VDC) + VPEAK /√2 (EQ 2) Where: VDC is the DC component of the output voltage. VPEAK is the highest positive excursion of the AC component of the output voltage. For the circuit shown in Figure 21: VRMS = (3.6V - 1.8V) + 1.0V/√2 = 2.507VRMS IRMS can be calculated as: IRMS ≅ IDC + (IPEAK/√2) (EQ 3) Where: IDC is the DC component of the output current. IPEAK is the highest positive excursion of the AC component of the output current. For the circuit shown in Figure 21: IRMS = (1.8V/32Ω) + (1.0V/32Ω)/√2 = 78.4mARMS Therefore, for the circuit in Figure 21 the package power dissipation can be calculated as: PPACKAGEDISS = VRMS IRMS COSθ = 196mW Adding a coupling capacitor improves the package power dissipation because there is no DC current to the load, as shown in Figure 22 on page 10. www.austriamicrosystems.com Revision 1.04 9 - 17 AS1710/AS1712 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 60mW Single-Supply Stereo Headphone Driver Two AS1710 amplifiers can be used as a single-supply, stereo headphone driver. The circuit shown in Figure 22 can deliver 60mW per channel with 1% distortion from a single 5V supply. Figure 22. Stereo Headphone Driver Application (with Coupling Capacitor) RF Audio In Left CIN RIN – AS1710 COUT + Headphone Jack to 32Ω Stereo Headset + VBIAS + AS1710 Audio In Right COUT + – CIN RIN RF In Figure 22, CIN and RIN form a high-pass filter that removes the DC bias from the incoming signal. The -3dB point of the high-pass filter is given by: f-3dB = 1/(2πRINCIN) (EQ 4) Choose gain-setting resistors RIN and RF according to the amount of desired gain, keeping in mind the maximum output amplitude. COUT blocks the DC component of the amplifier output, preventing DC current flowing to the load. The output capacitor and the load impedance form a high-pass filter with the -3dB point determined by: f-3dB = 1/(2πRLOADCOUT) (EQ 5) For a 32Ω load, a 100µF aluminum electrolytic capacitor gives a low-frequency pole at 50Hz. Rail-to-Rail Input Stage The AS1710/AS1712 CMOS op amps have parallel connected N- and P-channel differential input stages that combine to accept a common-mode range extending to both supply rails. The N-channel stage is active for common-mode input voltages typically greater than (VSS + 1.2V), and the p-channel stage is active for common-mode input voltages typically less than (VDD - 1.2V). Rail-to-Rail Output Stage The minimum output is within millivolts of ground for single- supply operation, where the load is referenced to ground (VSS). Figure 23 shows the input voltage range and the output voltage swing of an AS1710 connected as a voltage follower. The maximum output voltage swing is load dependent although it is guaranteed to be within 500mV of the positive rail (VDD = 2.7V) even with maximum load (32Ω to ground). www.austriamicrosystems.com Revision 1.04 10 - 17 AS1710/AS1712 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Figure 24. Rail-to-Rail Input/Output Range, 32Ω OUT OUT 1V/DIV 1V/DIV IN IN Figure 23. Rail-to-Rail Input/Output Range, 100kΩ VCC = 3.0V, RLOAD = 100kΩ VCC = 3.0V, RLOAD = 32Ω 2.5µs/Div 2.5µs/Div Note: The absolute maximum ratings (see page 3) for power dissipation and output short-circuit duration (10s, max) must be adhered to since the output current can exceed 200mA (see Typical Operating Characteristics on page 6). Input Capacitance The parallel-connected differential input stages for rail-to-rail operation results in relatively large input capacitance CIN (6pF typ). This introduces a pole at frequency (2πR′CIN)-1, where R′ is the parallel combination of the gain-setting resistors for the inverting or non-inverting amplifier configuration (Figure 25). If the pole frequency is less than or comparable to the unity-gain bandwidth (10MHz), the phase margin is reduced, and the amplifier exhibits degraded AC performance through either ringing in the step response or sustained oscillations. Figure 25. Inverting and Non-inverting Amplifiers with Feedback Compensation Inverting CF R′ = R II RF RFCF = RCIN Non-Inverting + VIN RF AS1710 R VIN VOUT – – AS1710 VOUT RF + CF R The pole frequency is 10MHz when R′ = 2kΩ. To maximize stability, R′ << 2kΩ is recommended. To improve step response when R′ > 2kΩ, connect a small capacitor (CF) between the inverting input and output. CF can be calculated by: CF = 6(R/RF) [pf] (EQ 6) Where: RF is the feedback resistor. R is the gain-setting resistor. www.austriamicrosystems.com Revision 1.04 11 - 17 AS1710/AS1712 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Driving Capacitive Loads The AS1710/AS1712 amplifiers have a high tolerance for capacitive loads, and are stable with capacitive loads up to 100pF. Figure 26 shows a typical non-inverting capacitive-load driving circuit in the unity-gain configuration. Figure 26. Capacitive-Load Driving Circuit – RISO AS1710 + CF Note: Resistor RISO improves the circuit’s phase margin by isolating the load capacitor from the AS1710/AS1712 output. Power-Up The AS1710/AS1712 typically settle within 5µs after power-up. Shutdown When SHDNN (not included in B versions) is pulled low, supply current drops to 0.5µA (per amplifier, VDD = 2.7V), the amplifiers are disabled, and their outputs are driven to VSS. Because the outputs are actively driven to VSS in shutdown, any pullup resistor on the output causes a current drain from the supply. Note: Pulling SHDNN high enables the amplifier. In the AS1712 the amplifiers shutdown in pairs. When exiting shutdown, there is a 6µs delay before the amplifier output becomes active. Power Supplies and Layout The AS1710/AS1712 can operate from a single 2.7 to 5.5V supply or from dual ±1.35 to ±2.5V supplies. Good design improves device performance by decreasing the amount of stray capacitance at the op amp inputs/outputs. ! For single-supply operation, bypass the power supply with a 0.1µF ceramic capacitor. ! For dual-supply operation, bypass each supply to ground. ! Decrease stray capacitance by placing external components close to the op amp pins, minimizing trace and lead lengths. www.austriamicrosystems.com Revision 1.04 12 - 17 AS1710/AS1712 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 9 Package Drawings and Markings Figure 27. SC70-5 Package Notes: 1. 2. 3. 4. All dimensions are in millimeters. Dimensions are inclusive of plating. Dimensions are exclusive of mold flash and metal burr. All specifications comply with JEITA SC88A and JEDEC MO203. www.austriamicrosystems.com Revision 1.04 Symbol e D b E HE Q1 A2 A1 A c L Lj Min Max 0.65BSC 1.80 2.20 0.15 0.30 1.15 1.35 1.80 2.40 0.10 0.40 0.80 1.00 0.00 0.10 0.80 1.10 0.10 0.18 0.10 0.30 0.26 0.46 13 - 17 AS1710/AS1712 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s Figure 28. SC70-6 Package Notes: 1. 2. 3. 4. All dimensions are in millimeters. Dimensions are inclusive of plating. Dimensions are exclusive of mold flash and metal burr. All specifications comply with JEITA SC88 and JEDEC MO203. www.austriamicrosystems.com Revision 1.04 Symbol e D b E HE Q1 A2 A1 A c L Lj Min Max 0.65BSC 1.80 2.20 0.15 0.30 1.15 1.35 1.80 2.40 0.10 0.40 0.80 1.00 0.00 0.10 0.80 1.10 0.10 0.18 0.10 0.30 0.26 0.46 14 - 17 AS1710/AS1712 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s -A- Figure 29. TQFN-16 3x3mm Package D INDEX AREA (D/2 xE/2) D2 D2/2 D/2 -B- aaa C 2x -BSEE DETAIL B 2 1 N N-1 INDEX AREA (D/2 xE/2) TOP VIEW Datum A or B 5 bbb ddd C A B C BTM VIEW 0.08 C A L1 ccc C NX 0.18 0.70 0.00 Typ 0.15 0.10 0.10 0.05 0.25 0.75 0.02 0.20REF A3 A1 Terminal Tip ODD TERMINAL SIDE Min SEATING PLANE -C- SIDE VIEW e Symbol aaa bbb ccc ddd b A A1 A3 e 6 SEE DETAIL B 4 NXb -A- aaa C 2x E2 E e E2/2 NXL E/2 4 5 Max 0.30 0.80 0.05 0.50 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 Symbol L1 D BSC E BSC D2 E2 L N ND NE Min 0.03 1.30 1.30 0.30 Typ 3.00 3.00 1.45 1.45 0.40 16 4 4 Max 0.15 1.55 1.55 0.50 Notes 1, 2 1, 2, 8 1, 2, 8 1, 2, 8 1, 2, 8 1, 2, 8 1, 2, 8 1, 2, 8 Notes: 1. 2. 3. 4. 5. 6. 7. 8. Dimensioning and tolerancing conform to ASME Y14.5m-1994. All dimensions are in millimeters while angle is in degrees (°). N is the total number of terminals. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC 95, SPP-002. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either a mold or marked feature. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. Depopulation is possible in a symmetrical fashion. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. ND and NE refer to the number of terminals on sides D and E respectively. www.austriamicrosystems.com Revision 1.04 15 - 17 AS1710/AS1712 Data Sheet 10 Ordering Information The device is available as the standard products shown in Table 6. Table 6. Ordering Information Model Description Delivery Form Package AS1710A-ASCT Single Op Amp with Shutdown Tape and Reel SC70-6 AS1710B-ASCT Single Op Amp Tape and Reel SC70-5 AS1712A-AQFT Quad Op Amp with Shutdown Tape and Reel TQFN-16 3x3mm www.austriamicrosystems.com Revision 1.04 16 - 17 AS1710/AS1712 Data Sheet - O r d e r i n g I n f o r m a t i o n Copyrights Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. 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Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.04 17 - 17