CA3306, CA3306A, CA3306C 6-Bit, 15 MSPS, Flash A/D Converters August 1997 Features Description • • • • • • The CA3306 family are CMOS parallel (FLASH) analog-to-digital converters designed for applications demanding both low power consumption and high speed digitization. Digitizing at 15MHz, for example, requires only about 50mW. CMOS Low Power with Video Speed (Typ) . . . . .70mW Parallel Conversion Technique Signal Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V 15MHz Sampling Rate with Single 5V Supply 6-Bit Latched Three-State Output with Overflow Bit Pin-for-Pin Retrofit for the CA3300 Applications • • • • • • • • • • TV Video Digitizing Ultrasound Signature Analysis Transient Signal Analysis High Energy Physics Research High Speed Oscilloscope Storage/Display General Purpose Hybrid ADCs Optical Character Recognition Radar Pulse Analysis Motion Signature Analysis Robot Vision The CA3306 family operates over a wide, full scale signal input voltage range of 1V up to the supply voltage. Power consumption is as low as 15mW, depending upon the clock frequency selected. The CA3306 types may be directly retrofitted into CA3300 sockets, offering improved linearity at a lower reference voltage and high operating speed with a 5V supply. The intrinsic high conversion rate makes the CA3306 types ideally suited for digitizing high speed signals. The overflow bit makes possible the connection of two or more CA3306s in series to increase the resolution of the conversion system. A series connection of two CA3306s may be used to produce a 7-bit high speed converter. Operation of two CA3306s in parallel doubles the conversion speed (i.e., increases the sampling rate from 15MHz to 30MHz). Sixty-four paralleled auto balanced comparators measure the input voltage with respect to a known reference to produce the parallel bit outputs in the CA3306. Sixty-three comparators are required to quantize all input voltage levels in this 6-bit converter, and the additional comparator is required for the overflow bit. Ordering Information PART NUMBER LINEARITY (INL, DNL) SAMPLING RATE TEMP. RANGE (oC) PACKAGE PKG. NO. CA3306E ±0.5 LSB 15MHz (67ns) -40 to 85 18 Ld PDIP E18.3 CA3306CE ±0.5 LSB 10MHz (100ns) -40 to 85 18 Ld PDIP E18.3 CA3306M ±0.5 LSB 15MHz (67ns) -40 to 85 20 Ld SOIC M20.3 CA3306CM ±0.5 LSB 10MHz (100ns) -40 to 85 20 Ld SOIC M20.3 CA3306D ±0.5 LSB 15MHz (67ns) -55 to 125 18 Ld SBDIP D18.3 CA3306CD ±0.5 LSB 10MHz (100ns) -55 to 125 18 Ld SBDIP D18.3 CA3306J3 ±0.5 LSB 15MHz (67ns) -55 to 125 20 Ld CLCC J20.B CA3306J3 ±0.5 LSB 10MHz (100ns) -55 to 125 20 Ld CLCC J20.B Pinouts CE2 6 CLK 7 PHASE 8 VREF + 9 14 B2 13 B1 (LSB) 12 VDD 11 VIN 10 VREF - B4 16 B2 2 B5 VZ 5 3 1 20 19 VZ 5 18 REF CENTER 17 B3 NC 6 16 B2 VSS 4 CE2 6 15 B1 (LSB) CE1 7 14 VDD CLK 8 13 NC 9 10 11 12 13 PHASE 9 12 VIN VREF + 10 11 VREF - CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 4-8 15 B1 (LSB) CE2 7 14 VDD CE1 8 VIN CE2 5 NC 4 19 B4 18 REF CENTER 17 B3 VSS 3 VREF - VZ 4 20 B5 VREF+ VSS 3 17 B4 REF 16 CENTER 15 B3 (MSB) B6 1 OVERFLOW 2 PHASE OVERFLOW 2 18 B5 CA3306 (CLCC) TOP VIEW OVERFLOW B6 (MSB) NC (MSB) B6 1 CA3306 (SOIC) TOP VIEW CLK CA3306 (PDIP, SBDIP) TOP VIEW File Number 3102.1 CA3306, CA3306A, CA3306C Functional Block Diagram VIN φ1 φ1 φ1 φ2 R/2 COMP 64 φ2 VREF+ THREE-STATE R COMP 63 R R ≅ 120Ω REF CENTER COMP 32 R COMPARATOR LATCHES AND ENCODER LOGIC R COMP 2 R D Q CL OVERFLOW D Q CL B6 (MSB) D Q CL B5 D Q CL B4 D Q CL B3 D Q CL B2 D Q CL B1 (LSB) VREFCOMP 1 R/2 ≅ 50kΩ CLOCK CE1 φ2 (SAMPLE UNKNOWN) PHASE φ1 (AUTO BALANCE) CE2 ZENER 6.2V NOMINAL DIODE VDD VSS VSS Typical Application Circuit OF B6 1 B6 2 OF B4 17 3 VSS RC 16 B2 4 VZ B3 15 B1 (LSB) 5 CE2 B2 14 6 CE1 B1 13 7 CLK VDD 12 8 PH 9 VREF+ CA3306 B5 18 B5 0.1µF 6.2V 560Ω +12V B4 B3 DATA OUTPUT +5V +5V CLOCK +12V 0.2µF 5kΩ + CA741CE VIN 11 0.1µF 4-9 VREF- 10 SIGNAL INPUT 10µF CA3306, CA3306A, CA3306C Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, VDD Voltage Referenced to VSS Terminal . . . . . . . . . . . -0.5V to +8.5V Input Voltage Range All Inputs Except Zener. . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V DC Input Current CLK, PH, CE1, CE2, VIN . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . . . 75 24 PDIP Package . . . . . . . . . . . . . . . . . . . . . 95 N/A SOIC Package . . . . . . . . . . . . . . . . . . . . . 115 N/A CLCC Package . . . . . . . . . . . . . . . . . . . . 80 28 Maximum Junction Temperature Hermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 8V Temperature Range (TA) Ceramic Package (D Suffix) . . . . . . . . . . . . . . . . . -55oC to 125oC Plastic Package (E or M Suffix). . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, VDD = 5V, VREF + = 4.8V, VSS = VREF - = GND, Clock = 15MHz Square Wave for CA3306 or CA3306A, 10MHz for CA3306C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 6 - - Bits ±0.25 ±0.5 LSB SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL CA3306, CA3306C - CA3306A - ±0.2 ±0.25 LSB Differential Linearity Error, DNL CA3306, CA3306C - ±0.25 ±0.5 LSB CA3306A - ±0.2 ±0.25 LSB Offset Error (Unadjusted) CA3306, CA3306C (Note 1) - ±0.5 ±1 LSB CA3306A - ±0.25 ±0.5 LSB CA3306, CA3306C (Note 2) - ±0.5 ±1 LSB CA3306A - ±0.25 ±0.5 LSB Gain Temperature Coefficient - +0.1 - mV/oC Offset Temperature Coefficient - -0.1 - mV/oC 10 13 - MSPS Gain Error (Unadjusted) DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale) Maximum Conversion Speed CA3306C CA3306, CA3306A Maximum Conversion Speed CA3306C CA3306, CA3306A Allowable Input Bandwidth 15 20 - MSPS (Note 4) φ1, φ2 ≥ Minimum 12 - - MSPS 18 - - MSPS (Note 4) DC - fCLOCK/2 MHz - 30 - MHz -3dB Input Bandwidth Signal to Noise Ratio, SNR RMSSignal = -------------------------------RMSNoise Signal to Noise Ratio, SINAD RMSSignal = -----------------------------------------------------------RMSNoise+Distortion Total Harmonic Distortion, THD Effective Number of Bits, ENOB fS = 15MHz, fIN = 100kHz - 34.6 - dB fS = 15MHz, fIN = 5MHz - 33.4 - dB fS = 15MHz, fIN = 100kHz - 34.2 - dB fS = 15MHz, fIN = 5MHz - 29.0 - dB fS = 15MHz, fIN = 100kHz - -46.0 - dBc fS = 15MHz, fIN = 5MHz - -30.0 - dBc fS = 15MHz, fIN = 100kHz - 5.5 - Bits fS = 15MHz, fIN = 5MHz - 4.5 - Bits 4-10 CA3306, CA3306A, CA3306C Electrical Specifications TA = 25oC, VDD = 5V, VREF + = 4.8V, VSS = VREF - = GND, Clock = 15MHz Square Wave for CA3306 or CA3306A, 10MHz for CA3306C (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ANALOG INPUTS Positive Full Scale Input Range (Notes 3, 4) 1 4.8 VDD + 0.5 V Negative Full Scale Input Range (Notes 3, 4) -0.5 0 VDD - 1 V - 15 - pF - - ±500 µA 5.4 6.2 7.4 V - 12 25 Ω - -0.5 - mV/oC 650 1100 1550 Ω Input Capacitance Input Current VIN = 4.92V, VDD = 5V INTERNAL VOLTAGE REFERENCE Zener Voltage IZ = 10mA Zener Dynamic Impedance IZ = 10mA, 20mA Zener Temperature Coefficient REFERENCE INPUTS Resistor Ladder Impedance DIGITAL INPUTS Maximum VIN , Logic 0 All Digital Inputs (Note 4) - - 0.3 x VDD V Maximum VIN , Logic 1 All Digital Inputs (Note 4) 0.7 x VDD - - V Digital Input Current Except CLK, VIN = 0V, 5V - ±1 ±5 µA Digital Input Current CLK Only - ±100 ±200 µA DIGITAL OUTPUTS Digital Output Three-State Leakage VOUT = 0V, 5V - ±1 ±5 µA Digital Output Source Current VOUT = 4.6V -1.6 - - mA Digital Output Sink Current VOUT = 0.4V 3.2 - - mA CA3306C 50 - ∞ ns CA3306, CA3306A 33 - ∞ TIMING CHARACTERISTICS Auto Balance Time (φ1) Sample Time (φ2) CA3306C (Note 4) CA3306, CA3306A Aperture Delay Aperture Jitter Output Data Valid Delay, tD CA3306C CA3306, CA3306A 33 - 5000 ns 22 - 5000 ns - 8 - ns - 100 - psP-P - 35 50 ns - 30 40 ns 15 25 - ns Output Enable Time, tEN - 20 - ns Output Disable Time, tDIS - 15 - ns Continuous Conversion (Note 4) - 11 20 mA - 14 25 mA Continuous φ1 - 7.5 15 mA Output Data Hold Time, tH (Note 4) POWER SUPPLY CHARACTERISTICS IDD Current, Refer to Figure 4 CA3306C CA3306, CA3306A IDD Current NOTES: 1. OFFSET ERROR is the difference between the input voltage that causes the 00 to 01 output code transition and (VREF + - VREF -)/128. 2. GAIN ERROR is the difference the input voltage that causes the 3F16 to overflow output code transition and (VREF + - VREF -) x 127/128. 3. The total input voltage range, set by VREF + and VREF -, may be in the range of 1 to (VDD + 1) V. 4. Parameter not tested, but guaranteed by design or characterization. 4-11 CA3306, CA3306A, CA3306C Timing Waveforms COMPARATOR DATA IS LATCHED CLOCK IF PHASE IS HIGH DECODED DATA IS SHIFTED TO OUTPUT REGISTERS φ2 CLOCK IF PHASE IS LOW φ1 φ2 φ1 φ2 AUTO BALANCE SAMPLE N+1 AUTO BALANCE SAMPLE N+2 tD tH DATA N-2 DATA N-1 DATA N FIGURE 1. INPUT-TO-OUTPUT CE1 CE2 tDIS tEN tDIS tDIS HIGH IMPEDANCE HIGH IMPEDANCE DATA BITS 1-6 DATA DATA HIGH IMPEDANCE DATA DATA OF FIGURE 2. OUTPUT ENABLE SAMPLE ENDS CLOCK SAMPLE ENDS φ1 φ2 φ2 CLOCK φ1 φ2 φ1 tD OUTPUT OUTPUT OLD DATA OLD DATA +1 FIGURE 3B. FIGURE 3A. SAMPLE ENDS CLOCK φ2 φ1 φ2 φ1 φ2 tD OUTPUT φ1 tD NEW DATA OLD DATA φ2 INVALID DATA OLD DATA FIGURE 3C. FIGURE 3. PULSE MODE 4-12 NEW DATA NEW DATA CA3306, CA3306A, CA3306C Typical Performance Curves 125 50 AMBIENT TEMPERATURE (oC) TA = 25oC, VREF + = VDD VIN = 0 TO VREF + SINE WAVE AT fCLK/2 40 IDD (mA) DISSIPATION LIMITED 30 VDD = 8V VDD = 7V VDD = 6V VDD = 5V 20 10 fCLK = 1MHz fCLK = 3MHz fCLK = 10MHz fCLK = 15MHz fCLK = 20MHz 100 MAXIMUM AMBIENT TEMPERATURE - PLASTIC 75 50 VREF + = VDD VIN = 0 TO VREF + SINE WAVE AT fCLK/2 ZENER NOT CONNECTED VDD = 3V 25 1 CLOCK FREQUENCY (MHz) 0.1 3 10 4 5 6 7 8 VDD (V) FIGURE 4. TYPICAL IDD AS A FUNCTION OF VDD FIGURE 5. TYPICAL MAXIMUM AMBIENT TEMPERATURE AS A FUNCTION OF SUPPLY VOLTAGE 0.35 TA = 25oC, VDD = 5V fCLK = 15MHz 1.2 0.25 INTEGRAL NON-LINEARITY (LSB) NON-LINEARITY (LSB) TA = 25oC, VREF = 4.8V 0.30 VDD = 5V 0.20 0.15 DIFFERENTIAL 0.10 0.05 0 0.1 0.8 INTEGRAL 0.6 0.4 DIFFERENTIAL 0.2 0 1 CLOCK FREQUENCY (MHz) 10 0 FIGURE 6. TYPICAL NON-LINEARITY AS A FUNCTION OF CLOCK SPEED 2 3 REFERENCE VOLTAGE (V) 4 fCLK = 15MHz, VREF + = VDD VREF - = VSS INPUT CURRENT (µA) +10 1 FIGURE 7. TYPICAL NON-LINEARITY AS A FUNCTION OF REFERENCE VOLTAGE VREF + = VDD , VREF - = VSS +15 PEAK INPUT CURRENT (mA) 1.0 VDD = 8V +5 VDD = 5V 0 -5 -10 -15 +400 VDD = 8V +200 VDD = 5V +0 -200 -400 -600 -800 0 1 2 3 4 5 6 7 INPUT VOLTAGE (V) 8 0 FIGURE 8. TYPICAL PEAK INPUT CURRENT AS A FUNCTION OF INPUT VOLTAGE 4-13 1 2 3 4 5 6 7 INPUT VOLTAGE (V) 8 FIGURE 9. TYPICAL AVERAGE INPUT CURRENT AS A FUNCTION OF INPUT VOLTAGE 5 CA3306, CA3306A, CA3306C Typical Performance Curves (Continued) 11 TA = 25oC, VREF+ = VDD VIN = 0 TO VREF + SINE WAVE AT fCLK/2 10 30 9 20 IDD (mA) DECODER LIMITED 25 DISSIPATION LIMITED 8 7 15 6 10 5 5 0 3 4 5 6 7 4 8 0 5 10 fS (MHz) SUPPLY VOLTAGE (V) FIGURE 10. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE 15 20 FIGURE 11. DEVICE CURRENT vs SAMPLE FREQUENCY 32.5 6.0 5.7 fS = 15MHz, fI = 1MHz 30.0 5.4 5.1 ENOB (LSB) tD (ns) 27.5 25.0 22.5 4.8 4.5 4.2 3.9 20.0 3.6 17.5 3.3 15.0 -50 -25 0 25 50 75 3.0 -40 -30 -20 -10 100 TEMPERATURE (oC) 12.6 0.90 11.2 0.80 NON-LINEARITY (LSB) 1.00 9.8 IDD (mA) 8.4 7.0 5.6 4.2 30 40 50 60 70 80 90 0.60 70 80 90 0.40 0.30 1.4 0.10 70 80 0.0 -40 -30 -20 -10 90 INL 0.50 0.20 60 fS = 15MHz 0.70 2.8 10 20 30 40 50 TEMPERATURE (oC) 20 FIGURE 13. ENOB vs TEMPERATURE 14.0 0 10 TEMPERATURE (oC) FIGURE 12. DATA DELAY vs TEMPERATURE 0.0 -40 -30 -20 -10 0 DNL 0 10 20 30 40 50 60 TEMPERATURE (oC) FIGURE 14. IDD vs TEMPERATURE FIGURE 15. NON-LINEARITY vs TEMPERATURE 4-14 CA3306, CA3306A, CA3306C Typical Performance Curves (Continued) 6.00 5.70 fS = 15MHz 5.40 ENOB (LSB) 5.10 4.80 4.50 4.20 3.90 3.60 3.30 3.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 fI (MHz) FIGURE 16. ENOB vs INPUT FREQUENCY Pin Descriptions PIN NUMBER DIP SOIC NAME DESCRIPTION 1 1 B6 Bit 6, Output (MSB). 2 2 OF Overflow, Output. 3 3, 4 VSS Digital Ground. 4 5 VZ Zener Reference Output. 5 6 CE2 Three-State Output Enable Input, Active Low. See Table 1. 6 7 CE1 Three-State Output Enable Input, Active High. See Table 1. 7 8 CLK Clock Input. 8 9 Phase Sample clock phase control input. When PHASE is low, “Sample Unknown” occurs when the clock is low and “Auto Balance” occurs when the clock is high (see text). 9 10 VREF + Reference Voltage Positive Input. 10 11 VREF - Reference Voltage Negative Input. 11 12 VIN Analog Signal Input. 12 13, 14 VDD Power Supply, +5V. 13 15 B1 Bit 1, Output (LSB). 14 16 B2 Bit 2, Output. 15 17 B3 Bit 3, Output. 16 18 REF(CTR) 17 19 B4 Bit 4, Output. 18 20 B5 Bit 5, Output. Reference Ladder Midpoint. 4-15 CA3306, CA3306A, CA3306C TABLE 1. CHIP ENABLE TRUTH TABLE CE1 CE2 B1 - B6 OF 0 1 Valid Valid 1 1 Three-State Valid X 0 Three-State Three-State X = Don’t care TABLE 2. OUTPUT CODE TABLE (NOTE 1) INPUT VOLTAGE BINARY OUTPUT CODE (LSB) CODE DESCRIPTION VREF 6.40 (V) VREF 5.12 (V) VREF 4.80 (V) VREF 3.20 (V) OF B6 B5 B4 B3 B2 B1 DECIMAL COUNT Zero 1 LSB 2 LSB 0.00 0.10 0.20 0.00 0.08 0.16 0.00 0.075 0.15 0.00 0.05 0.10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 2 • • • • 1/ Full Scale - 1 LSB 2 1/ Full Scale 2 1/ Full Scale + 1 LSB 2 • • • • 3.10 3.20 3.30 2.48 2.56 2.64 • • • • Full Scale - 1 LSB Full Scale Overflow • • • • 2.325 2.40 2.475 1.55 1.60 1.65 0 0 0 0 1 1 1 0 0 • • • • 6.20 6.30 6.40 4.96 5.04 5.12 1 0 0 • • • • 1 0 0 1 0 0 1 0 1 • • • • 4.65 4.725 4.80 3.10 3.15 3.20 0 0 1 1 1 1 1 1 1 1 1 1 • • • • 1 1 1 1 1 1 0 1 1 NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. 4-16 31 32 33 62 63 127 CA3306, CA3306A, CA3306C Device Operation Continuous Clock Operation A sequential parallel technique is used by the CA3306 converter to obtain its high speed operation. The sequence consists of the “Auto Balance” phase φ1 and the “Sample Unknown” phase φ2. (Refer to the circuit diagram.) Each conversion takes one clock cycle (see Note). With the phase control low, the “Auto Balance” (φ1) occurs during the High period of the clock cycle, and the “Sample Unknown” (φ2) occurs during the low period of the clock cycle. One complete conversion cycle can be traced through the CA3306 via the following steps. (Refer to timing diagram, Figure 1.) With the phase control in a “High” state, the rising edge of the clock input will start a “sample” phase. During this entire “High” state of the clock, the 64 comparators will track the input voltage and the 64 latches will track the comparator outputs. At the falling edge of the clock, after the specified aperture delay, all 64 comparator outputs are captured by the 64 latches. This ends the “sample” phase and starts the “auto balance” phase for the comparators. During this “Low” state of the clock the output of the latches propagates through the decode array and a 7-bit code appears at the D inputs of the output registers. On the next rising edge of the clock, this 7bit code is shifted into the output registers and appears with time delay to as valid data at the output of the three-state drivers. This also marks the start of a new “sample” phase, thereby repeating the conversion process for this next cycle. During the “Auto Balance” phase, a transmission-gate switch is used to connect each of 64 commutating capacitors to their associated ladder reference tap. Those tap voltages will be as follows: VTAP (N) = [(VREF/64) x N] - [VREF/(2 x 64)] = VREF[(2N - 1)/126], Where: VTAP (N) = reference ladder tap voltage at point N, VREF = voltage across VREF - to VREF +, N = tap number (I through 64). Pulse Mode Operation NOTE: This device requires only a single-phase clock The terminology of φ1 and φ2 refers to the High and Low periods of the same clock. The other side of the capacitor is connected to a singlestage inverting amplifier whose output is shorted to its input by a switch. This biases the amplifier at its intrinsic trip point, which is approximately, (VDD - VSS)/2. The capacitors now charge to their associated tap voltages, priming the circuit for the next phase. In the “Sample Unknown” phase, all ladder tap switches are opened, the comparator amplifiers are no longer shorted, and VlN is switched to all 64 capacitors. Since the other end of the capacitor is now looking into an effectively open circuit, any voltage that differs from the previous tap voltage will appear as a voltage shift at the comparator amplifiers. All comparators whose tap voltages were lower than VlN will drive the comparator outputs to a “low” state. All comparators whose tap voltages were higher than VlN will drive the comparator outputs to a “high” state. A second, capacitorcoupled, auto-zeroed amplifier further amplifies the outputs. The status of all these comparator amplifiers are stored at the end of this phase (φ2), by a secondary latching amplifier stage. Once latched, the status of the 64 comparators is decoded by a 64-bit 7-bit decode array and the results are clocked into a storage register at the rising edge of the next φ2. A three-state buffer is used at the output of the 7 storage registers which are controlled by two chip-enable signals. CE1 will independently disable 81 through 86 when it is in a high state. CE2 will independently disable B1 through B6 and the OF buffers when it is in the low state (Table 1). To facilitate usage of this device a phase-control input is provided which can effectively complement the clock as it enters the chip. Also, an on-board zener is provided for use as a reference voltage. For sampling high speed nonrecurrent or transient data, the converter may be operated in a pulse mode in one of three ways. The fastest method is to keep the converter in the Sample Unknown phase, φ2, during the standby state. The device can now be pulsed through the Auto Balance phase with a single pulse. The analog value is captured on the leading edge of φ1 and is transferred into the output registers on the trailing edge of φ1. We are now back in the standby state, φ2, and another conversion can be started, but not later than 5µs due to the eventual droop of the commutating capacitors. Another advantage of this method is that it has the potential of having the lowest power drain. The larger the time ratio between φ2 and φ1, the lower the power consumption. (See Timing Waveform, Figure 3.) The second method uses the Auto Balance phase, φ1, as the standby state. In this state the converter can stay indefinitely waiting to start a conversion. A conversion is performed by strobing the clock input with two φ2 pulses. The first pulse starts a Sample Unknown phase and captures the analog value in the comparator latches on the trailing edge. A second φ2 pulse is needed to transfer the data into the output registers. This occurs on the leading edge of the second pulse. The conversion now takes slightly longer, but the repetition rate may be as slow as desired. The disadvantage to this method is the higher device dissipation due to the low ratio of φ2 to φ1. (See Timing Waveform, Figure 3B.) For applications requiring both indefinite standby and lowest power, standby can be in the φ2 (Sample Unknown) state with two φ1 pulses to generate valid data (see Figure 3C). Valid data now appears two full clock cycles after starting the conversion process. Analog Input Considerations The CA3306 input terminal is characterized by a small capacitance (see Specifications) and a small voltagedependent current (See Typical Performance Curves). The signal-source impedance should be kept low, however, when operating the CA3306 at high clock rates. 4-17 CA3306, CA3306A, CA3306C The CA3306 outputs a short (less than 10ns) current spike of up to several mA amplitude (See Typical Performance Curves) at the beginning of the sample phase. (To a lesser extent, a spike also appears at the beginning of auto balance.) The driving source must recover from the spike by the end of the same phase, or a loss of accuracy will result. A locally terminated 50Ω or 75Ω source is generally sufficient to drive the CA3306. If gain is required, a high speed, fast settling operational amplifier, such as the HA-5033, HA-2542, or HA5020 is recommended. Digital Input And Output Interfacing The two chip-enable and the phase-control inputs are standard CMOS units. They should be driven from less than 0.3 x VDD to at least 0.7 x VDD . This can be done from 74HC series CMOS (QMOS), TTL with pull-up resistors, or, if VDD is greater than the logic supply, open collector or open drain drivers plus pull-ups. (See Figure 20.) The clock input is more critical to timing variations, such as φ1 becoming too short, for instance. Pull-up resistors should generally be avoided in favor of active drivers. The clock input may be capacitively coupled, as it has an internal 50kΩ feedback resistor on the first buffer stage, and will seek its own trip point. A clock source of at least 1VP-P is adequate, but extremely non-symmetrical waveforms should be avoided. The output drivers have full rail-to-rail capability. If driving CMOS systems with VDD below the VDD of the CA3306, a CD74HC4050 or CD74HC4049 should be used to step down the voltage. If driving LSTTL systems, no step-down should be necessary, as most LSTTLs will take input swings up to 10V to 15V. If VIN for the first transition is greater than the theoretical, then the 50Ω pot should be connected between VREF and a negative voltage of about 2 LSBs. The trim procedure is as stated previously. Gain Trim In general the gain trim can also be done in the preamp circuitry by introducing a gain adjustment for the operational amplifier. When this is not possible, then a gain adjustment circuit should be made to adjust the reference voltage. To perform this trim, VlN should be set to the 63 to overflow transition. That voltage is 1/2 LSB less than VREF+ and is calculated as follows: VlN (63 to 64 transition) = VREF - VREF/128 = VREF(127/128). To perform the gain trim, first do the offset trim and then apply the required VlN for the 63 to overtlow transition. Now adjust VREF+ until that transition occurs on the outputs. Midpoint Trim The reference center (RC) is available to the user as the midpoint of the resistor ladder. To trim the midpoint, the offset and gain trims should be done first. The theoretical transition from count 31 to 32 occurs at 311/2 LSBs. That voltage is as follows: VlN (31 to 32 transition) = 31.5 (VREF/64) = VREF(63/128). An adjustable voltage follower can be connected to the RC pin or a 2K pot can be connected between VREF+ and VREF- with the wiper connected to RC. Set VlN to the 31 to 32 transition voltage, then adjust the voltage follower or the pot until the transition occurs on the output bits. Although the output drivers are capable of handling typical data bus loading, the capacitor charging currents will produce local ground disturbances. For this reason, an external bus driver is recommended. The Reference Center point can also be used to create unique transfer functions. The user must remember, however, that there is approximately 120Ω in series with the RC pin. Increased Accuracy Applications In most cases the accuracy of the CA3306 should be sufficient without any adjustments. In applications where accuracy is of utmost importance, three adjustments can be made to obtain better accuracy; i.e., offset trim, gain trim, and midpoint trim. Offset Trim In general offset correction can be done in the preamp circuitry by introducing a DC shift to VlN or by the offset trim of the operational amplifier. When this is not possible the VREF- input can be adjusted to produce an offset trim. The theoretical input voltage to produce the first transition is 1/2 LSB. The equation is as follows: VIN (0 to 1 transition) = 1/2 LSB = 1/2(VREF/64) = VREF/128. If VlN for the first transition is less than the theoretical, then a single-turn 50Ω pot connected between VREF- and ground will accomplish the adjustment. Set VlN to 1/2 LSB and trim the pot until the 0 to 1 transition occurs. 7-Bit Resolution To obtain 7-bit resolution, two CA3306s can be wired together. Necessary ingredients include an open-ended ladder network, an overtlow indicator, three-state outputs, and chip-enabler controls - all of which are available on the CA3306. The first step for connecting a 7-bit circuit is to totem-pole the ladder networks, as illustrated in Figure 17. Since the absolute resistance value of each ladder may vary, external trim of the mid-reference voltage may be required. The overflow output of the lower device now becomes the seventh bit. When it goes high, all counts must come from the upper device. When it goes low, all counts must come from the lower device. This is done simply by connecting the lower overflow signal to the CE1 control of the lower A/D converter and the CE2 control of the upper A/D converter. The three-state outputs of the two devices (bits 1 through 6) are now connected in parallel to complete the circuitry. 4-18 CA3306, CA3306A, CA3306C Doubled Sampling Speed Signal-to-Noise (SNR) The phase control and both positive and negative true chip enables allow the parallel connection of two CA3306s to double the sampling speed. Figure 18 shows this configuration. One converter samples on the positive phase of the clock, and the second on the negative. The outputs are also alternately enabled. Care should be taken to provide a near square-wave clock it operating at close to the maximum clock speed for the devices. SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. 8-Bit to 12-Bit Conversion Techniques Effective Number of Bits (ENOB) To obtain 8-bit to 12-bit resolution and accuracy, use a feedforward conversion technique. Two A/D converters will be needed to convert up to 11 bits; three A/D converters to convert 12 bits. The high speed of the CA3306 allows 12-bit conversions in the 500ns to 900ns range. The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: The circuit diagram of a high-speed 12-bit A/D converter is shown in Figure 19. In the feed-forward conversion method two sequential conversions are made. Converter A first does a coarse conversion to 6 bits. The output is applied to a 6-bit D/A converter whose accuracy level is good to 12 bits. The D/A converter output is then subtracted from the input voltage, multiplied by 32, and then converted by a second flash A/D converter, which is connected in a 7-bit configuration. The answers from the first and second conversions are added together with bit 1 of the first conversion overlapping bit 7 of the second conversion. Total Harmonic Distortion (THD) When using this method, take care that: • The linearity of the first converter is better than 1/2 LSB. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. ENOB = (SINAD - 1.76 + VCORR)/6.02, where: VCORR = 0.5dB. THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal. Operating and Handling Considerations HANDLING All inputs and outputs of Intersil CMOS devices have a network for electrostatic protection during handling. Recommended handling practices for CMOS devices are described in AN6525. “Guide to Better Handling and Operation of CMOS Integrated Circuits.” • An offset bias of 1 LSB (1/64) Is subtracted from the first conversion since the second converter is unipolar. OPERATING • The D/A converter and its reference are accurate to the total number of bits desired for the final conversion (the A/D converter need only be accurate to 6 bits). During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause VDD - VSS to exceed the absolute maximum rating. The first converter can be offset-biased by adding a 20Ω resistor at the bottom of the ladder and increasing the reference voltage by 1 LSB. If a 6.4V reference is used in the system, for example, then the first CA3306 will require a 6.5V reference. Definitions Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the converter. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. Operating Voltage Input Signals To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS . Input currents must not exceed 20mA even when the power supply is off. The zener (pin 4) is the only terminal allowed to exceed VDD . Unused Inputs A connection must be provided at every input terminal. All unused input terminals must be connected to either VDD or VSS , whichever is appropriate. Output Short Circuits Shorting of outputs to VDD or VSS may damage CMOS devices by exceeding the maximum device dissipation. 4-19 CA3306, CA3306A, CA3306C Application Circuits OF B7 (MSB) B6 V+ B6 B5 B5 OF B4 B4 1K RC VSS DATA OUTPUT 0.1µF CA3306 CLOCK INPUT VZ B3 CE2 B2 B3 B2 (LSB) CE1 B1 B1 V+ CLK VSS VDD 0.2µF 10µF PH VIN VREF + VREF 0.1µF ADJUST POT TO 1/2 VZ B6 B5 OF B4 CA3306 RC VSS 0.1µF V+ VZ CE2 B3 CE1 B2 CLK B1 VDD 0.2µF PH 10µF NOTE: VDD MUST BE ≥ VZ FOR CIRCUIT TO WORK WITH VZ CONNECTED TO VREF+ VIN VREF - SIGNAL INPUT VREF + 0.1µF FIGURE 17. TYPICAL CA3306 7-BIT RESOLUTION CONFIGURATION 4-20 CA3306, CA3306A, CA3306C Application Circuits (Continued) (MSB) B6 V+ B6 B5 B5 OF B4 B4 DATA OUTPUT RC VSS 0.1µF CA3306 CLOCK INPUT VZ B3 CE2 B2 B3 B2 (LSB) CE1 B1 B1 V+ CLK VSS VDD 0.2µF 10µF PH VIN VREF + VREF 0.1µF ADJUST POT TO 1/2 VZ B6 B5 OF B4 CA3306 VSS RC 0.1µF V+ VZ B3 CE2 B2 CE1 CLK B1 VDD 0.2µF V+ PH 10µF NOTE: VDD MUST BE ≥ VZ FOR CIRCUIT TO WORK WITH VZ CONNECTED TO VREF+ VIN VREF - SIGNAL INPUT VREF + 0.1µF FIGURE 18. TYPICAL CA3306 6-BIT RESOLUTION CONFIGURATION WITH DOUBLE SAMPLING RATE CAPABILITY 4-21 CA3306, CA3306A, CA3306C Application Circuits (Continued) BINARY ADDER B12 B6’ NO. 1 6-BIT FLASH ADC S/H, VIN B6 + 0 B5 + 0 B4 + 0 B3 + 0 B2 + 0 B1 + B7 B1’ B6 + ∑ - 6-BIT DAC (12 BIT ACCURACY) X32 B6 NO. 2 6-BIT FLASH ADC B1 B1 B7 NO. 3 6-BIT FLASH ADC B6 B1 CONTROL LOGIC FIGURE 19. TYPICAL CA3306, 800ns, 12-BIT ADC SYSTEM 5V CA3306 VDD VDD CA3306 INPUT TYPICAL FOR: 1K CA3306 CLK 50kΩ 5V CA3306 INPUTS TYPICAL FOR: 0.01µF PHASE CE1 CE2 74LS04 7406 OPEN COLLECTOR DRIVER CA3306 OUTPUTS TYPICAL FOR: CA3306 VDD 5V B1 B2 B3 B4 B5 B6 OF CD74HC 4049 (INV.), OR CD74HC4050 (NON-INV.), OR ANY LOW POWER SCHOTTKY TTL WITH HIGH INPUT VOLTAGE RATING (MANY LS DEVICES ARE RATED TO ACCEPT VOLTAGES UP TO 15V). FIGURE 20. 5V LOGIC INTERFACE CIRCUIT FOR VDD > 5.5V 4-22 CA3306, CA3306A, CA3306C All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 4-23 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029