ams CMV300 Vga resolution cmos image sensor Datasheet

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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
VGA resolution CMOS image sensor
Datasheet
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CMV300 Datasheet
Change record
Issue
1
1.1
1.2
1.3
1.4
Date
13/04/2011
5/8/2011
20/10/2011
25/4/2012
22/08/2012
1.5
28/09/2012
1.6
19/12/2012
1.7
2.0
8/1/2012
05/06/2013
V2.1
03/07/2013
V2.2
08/07/2013
V2.3
20/08/2013
Modification
Origination
Update after tape out
Update after samples test and debug
Updated maximum output rate from 600Mbps to 300 Mbps
Updated recommended register values
Added Spectral Response and QE graphs
Updated recommended register values
Updated supply settings
Removed Draft status
Updated Part Numbers
Updated VDD18 range
Updated:
- maximum output rate from 300Mbps to 480Mbps
- Full Well Charge: 20ke- Conversion factor: 0.2LSB/e- Dynamic range: 60dB
- Dark current: 125e-/s
- Total power: 700mW
- VDDPIX: 3.3V
- VDD18 renamed to VDD20
- Supply settings
- FOT calculation and value
- Piecewise Linear Response details
- PLR external mode pulse requirements
- Bit mode details
- Recommended registers
Added:
- Temperature sensor formulas and graphs
- Output skew
- Control channel test pin (Test3) programming
- Disable PLL
- Actual exposure calculations
- ADC vs actual gain
- Detailed frame cycle timing
Updated:
- Detailed frame cycle timing
- Exposure calculation
Added:
- Color and mono QE
Updated:
- VDDPIX to 3.0V
- Recommended value for reg 106 = 90
Updated:
- Exposure time calculation
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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
Issue
V2.4
Date
05/03/2014
V2.5
28/10/2014
V2.6
19/06/2015
V2.7
09/09/2015
V2.8
12/10/2015
V2.9
23/10/2015
V2.10
29/02/2016
Modification
Updated:
- Assembly thickness dimensions (details PCN-01)
- Added ‘0’-bits in 8/10bit are LSB
- Ch5.7: reg69 to 9 for parallel output mode
- Piecewise Linear response Figure 32
- PLL settings ch. 5.10
- Disable PLL settings ch. 5.11
- LVDS output skew
- Part Number
Added:
- Location of pixel(0,0) in assembly drawing
- Limitations when using or disabling the PLL (ch. 5.10
& ch.5.11)
Updated:
- FOT description (ch 3.6)
- Exposure timing (ch 5.1)
- SPI_OUT is low when SPI_EN is low
- No TP between FOT and FVAL (ch 4.1.5)
- Supply settings
- Rename VDD18 to VDD20 in pin list
- Reflow soldering details (ch 12.1.1)
Added:
- MSL-5 (ch 12.1)
Removed:
- Wave soldering
Updated:
- Baking condition 24h-48h  12h
- SPI I/O’s are pulled low when not enabled
- Frame rate calculation ch 3.6
- Fig. Figure 30: Frame cycle timing
- Assembly drawing
Added:
- Figure 27: Detailed timing diagram
- Excessive light precaution
Updated:
- Removed ES label from part numbers
- Temperature sensor typical values
- ADC vs. clock speed
Added:
- Test image
Updated:
- Reflow profile
Updated:
- MSL and solder profile following J-STD-020
- Replaced “1.8V” notations with VDD20
Added:
- ESD level
Updated:
- Recommended PLL reg83 187  155 (for 40MHz)
Added:
- Exposure delay
- Pin list connection to internal blocks
Disclaimer
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
This is a preliminary datasheet. CMOSIS reserves the right to change the product, specification and other information
contained in this document without notice. Although CMOSIS does its best efforts to provide correct information, this
is not warranted.
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
Table of Contents
1 Introduction ...........................................................................................................................................................8
1.1 Overview ........................................................................................................................................................ 8
1.2 Features ......................................................................................................................................................... 8
1.3 Specifications.................................................................................................................................................. 8
1.4 Connection diagram........................................................................................................................................ 9
2 Sensor architecture .............................................................................................................................................. 10
2.1 Pixel array..................................................................................................................................................... 10
2.2 Analog front end ........................................................................................................................................... 11
2.3 LVDS block .................................................................................................................................................... 11
2.4 Parallel CMOS output block .......................................................................................................................... 11
2.5 Sequencer .................................................................................................................................................... 11
2.6 SPI interface ................................................................................................................................................. 11
2.7 Temperature sensor ..................................................................................................................................... 12
3 Driving the CMV300 ............................................................................................................................................. 13
3.1 Supply settings ............................................................................................................................................. 13
3.2 Biasing .......................................................................................................................................................... 13
3.3 Digital input pins........................................................................................................................................... 13
3.4 electrical IO specifications............................................................................................................................. 14
3.4.1
Digital IO CMOS/TTL DC specifications ................................................................................................................ 14
3.4.2
Parallel CMOS output DC specifications .............................................................................................................. 14
3.4.3
LVDS receiver specifications ............................................................................................................................... 14
3.4.4
LVDS driver specifications .................................................................................................................................. 14
3.5 Input clock .................................................................................................................................................... 15
3.6 Frame rate calculation .................................................................................................................................. 15
3.7 Start-up sequence......................................................................................................................................... 16
3.8 Reset sequence ............................................................................................................................................ 17
3.9 SPI programming .......................................................................................................................................... 17
3.9.1
SPI write ............................................................................................................................................................ 17
3.9.2
SPI read ............................................................................................................................................................. 18
3.10 Requesting a frame ....................................................................................................................................... 18
3.10.1 Internal exposure control ................................................................................................................................... 18
3.10.2 External exposure control .................................................................................................................................. 19
3.10.3 Exposure delay .................................................................................................................................................. 19
4 Reading out the sensor ........................................................................................................................................ 21
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CMV300 Datasheet
4.1 LVDS data outputs ........................................................................................................................................ 21
4.1.1
LVDS low-level pixel timing ................................................................................................................................ 21
4.1.2
LVDS readout timing .......................................................................................................................................... 22
4.1.3
4.1.4
4.1.2.1
4 output channels ............................................................................................................................... 22
4.1.2.2
2 output channels ............................................................................................................................... 22
4.1.2.3
1 output channel................................................................................................................................. 22
Pixel remapping ................................................................................................................................................. 22
4.1.3.1
4 outputs ............................................................................................................................................ 23
4.1.3.2
2 outputs ............................................................................................................................................ 23
4.1.3.3
1 output ............................................................................................................................................. 23
Control channel ................................................................................................................................................. 23
4.1.4.1
4.1.5
DVAL, LVAL, FVAL ................................................................................................................................ 24
Training data ..................................................................................................................................................... 24
4.2 Parallel CMOS output.................................................................................................................................... 26
4.2.1
Parallel output timing ........................................................................................................................................ 26
5 Image sensor programming.................................................................................................................................. 27
5.1 Exposure modes ........................................................................................................................................... 27
5.2 High dynamic range modes ........................................................................................................................... 28
5.2.1
Interleaved read-out .......................................................................................................................................... 28
5.2.2
Piecewise linear response .................................................................................................................................. 29
5.2.2.1
Piecewise linear response with internal exposure mode ...................................................................... 30
5.2.2.2
piecewise linear response with external exposure mode ...................................................................... 30
5.3 Windowing ................................................................................................................................................... 31
5.3.1
Single window ................................................................................................................................................... 31
5.3.2
Multiple windows .............................................................................................................................................. 32
5.4 Image flipping ............................................................................................................................................... 33
5.5 Image subsampling ....................................................................................................................................... 34
5.5.1
Simple subsampling ........................................................................................................................................... 34
5.5.2
Advanced subsampling ...................................................................................................................................... 34
5.6 Number of frames ........................................................................................................................................ 35
5.7 Output mode ................................................................................................................................................ 35
5.8 Training pattern ............................................................................................................................................ 35
5.9 8-bit, 10-bit or 12-bit mode........................................................................................................................... 36
5.10 Data rate ...................................................................................................................................................... 36
5.11 Disabling the internal PLL .............................................................................................................................. 36
5.12 Power control ............................................................................................................................................... 37
5.13 Offset and gain ............................................................................................................................................. 37
5.13.1 Offset ................................................................................................................................................................ 37
5.13.2 Gain .................................................................................................................................................................. 38
5.14 Test Image .................................................................................................................................................... 39
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CMV300 Datasheet
6 Register overview ................................................................................................................................................ 41
7 Mechanical specifications .................................................................................................................................... 44
7.1 Package drawing ........................................................................................................................................... 44
7.2 Assembly drawing......................................................................................................................................... 44
7.3 Cover glass ................................................................................................................................................... 44
7.4 Color filters................................................................................................................................................... 45
8 Spectral response ................................................................................................................................................. 46
9 Pin list .................................................................................................................................................................. 47
9.1 LVDS output mode pin list ............................................................................................................................. 47
9.2 Parallel CMOS output mode pin list ............................................................................................................... 48
10 Specification overview ......................................................................................................................................... 50
11 Ordering info ........................................................................................................................................................ 52
12 Handling and soldering procedure ....................................................................................................................... 53
12.1 Soldering ...................................................................................................................................................... 53
12.1.1 Reflow soldering ................................................................................................................................................ 53
12.1.2 Soldering recommendations .............................................................................................................................. 53
12.2 Handling image sensors ................................................................................................................................ 53
12.2.1 ESD ................................................................................................................................................................... 53
12.2.2 Glass cleaning .................................................................................................................................................... 53
12.2.3 Image sensor storing.......................................................................................................................................... 54
12.2.4 Excessive light.................................................................................................................................................... 54
13 Additional information......................................................................................................................................... 55
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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
1 INTRODUCTION
1.1 OVERVIEW
The CMV300 is a high speed CMOS image sensor with 648 by 488 pixels (1/3 optical inch) developed for machine
vision applications. The image array consists of 7.4μm x 7.4μm pipelined global shutter pixels which allow exposure
during read out, while performing CDS operation. The image sensor has 4 8, 10 or 12 bit digital LVDS outputs (serial) or
one 10 bit parallel CMOS output. The image sensor also integrates a programmable gain amplifier and offset
regulation. Each LVDS channel runs at 480 Mbps maximum which results in 480 fps frame rate at full resolution.
Higher frame rates can be achieved in row-windowing mode or row-subsampling mode. These modes are all
programmable using the SPI interface. All internal exposure and read out timings are generated by a programmable
on-board sequencer. External triggering and exposure programming is also possible. Extended optical dynamic range
can be achieved by multiple integrated high dynamic range modes.
1.2 FEATURES



















648 * 488 active pixels on a 7.4µm pitch
8 Dark reference and dummy rows and columns
Frame rate 480 frames/sec @ 640 * 480 resolution
Row windowing capability
X-Y mirroring function
Master clock: 10-40MHz
4 LVDS-outputs @ 480Mbit/s (480 fps) multiplexable to 2 (240fps) and 1 (120 fps) outputs
One 10 bit parallel CMOS output running at maximum 40 MHz (120 fps)
LVDS control line with frame and line information
LVDS DDR output clock to sample data on the receiving end
12 bit ADC output at maximum frame rate
Multiple High Dynamic Range modes supported
On chip temperature sensor
On chip timing generation
On chip black reference
SPI-control
Chip scale package ( 8 x 8 BGA pins)
3.3V and 2.2V signaling
Available in panchromatic and Bayer (RGB)
1.3 SPECIFICATIONS










Full well charge: 20KeSensitivity: 6 V/lux.s (with microlenses)
Dark noise: 20e- RMS
Conversion factor: 0.2LSB/e- (12 bit mode) at recommended gain
Dynamic range: 60 dB
Extended dynamic range: piecewise linear response or interleaved read-out
Parasitic light sensitivity: 1/50 000
Dark current: 120 e/s (@ 25C die temperature)
Fixed pattern noise: <4 LSB (12 bit mode, <0.1% of full swing, standard deviation on full image)
Power consumption: 700mW
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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
1.4 CONNECTION DIAGRAM
2.2V
3.3V
3.3V
CLK_IN
4 LVDS outputs
1 parallel CMOS
output
SYS_RES_N
SPI_CLK
SPI_EN
SPI_IN
SPI_OUT
LVDS output
clock
CMV300
Image sensor
FRAME_REQ
LVDS control
signal
CMOS output
clock
Vdd
CMOS control
signal
Decoupling
pins
All ground pins
FIGURE 1: CONNECTION DIAGRAM FOR THE CMV300 IMAGE SENSOR
Please look at the pin list for a detailed description of all pins and their proper connections. Some optional pins are not
displayed on the figure above. The exact pin numbers can be found in the pin list and on the package drawing.
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CMV300 Datasheet
2
SENSOR ARCHITECTURE
2 or 1 output(s)
LVDS block
(drivers, multiplexers)
Pixel (4095,3071)
Analog front end (AFE)
(gain, offset, ADCs)
External driving
signals
sequencer
Active pixel area
480 rows
2 dark reference rows on top/bottom
640 columns
2 dark reference columns on left
2 test columns on right
Pixel (0,0)
Input clock
Analog front end (AFE)
(gain, offset, ADCs)
SPI & PLL
SPI signals
Temp
sensor
LVDS block
(drivers, multiplexers)
2 or 1 output(s)
FIGURE 2: SENSOR BLOCK DIAGRAM
Figure 2 shows the image sensor architecture. The internal sequencer generates the necessary signals for image
acquisition. The image is stored in the pixel (global shutter) and is then read out sequentially, row-by-row. On the pixel
output, an analog gain is possible. The pixel values then passes to a column ADC cell, in which ADC conversion is
performed. The digital signals are then read out over multiple LVDS channels or one parallel CMOS output. Each LVDS
channel reads out 324 adjacent columns of the array. Two rows are being read out at the same time when 4 LVDS
channels are used. In the Y-direction, rows of interest are selected through a row-decoder which allows a flexible
windowing. Control registers are foreseen for the programming of the sensor. These register parameters are uploaded
via a four-wire SPI interface. A temperature sensor which can be read out over the SPI interface is also included.
2.1 PIXEL ARRAY
The pixel array consists of 648 x 488 square global shutter pixels with a pitch of 7.4µm (7.4μm x 7.4μm). The pixels are
designed to achieve maximum sensitivity with low noise and low PLS specifications. Micro lenses are placed on top of
the pixels for improved fill factor and quantum efficiency (>50%). There are 4 dark reference rows available on the
sensor (rows 0, 1, 486 and 487) and 2 dark reference columns (column 0 and 1). Columns 646 and 647 are test
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CMV300 Datasheet
columns and do not contain useful image data. This means that the useable image data area is 644 x 484. This results
in an optical area of 1/3 optical inch (5.9 mm). This means that off-the-shelf C-mount lenses can be used.
2.2 ANALOG FRONT END
The analog front end consists of 2 major parts, a column amplifier block and a column ADC block.
The column amplifier prepares the pixel signal for the column ADC and applies analog gain if desired (programmable
using the SPI interface). The column ADC converts the analog pixel value to a 12 bit value. A digital offset can also be
applied to the output of the column ADC’s. All gain and offset settings can be programmed using the SPI interface.
2.3 LVDS BLOCK
The LVDS block converts the digital data coming from the column ADC into standard serial LVDS data running at
maximum 300Mbps. The sensor has 6 LVDS output pairs:



4 Data channels
1 Control channel
1 Clock channel
The 4 data channels are used to transfer 12-bit data words from sensor to receiver. The output clock channel
transports a DDR clock, synchronous to the data on the other LVDS channels. This clock can be used at the receiving
end to sample the data. The data on the control channel contains status information on the validity of the data on the
data channels, among other useful sensor status information. Details on the LVDS timing and format can be found in
section 4 of this document.
2.4 PARALLEL CMOS OUTPUT BLOCK
The parallel CMOS block sends the digital data coming from the column ADC to a standard CMOS parallel output
(supplied by VDD20) running at maximum 25MHz. The parallel output has 13 pins:



10 Data channels
2 Control channels
1 Clock channel
The 10 data channels are used to transfer 10-bit pixel data from the sensor to a receiver. The output clock channel
transports a clock, synchronous to the data on the data channels. This clock can be used at the receiving end to
sample the data. The data on the control channels contains status information on the validity of the data on the data
channels (LVAL, DVAL). Details on the parallel CMOS timing and format can be found in section 4 of this document.
2.5 SEQUENCER
The on-chip sequencer will generate all required control signals to operate the sensor from only a few external control
signals. This sequencer can be activated and programmed through the SPI interface. A detailed description of the SPI
registers and sensor (sequencer) programming can be found in section 5 of this document.
2.6 SPI INTERFACE
The SPI interface is used to load the sequencer registers with data. The data in these registers is used by the
sequencer while driving and reading out the image sensor. Features like windowing, subsampling, gain and offset are
programmed using this interface. The data in the on-chip registers can also be read back for test and debug of the
surrounding system. Section 5 contains more details on register programming.
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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
2.7 TEMPERATURE SENSOR
A 16-bit digital temperature sensor is included in the image sensor and can be read out through the SPI-interface. The
on-chip temperature can be obtained by reading out the registers with address 78 and 79 (in burst mode, see section
3.9.2 for more details on this mode).
A calibration of the temperature sensor is needed for absolute temperature measurements. A typical temperature
sensor output vs. temperature curve can be found below. The temperature sensor requires a running input clock
(CLK_IN), the other functions of the image sensor can be operational or in standby mode.
A typical value of the sensor at 0°C is about
𝑓[𝑀𝐻𝑧]
25
∗ 5100 DN. A typical slope will be around
𝑓[𝑀𝐻𝑧]
25
∗ 15.5 DN/°C. A
sensor will typically heat up about 15°C above ambient temperature.
Temperature Sensor
5900
y = 12.828x + 4907.9
5700
5500
Temp. Sensor value
dev1
dev2
5300
dev3
dev4
5100
dev5
Linear (dev2)
4900
4700
4500
-20
-10
0
10
20
30
Die Temperature [°C]
40
50
60
FIGURE 3: TYPICAL OUTPUT OF THE TEMPERATURE SENSOR OF SEVERAL CMV300 SENSORS @ 25MHZ
© 2016 CMOSIS bvba
70
80
Reference:CMV300-datasheet-v2.10
Page 13 of 55
CMV300 Datasheet
3 DRIVING THE CMV300
3.1 SUPPLY SETTINGS
The CMV300 image sensor has the following supply settings:
Supply
name
Usage
Recommended
value
Maximum
tolerance
DC Current
Idle
DC Current
Nom.
DC Current
Max.
VDD20
LVDS, ADC
2.2V
-0.4/+0.05V
175mA
220mA
270mA
VDD33
Dig. I/O. SPI, ADC
3.3V
+/-0.3V
25mA
30mA
30mA
VDDpix
Pixel array supply
3.0V
+/-0.3V
1mA
5mA
5mA
470mW
600mW
710mW
Total DC Power
See pin list for exact pin numbers for every supply.
The maximum currents will be reached during readout. The current of the VDD20 supply depends on the average
value of the image (a pure white image will draw 270mA). Idle is when the sensor is idle (not reading out or
integrating) and nominal is a 50% grey average image. These values are for a sensor running at 40MHz. The power
consumption decreases with the clock speed albeit little.
Besides these DC currents, decoupling should be foreseen to suppress current spikes. VDDPIX can generate current
spikes up to 500mA during FOT. Because this supply is the pixel array supply, the voltage should be as noise-free as
possible, because noise can ripple through to the image. We propose to use 5x 100nF capacitors on each supply as
close to the sensor as possible.
3.2 BIASING
For optimal performance, some pins need to be decoupled to ground or to VDD. Please refer to the pin list for a
detailed description for every pin and the appropriate decoupling if applicable.
3.3 DIGITAL INPUT PINS
The table below gives an overview of the external pins used to drive the sensor.
Pin name
CLK_IN
SYS_RES_N
FRAME_REQ
SPI_IN
SPI_EN
SPI_CLK
Description
Master input clock, frequency range between 10
and 40 MHz
System reset pin, active low signal. Resets the onboard sequencer and must be kept low during startup
Frame request pin. This signal should be at least one
period of CLK_IN long to assure detection.
Data input pin for the SPI interface. The data to
program the image sensor is sent over this pin.
SPI enable pin. When this pin is high the data should
be written/read on the SPI
SPI clock. This is the clock on which the SPI runs
(max 40Mz)
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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
Pin name
Description
T_EXP1
Input pin which can be used to program the
exposure time externally. This signal should be at
least one period of CLK_IN long to assure detection.
Input pin which can be used to program the
exposure time externally in interleaved high
dynamic range mode. This signal should be at least
one period of CLK_IN long to assure detection.
T_EXP2
3.4
ELECTRICAL IO SPECIFICATIONS
3.4.1 DIGITAL IO CMOS/TTL DC SPECIFICATIONS
Parameter
VIH
VIL
VOH
VOL
Description
High level input
voltage
Low level input
voltage
High level
output voltage
Low level output
voltage
Conditions
min
VDD=3.3V
IOH=-2mA
VDD=3.3V
IOL=2mA
2.0
typ
max
VDD33
V
Units
GND
0.8
V
2.4
V
0.4
V
3.4.2 PARALLEL CMOS OUTPUT DC SPECIFICATIONS
Parameter
VOH
VOL
Description
High level
output voltage
Low level output
voltage
Conditions
VDD20=2.2V
IOH=-2mA
VDD20=2.2V
IOL=2mA
min
typ
max
Units
2.0
V
0.2
V
3.4.3 LVDS RECEIVER SPECIFICATIONS
Parameter
VID
VIC
IID
∆IID
Description
Differential
input voltage
Receiver
input range
Receiver
input current
Receiver
input current
difference
Conditions
Steady state
min
100
Steady state
0.0
typ
350
VINP|INN=1.2V±50mV,
0≤ VINP|INN≤2.4V
|IINP – IINN|
max
Units
600
mV
2.4
V
20
µA
6
µA
3.4.4 LVDS DRIVER SPECIFICATIONS
Parameter
VOD
∆VOD
VOC
Description
Differential
output voltage
Difference in
VOD between
complementary
output states
Common mode
voltage
Conditions
Steady State, RL
= 100Ω
Steady State, RL
= 100Ω
Steady State, RL
= 100Ω
min
247
1.125
© 2016 CMOSIS bvba
typ
350
1.25
max
Units
454
mV
50
mV
1.375
V
Reference:CMV300-datasheet-v2.10
Page 15 of 55
CMV300 Datasheet
Parameter
∆VOC
IOS,GND
IOS,PN
Description
Difference in
VOC between
complementary
output states
Output short
circuit current
to ground
Output short
circuit current
Conditions
Steady State, RL
= 100Ω
min
typ
max
Units
50
mV
VOUTP=VOUTN=GND
24
mA
VOUTP=VOUTN
12
mA
3.5 INPUT CLOCK
The input clock (CLK_IN) defines the output data rate of the CMV300. This master clock (CLK_IN) is 12 times slower
than the output date rate. The maximum data rate of the output is 480Mbps which results in a CLK_IN of 40MHz. The
minimum frequency is 10MHz for CLK_IN. Any frequency between the minimum and maximum can be applied by the
user and will result in a corresponding output data rate. The SPI register with address 83 must be programmed to the
correct frequency range when the CLK_IN frequency is changed.
3.6 FRAME RATE CALCULATION
The frame rate of the CMV300 is defined by 2 main factors.
1.
2.
Exposure time
Read out time
For ease of use we will assume that the exposure time is no longer than the read out time. By assuming this the frame
rate is completely defined by the read out time (because the exposure time happens in parallel with the read-out
time). The read-out time (and thus the frame rate) is defined by:
1.
2.
3.
Output clock speed: max 480Mbps
Number of lines read-out
Number of outputs used: max 4 LVDS outputs (2 on the top and 2 on the bottom) or one parallel CMOS
output
This means that if any of the parameters above is changed, it will have an impact on the frame rate of the CMV300. In
normal operation (4 outputs @ 480Mbps, 12 bit and full resolution) this will result in 480 fps.
Total readout time is composed of two parts: FOT (frame overhead time) + image readout time.
𝐹𝑂𝑇 = (
4
𝑟𝑒𝑔58
) ∗ 325 ∗ 𝑐𝑙𝑘_𝑝𝑒𝑟
+
# 𝑏𝑜𝑡𝑡𝑜𝑚 𝑜𝑢𝑡𝑝𝑢𝑡𝑠 𝑢𝑠𝑒𝑑
4
With clk_per being the period of CLK_IN. The FOT consists of a time where the pixels are prepared for read out:
𝑟𝑒𝑔58
) ∗ 325 ∗ 𝑐𝑙𝑘_𝑝𝑒𝑟
4
And an idle time until read out starts, depending on the used channels:
(
(
4
) ∗ 325 ∗ 𝑐𝑙𝑘_𝑝𝑒𝑟
# 𝑏𝑜𝑡𝑡𝑜𝑚 𝑜𝑢𝑡𝑝𝑢𝑡𝑠 𝑢𝑠𝑒𝑑
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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
With clk_per being equal to one period of CLK_IN and reg58 should be a multiple of 4. The FOT consists of the actual
FOT (where the control channel FOT bit is ‘1’) and 2 (using 4 outputs) or 4 (using 2 or 1 outputs) line times where the
sensor is idle before read out starts.
When running the CMV300 sensor at 40MHz with 4 outputs and recommended FOT settings this results in: 105.625us.
# 𝑙𝑖𝑛𝑒𝑠
𝑅𝑒𝑎𝑑𝑜𝑢𝑡 𝑡𝑖𝑚𝑒 = 𝑙𝑖𝑛𝑒 𝑡𝑖𝑚𝑒 ∗
# 𝑠𝑖𝑑𝑒𝑠 𝑢𝑠𝑒𝑑
𝐿𝑖𝑛𝑒 𝑡𝑖𝑚𝑒 =
2 ∗ 325 ∗ 𝑐𝑙𝑘_𝑝𝑒𝑟
# 𝑏𝑜𝑡𝑡𝑜𝑚 𝑜𝑢𝑡𝑝𝑢𝑡𝑠 𝑢𝑠𝑒𝑑
When running the CMV300 sensor at 40MHz with 4 outputs and reading 480 lines this results in: 1950µs
This results in a total read-out time of 105.625us + 1950µs = 2.055625ms  486fps for 640 * 480 resolution.
3.7 START-UP SEQUENCE
The following sequence should be followed when the CMV300 is started up in default output mode (300Mbps, 12bit
resolution).
Stabelization time
1μs
Supply
CLK_IN
SYS_RES
1μs
Frame_REQ
FIGURE 4: START-UP SEQUENCE FOR 300MBPS @ 12-BIT
The master clock (25MHz for 300Mbps in 12-bit mode) should only start after the supplies are stable. The external
reset pin should be released at least 1μs after the supplies have become stable. The first frame can be requested 1μs
after the reset pin has been released. An optional SPI upload (to program the sequencer) is possible 1μs after the
reset pin has been released. In this case the FRAME_REQ pulse must be postponed until after the SPI upload has been
completed.
When the CMV300 will be used in 8 or 10-bit mode or at another speed than 300mbps, an SPI upload is necessary to
program the sensor. In this case the start-up sequence looks like the diagram below. A PLL lock-time of 1ms should be
considered after uploading the register settings and before sending the FRAME_REQ pulse.
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CMV300 Datasheet
Stable time
1μs
Supply
CLK_IN
1μs
SYS_RES_N
1ms
FRAME_REQ
SPI upload
SPI settings
FIGURE 5: START-UP SEQUENCE FOR 8 OR 10 BIT MODE OR ANOTHER SPEED
The following SPI registers should be uploaded in this mode:
1.
2.
Bit mode settings (address 68) : set to 8 or 10 bit mode
PLL settings (address 83): set to correct PLL range
3.8 RESET SEQUENCE
If a sensor reset is necessary while the sensor is running the following sequence should be followed.
CLK_IN
1μs
SYS_RES_N
FRAME_REQ
FIGURE 6: RESET SEQUENCE
The on-board sequencer will be reset and all programming registers will return to their default start-up values when a
falling edge is detected on the SYS_RES_N pin. After the reset there is a minimum time of 1μs needed before a
FRAME_REQ pulse can be sent. When a lower clock speed is desired while the sensor is running the reset sequence
should be executed. In this case it must be followed by a SPI upload to program the sensor for this lower clock speed.
3.9 SPI PROGRAMMING
Programming the sensor is done by writing the appropriate values to the on-board registers. These registers can be
written over a simple serial interface (SPI). The details of the timing and data format are described below. The data
written to the programming registers can also be read out over this same SPI interface.
SPI I/O’s are pulled low when not used/enabled.
3.9.1 SPI WRITE
The timing to write data over the SPI interface can be found below.
SPI_EN
½ CLK
1 CLK
SPI_CLK
SPI_IN
C=’1'
A6
A5
A4
A3
A2
A1
A0
D7
D6
FIGURE 7: SPI WRITE TIMING
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D5
D4
D3
D2
D1
D0
Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
The data is sampled by the CMV300 on the rising edge of the SPI_CLK. The SPI_CLK has a maximum frequency of
40MHz. The SPI_EN signal has to be high for half a clock period before the first databit is sampled. SPI_EN has to
remain high for 1 clock period after the last databit is sampled. The sampled data will be written in the sequencer on
the last falling clock edge, so SPI_CLK has to go low again at the end for the write operation to be successful.
One write action contains 16 databits:


One control bit: First bit to be sent, indicates whether a read (‘0’) or write (‘1’) will occur on the SPI interface.
7 address bits: These bits form the address of the programming register that needs to be written. The
address is sent MSB first.
8 data bits: These bits form the actual data that will be written in the register selected with the address bits.
The data is written MSB first.

When several sensor registers need to be written, the timing above can be repeated with SPI_EN remaining high all
the time. See the figure below for an example of 2 registers being written in burst.
½ CLK
SPI_EN
1 CLK
SPI_CLK
SPI_IN
C=’1'
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
C=’1'
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 8: SPI WRITE TIMING FOR 2 REGISTERS IN BURST
3.9.2 SPI READ
The timing to read data from the registers over the SPI interface can be found below.
SPI_EN
½ CLK
1 CLK
SPI_CLK
SPI_IN
C=’0'
A6
A5
A4
A3
A2
A1
SPI_OUT
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 9: SPI READ TIMING
To indicate a read action over the SPI interface, the control bit on the SPI_IN pin is made ‘0’. The address of the
register being read out is sent immediately after this control bit (MSB first). After the LSB of the address bits, the data
is launched on the SPI_OUT pin on the falling edge of the SPI_CLK. This means that the data should be sampled by the
receiving system on the rising edge of the SPI_CLK. The data comes over the SPI_OUT with MSB first. When reading
out the temperature sensor over the SPI, addresses 78 and 79 should be read out in burst mode (keep SPI_EN high).
When SPI_EN is low, SPI_OUT will be (pulled) low.
3.10 REQUESTING A FRAME
After starting up the sensor (see section 3.7), a number of frames can be requested by sending a FRAME_REQ pulse.
The number of frames can be set by programming the appropriate register (addresses 55 and 56). The default number
of frames to be grabbed is 1.
In internal-exposure-time mode, the exposure time will start after this FRAME_REQ pulse. In the external-exposuretime mode, the read-out will start after the FRAME_REQ pulse. Both modes are explained into detail in the sections
below.
3.10.1 INTERNAL EXPOSURE CONTROL
In this mode, the exposure time is set by programming the appropriate registers (address 42-44) of the CMV300.
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CMV300 Datasheet
After the high state of the FRAME_REQ pulse is detected, the exposure time will start immediately. When the
exposure time ends (as programmed in the registers), the pixels are being sampled and prepared for read-out. This
sequence is called the frame overhead time (FOT). After the FOT, the frame is read-out automatically. If more than
one frame is requested, the exposure of the next frame starts already during the read-out of the previous one
(pipeline mode). See the diagram below for more details.
FRAME_REQ
Frame1_cycle
Exposure time
FOT
Frame2_cycle
Read-out time
Exposure time
FOT
Read-out time
FIGURE 10: REQUEST FOR 2 FRAMES IN INTERNAL- EXPOSURE-TIME MODE
When the exposure time is shorter than the read-out time, the FOT and read-out of the next frame will start
immediately after the read-out of the previous frame.
FRAME_REQ
Frame1_cycle
Exposure time
FOT
Frame2_cycle
Read-out time
Exposure time
FOT
Read-out time
FIGURE 11: REQUEST FOR 2 FRAMES IN INTERNAL-EXPOSURE-TIME MODE WITH EXPOSURE TIME < READ-OUT TIME
3.10.2 EXTERNAL EXPOSURE CONTROL
The exposure time can also be programmed externally by using the T_EXP1 input pin. This mode needs to be enabled
by setting the appropriate register (address 41). In this case, the exposure starts when a high state is detected on the
T_EXP1 pin. When a high state is detected on the FRAME_REQ input, the exposure time stops and the read-out will
start automatically. A new exposure can start by sending a pulse to the T_EXP1 pin during or after the read-out of the
previous frame.
T_EXP1
FRAME_REQ
Frame1_cycle
Exposure time
FOT
Read-out time
Frame2_cycle
Exposure time
FOT
Read-out time
FIGURE 12: REQUEST FOR 2 FRAMES USING EXTERNAL-EXPOSURE-TIME MODE
3.10.3 EXPOSURE DELAY
In internal exposure mode, when reading out an image with an exposure time smaller than the number of lines read
out divided by the number outputs used, there will be increase in delay between the frame_req pulse and the actual
start of exposure. This delay is equal to:
exposure start delay = (196 * clk_per) + (
# lines
− inte_time)
# sides
With a minimum of 196 clk_in periods.
For example, when a complete image (488 lines) is read out with 2 sided outputs, and the integration time is 1 line
time, the delay will be 244.66 lines. When the integration time is 100 lines, the delay will be 145.66 lines.
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CMV300 Datasheet
Frame_req
INTE
INTE
READ OUT
READ OUT
INTE
READ OUT
INTE = < 244
INTE = 244
INTE = >244
FIGURE 13: EXPOSURE DELAY
st
If the integration time is longer than the readout time, the delay will always be the minimum. The 1 frame after a
reset will always have the minimum delay only.
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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
4 READING OUT THE SENSOR
When reading out the CMV300, the user has a choice to use 4 LVDS outputs (max 480fps) or 1 parallel CMOS output
(max 120 fps). This choice is made by connecting pin B2 to VDD33 (LVDS outputs) or GND (parallel CMOS output).
4.1 LVDS DATA OUTPUTS
The CMV300 has LVDS (low voltage differential signaling) outputs to transport the image data to the surrounding
system. Next to 4 data channels, the sensor also has two other LVDS channels for control and synchronization of the
image data. In total, the sensor has 6 LVDS output pairs (2 pins for each LVDS channel):



4 Data channels
1 Control channel
1 Clock channel
This means that a total of 12 pins of the CMV300 are used for the LVDS outputs (8 for data + 2 for LVDS clock + 2 for
control channel). See the pin list for the exact pin numbers of the LVDS outputs. The 4 data channels are used to
transfer the 12-bit, 10-bit or 8-bit pixel data from the sensor to the receiver in the surrounding system. The output
clock channel transports a clock, synchronous to the data on the other LVDS channels. This clock can be used at the
receiving end to sample the data. This clock is a DDR clock which means that the frequency will be half of the output
data rate. When 480Mbps output data rate is used, the LVDS output clock will be 240MHz. The data on the control
channel contains status information on the validity of the data on the data channels. Information on the control
channel is grouped in 12-bit words that are transferred synchronous to the 4 data channels.
4.1.1 LVDS LOW-LEVEL PIXEL TIMING
The figures below show the timing for transfer of 8-bit, 10-bit and 12-bit pixel data over one LVDS output. To make the
timing more clear, the figures show only the p-channel of each LVDS pair. The data is transferred LSB first, with the
transfer of bit D[0] during the high phase of the DDR output clock.
T1
LVDS_CLOCK_OUT
DATA_OUT
‘0’
‘0’
‘0’
‘0’
D(0)
D(1)
D2)
D(3)
D(4)
D(5)
D(6)
D(7)
‘0'
‘0’
‘0’
‘0’
D(8)
D(9)
‘0’
‘0’
D(0)
D(1)
D(1)
D2)
D(3)
FIGURE 14: 8-BIT PIXEL DATA ON AN LVDS CHANNEL
T1
LVDS_CLOCK_OUT
DATA_OUT
‘0’
‘0’
D(0)
D(1)
D2)
D(3)
D(4)
D(5)
D(6)
D(7)
FIGURE 15: 10-BIT PIXEL DATA ON AN LVDS CHANNEL
T1
LVDS_CLOCK_OUT
DATA_OUT
D(0)
D(1)
D2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9) D(10) D(11) D(0)
FIGURE 16: 12-BIT PIXEL DATA ON AN LVDS CHANNEL
The time ‘T1’ in the diagram above is 1/12th of the period of the input clock (CLK_IN) of the CMV300. If a frequency of
40MHz is used for CLK_IN (max), this results in a 240MHz LVDS_CLOCK_OUT.
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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
4.1.2 LVDS READOUT TIMING
The readout of image data is grouped in bursts of 324 pixels per channel (2 rows at the same time). Each pixel is 12
bits of data (see section 4.1.1). One complete pixel period equals one period of the master clock input. For details on
pixel remapping and pixel vs channel location please see section 4.1.3 of this document. An overhead time exists
between two bursts of 324 pixels. This overhead time has the length of one pixel read-out (i.e. the length of 12 bits at
the selected data rate) or one master clock cycle.
4.1.2.1 4 OUTPUT CHANNELS
By default, all 4 data output channels are used to transmit the image data. This means that two entire rows of image
data are transferred in one slot of 324 pixel periods (4 x 324 = 1296). Next figure shows the timing for the top and
bottom LVDS channels.
DATA_OUT_BOTTOM
IDLE
OH
324
OH
Row 1
DATA_OUT_TOP
IDLE
OH
324
OH
324
Row 3
324
OH
Row 2
Row 5
324
OH
324
Row 4
Row 6
FIGURE 17: OUTPUT TIMING IN DEFAULT 4 CHANNEL MODE
Only when 4 data outputs, running at 300Mbps, are used, the frame rate of 300fps can be achieved (default).
4.1.2.2 2 OUTPUT CHANNELS
The CMV300 has the possibility to use only 2 LVDS output channels. This setting can be programmed in the register
with address 57 (see section 5.7). In such multiplexed output mode, only the 2 bottom LVDS channels are used
(channel 1 and channel 2). The readout of one row takes 1*324 periods. Next figure shows the timing for the bottom
LVDS channels.
DATA_OUT_BOTTOM
IDLE
OH
324
OH
Row 1
324
OH
324
Row 2
Row 3
FIGURE 18: OUTPUT TIMING IN 2 CHANNEL MODE
In this 2 channel mode, the frame rate is reduced with a factor of 2 compared to 4 channel mode.
4.1.2.3 1 OUTPUT CHANNEL
The CMV300 has also the possibility to use only 1 LVDS output channel. This setting can be programmed in the register
with address 57 (see section 5.7). In such multiplexed output mode, only 1 of the bottom 2 LVDS channels is used
(channel 1) and the readout of one row takes 2*324 periods.
DATA_OUT_BOTTOM
IDLE
OH
324
OH
324
OH
Row 1
324
OH
324
Row 2
FIGURE 19: OUTPUT TIMING IN OF 1 CHANNEL MODE
In this 1 channel mode, the frame rate is reduced with a factor of 4 compared to 4 channel mode.
4.1.3 PIXEL REMAPPING
Depending on the number of output channels, the pixels are read out by different channels and come out at a
different moment in time. With the details from the next sections, the end user is able to remap the pixel values at the
output to their correct image array location.
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CMV300 Datasheet
4.1.3.1 4 OUTPUTS
The figure below shows the location of the image pixels versus the output channel of the image sensor.
Channel 1
IDLE
Pixel 0 to 323
Pixel 0 to 323
Bottom
channels
Channel 2
Channel 3
IDLE
IDLE
Pixel 324 to 647
Pixel 324 to 647
Row 1
Row 3
Pixel 0 to 323
Pixel 0 to 323
Top
channels
Channel 4
IDLE
Pixel 324 to 647
Pixel 324 to 647
Row 2
Row 4
FIGURE 20: PIXEL REMAPPING FOR 4 OUTPUT CHANNELS
4 bursts (2 x 2) of 324 pixels happen in parallel on the data outputs. This means that two complete rows are read out
in one burst. The amount of rows that will be read out depends on the value in the corresponding register. By default
there are 488 rows being read out.
4.1.3.2 2 OUTPUTS
When only 2 outputs are used, the pixel data is placed on the outputs as detailed in the figure below. 2 bursts of 324
pixels happen in parallel on the data outputs. This means that one complete row is read out in one burst. The time
needed to read out two rows is doubled compared to when 4 outputs are used. The top LVDS channels are not being
used in this mode, so they can be turned off by setting the correct bits in the register with address 81. Turning off
these channels will reduce the power consumption of the chip. The amount of rows that will be read out depends on
the value in the corresponding register. By default there are 488 rows being read out.
Channel 1
IDLE
Pixel 0 to 323
Pixel 0 to 323
Bottom
channels
Channel 2
IDLE
Pixel 324 to 647
Pixel 324 to 647
Row 1
Row 2
FIGURE 21: PIXEL REMAPPING FOR 2 OUTPUT CHANNELS
4.1.3.3 1 OUTPUT
When only 1 output is used, 1 burst of 324 pixels happens on the data outputs. This means that one complete row is
read out in 2 bursts. The time needed to read out one row is 2x longer compared to when 2 outputs are used. The top
LVDS channels are not being used in this mode, so these and the remaining bottom channel can be turned off by
setting the correct bits in the register with address 81. Turning off these channels will reduce the power consumption
of the chip. The amount of rows that will be readout depends on the value in the corresponding register. By default
there are 488 rows being read out
Channel 1
IDLE
Pixel 0 to 323
Pixel 324 to 647
Pixel 0 to 323
Row 1
Pixel 324 to 647
Row 2
FIGURE 22: PIXEL REMAPPING FOR 1 OUTPUT CHANNEL
4.1.4 CONTROL CHANNEL
The CMV300 has one LVDS output channel dedicated for the valid data synchronization and timing of the output
channels. The end user must use this channel to know when valid image data or training data is available on the data
output channels.
The control channel transfers status information in 12-bit word format. Every bit of the word has a specific function.
Next table describes the function of the individual bits.
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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
Bit
Function
Description
[0]
DVAL
Indicates valid pixel data on the outputs
[1]
LVAL
Indicates validity of the readout of a row
[2]
FVAL
Indicates the validity of the readout of a frame
[3]
FOT
Indicates when the sensor is in FOT (sampling of image data in pixels) (*)
[4]
INTE1
Indicates when pixels of integration block 1 are integrating (*)
[5]
INTE2
Indicates when pixels of integration block 2 are integrating (*)
[6]
‘0’
Constant zero
[7]
‘1’
Constant one
[8]
‘0’
Constant zero
[9]
‘0’
Constant zero
[10]
‘0’
Constant zero
[11]
‘0’
Constant zero
(*)Note: The status bits are purely informational. These bits are not required to know when the data is valid. The
DVAL, LVAL and FVAL signals are sufficient to know when to sample the image data.
Pin C6 (Test3 / CLK_OUT) can be programmed to map some control bits for easy measurement. Register 69 is used for
this programming:
Register 69 Value
0
1
2
6
7
8
9
T_dig1
DVAL
LVAL
FVAL
FOT
INTE1
INTE2
CLK_OUT
4.1.4.1 DVAL, LVAL, FVAL
The first three bits of the control word must be used to identify valid data and the readout status. Next figure shows
the timing of the DVAL, LVAL and FVAL bits of the control channel with an example of the readout of a frame of 3 rows
(default is 488 rows). This example uses the default mode of 4 outputs (2 outputs on each side).
DATA_OUT
IDLE
OH
324
OH
324
OH
324
DVAL
LVAL
FVAL
FIGURE 23: DVAL, LVAL AND FVAL TIMING IN 4 OUTPUT MODE
When only 1 output (on one side) is used, the line read-out time is 2x longer. The control channel takes this into
account and the timing in this mode looks like the diagram below.
DATA_OUT
IDLE
OH
324
OH
324
OH
324
OH
324
OH
324
OH
324
DVAL
LVAL
FVAL
FIGURE 24: DVAL, LVAL AND FVAL TIMING IN 1 OUTPUT MODE
4.1.5 TRAINING DATA
The LVDS outputs are not perfectly edge aligned. This alignment has to be done in the receiving system. You can see
the typical output skew in Figure 25. This skew is independent of the clock speed used. To synchronize the receiving
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CMV300 Datasheet
side with the LVDS outputs of the CMV300, a known data pattern can be put on the output channels. This pattern can
be used to “train” the LVDS receiver of the surrounding system to achieve correct bit and word alignment of the image
data. Such a training pattern is put on all 4 data channel outputs when there is no valid image data to be sent (in idle,
exposure and in between bursts of 324 pixels). The TP is not present during the 2 or 4 idle line times after FOT and
before FVAL. The training pattern is a 12-bit data word that replaces the pixel data. The sensor has a 12-bit sequencer
register (address 61-62) that can be loaded through the SPI to change the contents of the 12-bit training pattern.
T1
CTR
D(0)
D(1)
D2)
-100ps
CH1
D(0)
D(1)
D2)
200ps
D(0)
CH2
D(1)
D2)
800ps
D(0)
CH3
D(1)
D2)
200ps
D(0)
CH4
D(1)
D2)
800ps
FIGURE 25: LVDS OUTPUT SKEW
The control channel does not send a training pattern, because it is used to send control information at all time. Word
alignment can be done on this channel when the sensor is idle (not exposing or sending image data). In this case all
bits of the control word are zero, except for bit [7].
The figure below shows the location of the training pattern (TP) on the data channels and control channels when the
sensor is in idle mode and when a frame of 3 rows is read-out. The default mode of 4 outputs is selected.
Sensor in idle mode
DVAL
LVAL
FVAL
Data
channels
Training pattern
Control
channel
Training pattern
TP
324
TP
324
TP
324
Control information
FIGURE 26: TRAINING PATTERN LOCATION IN THE DATA CHANNEL AND CONTROL CHANNEL
CMV300 OUTPUT TIMING
Frame cycle
EXPOSURE
FOT
READ OUT
EXPOSURE
FOT
READ OUT
DVAL
LVAL
FVAL
FOT
INTE1
INTE2
BIT[11:6]
000010
DATA OUT
Training
Training
Pattern
Pattern
(TP)
xxx
Pixel Data + TP
TP
xxx
Pixel Data + TP
DVAL
xxx = random,
undefined data
LVAL
For
FVAL
DATA OUT
xxx
Data
TP
Data
TP
Data
TP
Data
TP
Data
TP
FIGURE 27: DETAILED TIMING DIAGRAM
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Data
TP
Data
TP
Data
4 * 325 * clk_per
#bot outputs used
Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
4.2 PARALLEL CMOS OUTPUT
When pin B2 is connected to GND, the CMV300 also has one 10 bit digital parallel CMOS output. On this output the
pixels of the image array are presented with a frequency of maximum 40MHz resulting in a frame rate of 120 fps. Next
to the data channels 3 additional CMOS channels are available for control and synchronization of the image data.



10 Data channels (bit[0] to bit[9], VDD20 CMOS)
2 Control channels (DVAL and LVAL, VDD20 CMOS)
1 Clock channel (CLK_OUT, 3.3V CMOS)
This means that a total of 13 pins of the CMV300 are used for the parallel CMOS output (10 for data + 2 for control
channel + 1 for clock channel). See the pin list for the exact pin numbers of the parallel CMOS output. The 10 data
channels are used to transfer the 10-bit pixel data from the sensor to the receiver in the surrounding system. The
output clock channel transports a clock, synchronous to the data on the data channels. Register 69 has to be set to 9
to output this clock. This clock can be used at the receiving end to sample the data. The data on the control channels
contains status information on the validity of the data on the data channels.
4.2.1 PARALLEL OUTPUT TIMING
In parallel output mode, the readout of one row takes 2*324 periods. In this mode, the frame rate is reduced with a
factor of 4 compared to 4 LVDS channel mode. The figure below shows the timing for read-out of one line
LVAL
DVAL
T1
CLK_OUT
DATA_OUT
Pixel 0
Pixel 1
Pixel 2
Pixel 322
Pixel 323
INVALID
Pixel 324
Pixel 325
Pixel 326
Pixel 646
Pixel 647
FIGURE 28: PARALLEL OUTPUT TIMING OF ONE LINE
The time of ‘T1’ from the figure above and below has the same length as the period of the CLK_IN signal. As can be
seen in the figure above it is advised to sample the parallel output data on the falling edge of the CLK_OUT.
The figure below details the LVAL and DVAL timing for a frame read-out of tree lines.
T1
LVAL
DVAL
T1
Row 1
T1
Row 2
FIGURE 29: LVAL/DVAL TIMING FOR A FRAME OF 3 LINES USING THE PARALLEL OUTPUT
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Row 3
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CMV300 Datasheet
5 IMAGE SENSOR PROGRAMMING
This section explains how the CMV300 can be programmed using the on-board sequencer registers.
5.1 EXPOSURE MODES
The exposure time can be programmed in two ways, externally or internally. Externally, the exposure time is defined
as the time between the rising edge of T_EXP1 and the rising edge of FRAME_REQ (see section 3.10 for more details).
Internally, the exposure time is set by uploading the desired value to the corresponding sequencer register.
The table below gives an overview of the registers involved in the exposure mode.
Register name
Exp_ext
Register address
41[0]
Exp_time
42-44
Exposure time settings
Default value
Description of the value
0
0: Exposure time is defined by the value uploaded in the
sequencer register (42-44)
1: Exposure time is defined by the pulses applied to the
T_EXP1 and FRAME_REQ pins.
488
When the Exp_ext register is set to ‘0’, the value in this
register defines the exposure time according to the
following formula: Exp_time x 325 x clk_per, where clk_per
is the period of the master input clock. The minimal value
for this is 1.
To calculate the exact exposure time when using internal exposure mode (Exp_ext = 0) use:
𝐸𝑥𝑝𝑜𝑠𝑢𝑟𝑒 𝑡𝑖𝑚𝑒 = ((Exp_time − 1) ∗ 325 + [163 + (48 ∗ 𝑟𝑒𝑔58)]) ∗ clk_per
Clk_per is the period of the input CLK_IN clock (or LVDS input clock divided by 12). The part [163 + (48*reg58)] should
always be a multiple of 325. So the “163” term depends on the value of reg58.
For external exposure mode (Exp_ext = 1) this becomes:
𝐸𝑥𝑝𝑜𝑠𝑢𝑟𝑒 𝑡𝑖𝑚𝑒 = Ext_exp_time + (48 ∗ reg58 ∗ clk_per)
Ext_exp_time is the time between the T_EXP1/2 and Frame_req pulses.
The 163 + (48 * reg58) or 48*reg58 is the part of the FOT for which the sensor is light sensitive (called exposure
overlap) and will therefore determine the minimum exposure time. Below you can see the detailed timing of one
frame cycle in internal exposure mode with Exp_time = 244, reg58 = 44, line time = 325*clk_per and clk_per is the
period of the master CLK_IN without multiplexing.
Frame_REQ
Exposure overlap = min. exposure
7 * 325 * clk_per
Frame_cycle
Exposure time
244 * 325 * clk_per
FOT
Read-out time
13 * 325 * clk_per
244 * 325 * clk_per
Actual exposure time = 251 * 325 * clk_per
FIGURE 30: FRAME CYCLE TIMING
th
We see that 163 + (48*reg58) = 7 * 325. So the exposure overlap during FOT is 7/13 of the total FOT.
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CMV300 Datasheet
5.2 HIGH DYNAMIC RANGE MODES
The sensor has different ways to achieve high optical dynamic range in the grabbed image.


Interleaved read-out: the odd and even columns have a different exposure time
Piecewise linear response: pixels respond to light with a piecewise linear response curve.
All the HDR modes mentioned above can be used in both the internal- and external-exposure-time mode.
5.2.1 INTERLEAVED READ -OUT
In this HDR mode, the odd and even columns of the image sensors will have a different exposure time. This mode can
be enabled by setting the register in the table below.
Register name
Exp_dual
HDR settings – interleaved read-out
Register address Default value
Description of the value
41[1]
0
0: interleaved exposure mode disabled
1: interleaved exposure mode enabled
The surrounding system can combine the image of the odd columns with the image of the even columns which can
result in a high dynamic range image. In such an image very bright and very dark objects are made visible without
clipping. The table below gives an overview of the registers involved in the interleaved read-out when the internal
exposure mode is selected.
Register name
Exp_time
Register address
42-44
Exp_time2
45-47
HDR settings – interleaved read-out
Default value
Description of the value
488
When the Exp_dual register is set to ‘1’, the value in this
register defines the exposure time for the even columns
according following formula: Exp_time x 325 x clk_per,
where clk_per is the period of the master input clock.
488
When the Exp_dual register is set to ‘1’, the value in this
register defines the exposure time for the odd columns
according following formula: Exp_time2 x 325 x clk_per,
where clk_per is the period of the master input clock.
When the external exposure mode and interleaved read-out are selected, the different exposure times are achieved
by using the T_EXP1 and T_EXP2 input pins. T_EXP1 defines the exposure time for the even columns, while T_EXP2
defines the exposure time for the odd columns. See the figure below for more details.
T_EXP1
T_EXP2
Exposure time even columns
Exposure time odd columns
FRAME_REQ
FIGURE 31: INTERLEAVED READ-OUT IN EXTERNAL EXPOSURE MODE
When a color sensor is used, the sequencer should be programmed to make sure it takes the Bayer pattern into
account when doing interleaved read-out. This can be done by setting the appropriate register to ‘0’.
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CMV300 Datasheet
Register name
Color
Register address
39[0]
Color/mono
Default value
Description of the value
1
0: color sensor is used
1: monochrome sensor is used
5.2.2 PIECEWISE LINEAR RESPONSE
The CMV300 has the possibility to achieve a high optical dynamic range by using a piecewise linear response. This
feature will clip illuminated pixels which reach a programmable voltage, while leaving the darker pixels untouched.
The clipping level can be adjusted 2 times within one exposure time to achieve a maximum of 3 slopes in the response
curve. More details can be found in the figure below.
Pixel reset
Pixel sample
Vhigh
Vtfl2
Vtfl3
Vlow
Exp_kp1
Exp_kp2
Total exposure time
FIGURE 32: PIECEWISE LINEAR RESPONSE DETAILS
In the figure above, the red lines represent a pixel on which a large amount of light is falling. The blue line represents a
pixel on which less light is falling. As shown in the figure, the bright pixel is held to a programmable voltage for a
programmable time during the exposure time. This happens two times to make sure that at the end of the exposure
time the pixel is not saturated. The darker pixel is not influenced and will have a normal response. The Vtfl voltages
and different exposure times are programmable using the sequencer registers. Using this feature, a response as
detailed in the figure below can be achieved. The placement of the kneepoints in X is controlled by the Vtfl
programming, while the slope of the segments is controlled by the programmed exposure times.
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CMV300 Datasheet
Saturation
level
Output signal
Kneepoint 2
Kneepoint 1
# of electrons
FIGURE 33: PIECEWISE LINEAR RESPONSE
When using the PLR mode, the CDS for the second and third slope is not available anymore, increasing the FPN for
these slopes. Also the noise will become higher in this mode.
5.2.2.1 P IECEWISE LINEAR RESPONSE WITH INTERNAL EXPOSURE MODE
The following registers need to be programmed when a piecewise linear response in internal exposure mode is
desired.
Register name
Exp_time
Register address
42-44
Nr_slopes
54[1:0]
Exp_kp1
48-50
Exp_kp2
51-53
Vtfl2
113[6:0]
Vtfl3
114[6:0]
HDR settings – PLR
Default value
Description of the value
488
The value in this register defines the total exposure time
according following formula: Exp_time x 325 x clk_per,
where clk_per is the period of the master input clock.
1
The value in this register defines the number of slopes
(min=1, max=3).
1
The value in this register defines the exposure time from
kneepoint 1 to the end of the total exposure time. Formula:
Exp_kp1 x 325 x clk_per, where clk_per is the period of the
master input clock.
1
The value in this register defines the exposure time from
kneepoint 2 to the end of the total exposure time. Formula:
Exp_kp2 x 325 x clk_per, where clk_per is the period of the
master input clock.
64
The value in this register defines the Vtfl2 voltage (DAC
setting) of kneepoint 1.
Bit[6] = enable (=1)
Bit[5:0] = value (0-63)
64
The value in this register defines the Vtfl3 voltage (DAC
setting) of kneepoint 2.
Bit[6] = enable (=1)
Bit[5:0] = value (0-63)
5.2.2.2 PIECEWISE LINEAR RESPONSE WITH EXTERNAL EXPOSURE MODE
When external exposure time is used and a piecewise linear response is desired, the following registers should be
programmed.
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CMV300 Datasheet
Register name
Nr_slopes
Register address
54
Vtfl2
113[6:0]
Vtfl3
114[6:0]
HDR settings – PLR
Default value
Description of the value
1
The value in this register defines the number of slopes
(min=1, max=3).
64
The value in this register defines the Vtfl2 voltage (DAC
setting) of kneepoint 1.
Bit[6] = enable (=1)
Bit[5:0] = value (0-64)
64
The value in this register defines the Vtfl3 voltage (DAC
setting) of kneepoint 2.
Bit[6] = enable (=1)
Bit[5:0] = value (0-64)
The timing that needs to be applied in this external exposure mode looks like the one below.
T_EXP1
Frame_REQ
Total exposure time
Exposure kp2
Exposure kp1
FIGURE 34: PIECEWISE LINEAR RESPONSE WITH EXTERNAL EXPOSURE MODE
In this case the T_EXP1 pulses should be one CLK_IN period wide exactly. When shorter, they might not be detected
and when longer, this will be seen as 2 (or more) pulses one after the other, which will not give a useable image.
Please note, that a combination of the piecewise linear response and interleaved read-out is not possible.
5.3 WINDOWING
To limit the amount of data or to increase the frame rate of the sensor, windowing in Y direction is possible. The
number of lines and start address can be set by programming the appropriate registers. The CMV300 has the
possibility to read out multiple (max=8) predefined subwindows in one read-out cycle. The default mode is to read-out
one window with the full frame size (648 x 488).
5.3.1 SINGLE WINDOW
When a single window is read out, the start address and size can be uploaded in the corresponding registers. The
default start address is 0 and the default size is 488 (full frame).
Register name
start1
Register address
3-4
Number_lines
1-2
Windowing – single window
Default value
Description of the value
0
The value in this register defines the start address of the
window in Y (min=0, max=487)
488
The value in this register defines the number of lines read
out by the sensor (min=1, max=488)
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488
CMV300 Datasheet
Number_lines
start1
648
FIGURE 35: SINGLE WINDOW SETTINGS
5.3.2 MULTIPLE WINDOWS
The CMV300 can read out a maximum of 8 different subwindows in one read-out cycle. The location and length of
these subwindows must be programmed in the correct registers. The total number of lines to be read-out (sum of all
windows) needs to be specified in the Number_lines register. The registers which need to be programmed for the
multiple windows can be found in the table below.
Register name
Number_lines
Register address
1-2
start1
3-4
Number_lines1
19-20
start2
5-6
Number_lines2
21-22
start3
7-8
Number_lines3
23-24
start4
9-10
Number_lines4
25-26
start5
11-12
Number_lines5
27-28
start6
13-14
Windowing – multiple windows
Default value
Description of the value
488
The value in this register defines the total number of lines
read-out by the sensor (min=1, max=488)
0
The value in this register defines the start address of the
first window in Y (min=0, max=487)
0
The value in this register defines the number of lines of the
first window (min=1, max=488)
0
The value in this register defines the start address of the
second window in Y (min=0, max=487)
0
The value in this register defines the number of lines of the
second window (min=1, max=488)
0
The value in this register defines the start address of the
third window in Y (min=0, max=487)
0
The value in this register defines the number of lines of the
third window (min=1, max=488)
0
The value in this register defines the start address of the
fourth window in Y (min=0, max=487)
0
The value in this register defines the number of lines of the
fourth window (min=1, max=488)
0
The value in this register defines the start address of the
fifth window in Y (min=0, max=487)
0
The value in this register defines the number of lines of the
fifth window (min=1, max=488)
0
The value in this register defines the start address of the
sixth window in Y (min=0, max=487)
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CMV300 Datasheet
Windowing – multiple windows
Default value
Description of the value
0
The value in this register defines the number of lines of the
sixth window (min=1, max=488)
start7
15-16
0
The value in this register defines the start address of the
seventh window in Y (min=0, max=487)
Number_lines7
31-32
0
The value in this register defines the number of lines of the
seventh window (min=1, max=488)
start8
17-18
0
The value in this register defines the start address of the
eighth window in Y (min=0, max=487)
Number_lines8
33-34
0
The value in this register defines the number of lines of the
eighth window (min=1, max=488)
Note: The default values will result in one window with 488 lines to be read out
Register name
Number_lines6
Register address
29-30
Number_lines4
488
start4
Number_lines3
start3
Number_lines2
start2
Number_lines1
start1
648
Number_lines = Number_lines1 + Number_lines2 + Number_lines3 + Number_lines4
FIGURE 36: EXAMPLE OF 4 SUBWINDOWS READ-OUT
5.4 IMAGE FLIPPING
The image coming out of the image sensor, can be flipped in X and/or Y direction. This means that if flipping is enabled
in both directions the upper right pixel is read out first (instead of lower left). The following registers are involved in
image flipping
Register name
Image_flipping
Register address
40[1:0]
Image flipping
Default value
Description of the value
0
0: No image flipping
1: Image flipping in X
2: Image flipping in Y
3: Image flipping in X and Y
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CMV300 Datasheet
5.5 IMAGE SUBSAMPLING
To maintain the same field of view but reduce the amount of data coming out of the sensor, a subsampling mode is
implemented on the chip. Different subsampling schemes can be programmed by setting the appropriate registers.
These subsampling schemes can take into account whether a color or monochrome sensor is used to preserve the
Bayer pattern information. The registers involved in subsampling are detailed below. A distinction is made between a
simple and advanced mode (can be used for color devices). Subsampling can be enabled in every windowing mode.
5.5.1 SIMPLE SUBSAMPLING
Register name
Number_lines
Register address
1-2
Sub_s
Sub_a
35-36
37-38
Image subsampling - simple
Default value
Description of the value
488
The value in this register defines the total number of lines
read out by the sensor (min=1, max=488)
0
Number of rows to skip (min=0, max=487)
0
Identical to Sub_s
The figures below give two subsampling examples (skip 4x and skip 1x).
Sub_s = 4
Sub_a = 4
Number_lines = sum of red lines
Sub_s = 1
Sub_a = 1
Number_lines = sum of red lines
FIGURE 37: SUBSAMPLING EXAMPLES (SKIP 4X AND SKIP 1X)
5.5.2 ADVANCED SUBSAMPLING
When a color sensor is used, the subsampling scheme should take into account that a Bayer color filter is applied on
the sensor. This Bayer pattern should be preserved when subsampling is used. This means that the number of rows to
be skipped should always be a multiple of two. An advanced subsampling scheme can be programmed to achieve
these requirements. Of course, this advanced subsampling scheme can also be programmed in a monochrome sensor.
See the table of registers below for more details.
Register name
Number_lines
Register address
1-2
Sub_s
Sub_a
35-36
37-38
Image subsampling - advanced
Default value
Description of the value
488
The value in this register defines the total number of lines
read out by the sensor (min=1, max=488)
0
Should be ‘0’ at all times
0
Number of rows to skip, it should be an even number
between (0 and 486).
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CMV300 Datasheet
The figures below give two subsampling examples (skip 4x and skip 2x) in advanced mode.
Sub_s = 0
Sub_a = 2
Sub_s = 0
Sub_a = 4
Number_lines = sum of red lines
Number_lines = sum of red lines
FIGURE 38: SUBSAMPLING EXAMPLES IN ADVANCED MODE (SKIP 4X AND SKIP2X)
5.6 NUMBER OF FRAMES
When internal exposure mode is selected, the number of frames sent by the sensor after a frame request can be
programmed in the corresponding sequencer register.
Register name
Number_frames
Register address
55-56
Number of frames
Default value
Description of the value
1
The value in this register defines the number of frames
grabbed and sent by the image sensor in internal exposure
mode (min =1, max = 65535)
5.7 OUTPUT MODE
When LVDS output mode is selected, the number of LVDS channels can be selected by programming the appropriate
sequencer register. The pixel remapping scheme and the read-out timing for each mode can be found in section 4 of
this document.
When parallel CMOS output mode is selected, the Output_mode register should be fixed to 3. Also register 69 has to
be set at 9 and pin B2 connected to ground. The read-out timing for this mode can be found in section 4 of this
document.
Register name
Output_mode
Register address
57[1:0]
Output mode
Default value
Description of the value
0
0: 4 outputs (LVDS)
2: 2 outputs (LVDS)
3: 1 output (LVDS or parallel CMOS)
5.8 TRAINING PATTERN
As detailed in section 4.1.5, a training pattern is sent over the LVDS data channels whenever no valid image data is
sent. This training pattern can be programmed using the sequencer register.
Register name
Training_pattern
Register address
61-62[3:0]
Training pattern
Default value
85
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Description of the value
Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
5.9 8-BIT, 10-BIT OR 12-BIT MODE
The CMV300 has the possibility to send 8 bits, 10 bits or 12 bits per pixel. The end user can select the desired
resolution by programming the corresponding sequencer register.
8-bit, 10-bit or 12-bit mode
Default value
Description of the value
0
0: 12 bits per pixel
1: 10 bits per pixel
2: 8 bits per pixel
The sensor will always output words of 12 bit length. So when changing to 10 or 8 bit, the LSB’s will be filled with 0’s.
This means that changing bit mode doesn’t affect the frame rate.
Register name
Bit_mode
Register address
68[1:0]
Bit mode
8b
10b
12b
Decimal value
170
682
2730
Output word
1010 1010 0000
1010 1010 1000
1010 1010 1010
5.10 DATA RATE
During start-up or after a sequencer reset, the data rate can be changed if a lower speed than 480Mbps is desired.
This can be done by applying a lower master input clock (CLK_IN) to the sensor and uploading a new value in the
PLL_range register. See section 3.5 for more details on the input clock. See section 3.7 and 3.8 for details on how and
when the data rate can be changed.
Register name
PLL_range
Register address
83
PLL range
Default value
Description of the value
155
155: CLK_IN is between 32MHz and 50MHz
187: CLK_IN is between 20MHz and 50MHz
251: CLK_IN is between 10 and 32MHz
The internal PLL has some temperature instabilities (full details are in errata sheet CMV300-ES2). The PLL cannot lock
after startup or reset at higher temperatures (resulting in an unstable output clock)(= instability 1) and the PLL can get
out of lock for a brief moment (~40µs) when the temperature increases/decreases during operation (=instability 2).
If you want to use the internal PLL without this issues occurring, you will be confined to some settings:
-
Keep the sensor temperature lower than 55°C (instability 1 will not occur)
Keep the temperature stable during operation (instability 2 will not occur)
You can set the input clock frequency above 32MHz (PLL range 187 or 155 see below) or 24MHz (PLL range
251) for instability 1 not to occur.
Only use PLL range of 155. Both instabilities should not occur with this setting. This will increase the minimum
frequency that can be used to 32MHz.
To decrease the output frame rate (caused by increasing the clock), you can increase the number of lines being read
out (reg1-2). This will increase the number of DVAL/LVAL blocks. The data of these rows outside the sensor pixel array
will not contain useable data. In the system these extra rows can just be discarded.
Also the PLL generates a higher jitter on the outputs (5-10%) then when using the LVDS input clock.
5.11 DISABLING THE INTERNAL PLL
When you do not want to use the internal PLL of the sensor, you can disable it and input an LVDS clock yourself. The
output data speed will then be equal to this clock speed, while the output LVDS clock will be half of the LVDS input
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CMV300 Datasheet
clock (DDR). The LVDS_CLK_IN should be connected to pins D7 (LVDS_CLK_N) and D8 (LVDS_CLK_P) with a 100Ω
parallel termination resistor between the two pins. To disable the PLL set the following registers:
Register name
PLL_ENABLE
I_LVDS_REC
Register address
83 [7]
82 [3:0]
Set to value
0
8
LVDS_ENABLE
81 [6:0]
127
CLK_LVDS_EXT
84 [0]
1
REG_CLK_SEL
63 [7]
1
I_LVDS_DRIV
82 [7:4]
8
Description of the value
0/1 = PLL disabled/enabled
LVDS Receiver strength
0 = off
Enabled LVDS outputs:
Bit 0 = LVDS Input
Bit 1-4 = CH1-4 output
Bit 5 = LVDS CLK output
Bit 6 = CTR CH output
0/1 = Disabled/Enabled
Selects the CLK_IN or LVDS_CLK as input clock
0 = CLK_IN
1 = LVDS_CLK_N/P
Selects the PLL clock or the input clock
0 = PLL clock
1 = input clock
Sets the LVDS driver strength
0 = Off
1 – 15 = LVDS driver current
When you put in a LVDS_CLK_N/P clock of 430MHz, the LVDS output data rate will be 430Mbps (1 x 430MHz) with an
LVDS output clock of 215MHz (0.5 x 430MHz).
When using this mode, the maximum clock speed and therefor frame rate is lower than when using the internal PLL.
When disabling the PLL, the maximum LVDS input clock speed will be 430MHz, resulting in a frame rate of 430fps. See
Errata Sheet 2 for more detail on this speed limit.
5.12 POWER CONTROL
The power consumption of the CMV300 can be regulated by disabling the LVDS data channels when they are not used
(in 2 or 1 channel mode).
Register name
Channel_en
Register address
81[6:0]
Power control
Default value
Description of the value
126
Bit 1-2 enable/disable the bottom data output channels
Bit 3-4 enable/disable the top data output channels
Bit 5 enables/disables the output clock channel
Bit 6 enables/disables the control channel
Bit 0 enables/disables the optional LVDS clock input
channel
0: disabled
1: enabled
5.13 OFFSET AND GAIN
5.13.1 OFFSET
A digital offset can be applied to the output signal. A separate offset can be given to the data coming from the top
outputs and the data coming from the the bottom outputs. The dark level offset can be programmed by setting the
desired value in the sequencer registers. Dark-level @ output = ADC_output + Offset
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Offset
Register name
Offset_bot
Offset_top
Register address
59-60[3:0]
97-98[3:0]
Default value
0
0
Description of the value
The value in this register defines the dark level offset
applied to the output signal (min = 0, max = 4095)
The value must be seen as a two’s complement where
values higher than 2047 are used to give a negative offset.
Example:
- 000000000101 = 5 will add 5DN to the signal
- 111111111011 = -5 will subtract 5DN from the signal
Both offsets don’t have to be the same value.
5.13.2 GAIN
An analog gain and ADC gain can be applied to the output signal. The analog gain is applied by a PGA in every column.
The digital gain is applied by the ADC.
Gain
Register name
PGA_gain
Register address
80[2:0]
Default value
0
ADC_gain
100[6:0]
96
Description of the value
0: x1 gain
1: x1.25 gain
2: x1.5 gain
3: x1.75 gain
4: x2 gain
5: x2.5 gain
6: x3 gain
7: x3.5 gain
Bit[6] = 1 (enable)
Bit[5:0] = ADC gain value (range 0 to 63)
The ADC value should be adjusted per clock speed to get the same response. The ADC unity gain value for 40MHz is
48, for 25MHz it is 54. Small differences between devices can occur, so ADC_gain matching can be needed to match
responses. In the plot below you can see the actual gain per ADC gain value.
In the plot below you can also see the relative gain versus the ADC_gain setting. It is recommended for the ADC_gain
value to stay within the limits of the plots or otherwise setting the ADC_gain too high or low will result in non-linear
behavior or image artifacts to occur.
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CMV300 Datasheet
62
ADC_gain vs. Clock
Recommended ADC_gain setting
60
58
56
54
52
50
48
y = -0.4x + 64
46
5
10
15
20
25
30
35
40
45
LVDS_CLK_IN/12 or CLK_IN [MHz]
FIGURE 39: RECOMMENDED ADC_GAIN SETTING PER CLOCK SPEED
5
ADC_gain vs relative gain
4.5
40MHz
30MHz
20MHz
10MHz
4
Relative gain
3.5
3
2.5
2
1.5
1
0.5
0
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
ADC_gain setting
FIGURE 40: ADC VALUE VS ACTUAL GAIN
5.14 TEST IMAGE
The sensor can output a fixed test image, which can be used to test the functional workings of the sensor and pixel
mapping. The test image can be enabled by setting reg 67[0] to 1. The image should not contain any temporal noise as
it is fixed and injected at the end of the image readout chain, at the lvds drivers.
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
Page 40 of 55
CMV300 Datasheet
FIGURE 41: TEST IMAGE
ROW 487
487 488 489
809 810 488 489
809 810 811
ROW 486
486 487 488
808 809 487 488
808 809 810
ROW 485
485 486 487
807 808 486 487
807 808 809
ROW 2
2
3
4
324 325
3
4
324 325 326
ROW 1
1
2
3
323 324
2
3
323 324 325
ROW 0
0
1
2
322 323
1
2
322 323 324
FIGURE 42: TEST IMAGE PIXEL MAPPING
This test image is independent of the number of channels used.
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
Page 41 of 55
CMV300 Datasheet
6 REGISTER OVERVIEW
The table below gives an overview of all the sensor registers. The registers with the remark “Do not change” should
not be changed. The required values should be written to the appropriate registers for optimal sensor workings and
image performance (using the PLL at 40MHz in 10b mode).
Address
Default
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
0
232
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
232
1
0
Register overview
Value
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Remark/Required
value
Bit[1]
Bit[0]
Do not change
Number_lines[7:0]
Number lines [15:8]
Start1[7:0]
Start1[15:8]
Start2[7:0]
Start2[15:8]
Start3[7:0]
Start3[15:8]
Start4[7:0]
Start4[15:8]
Start5[7:0]
Start5[15:8]
Start6[7:0]
Start6[15:8]
Start7[7:0]
Start7[15:8]
Start8[7:0]
Start8[15:8]
Number_lines1[7:0]
Number_lines1[15:8]
Number_lines2[7:0]
Number_lines2[15:8]
Number_lines3[7:0]
Number_lines3[15:8]
Number_lines4[7:0]
Number_lines4[15:8]
Number_lines5[7:0]
Number_lines5[15:8]
Number_lines6[7:0]
Number_lines6[15:8]
Number_lines7[7:0]
Number_lines7[15:8]
Number_lines8[7:0]
Number_lines8[15:8]
Sub_s[7:0]
Sub_s[15:8]
Sub_a[7:0]
Sub_a[15:8]
Color
Image_flipping[1:0]
Exp_dual Exp_ext
Exp_time[7:0]
Exp_time[15:8]
Exp_time[23:16]
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
Page 42 of 55
CMV300 Datasheet
Address
Default
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
232
1
0
0
0
0
0
0
0
1
1
0
0
4
0
0
85
0
12
2
0
0
0
0
0
0
0
0
0
0
0
0
128
0
0
0
126
128
155
0
3
0
0
0
0
0
0
0
0
0
0
Register overview
Value
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3] Bit[2]
Exp_time2[7:0]
Exp_time2[15:8]
Exp_time2[23:16]
Exp_kp1[7:0]
Exp_kp1[15:8]
Exp_kp1[23:16]
Exp_kp2[7:0]
Exp_kp2[15:8]
Exp_kp2[23:16]
Remark/Required
value
Bit[1]
Bit[0]
Nr_slopes[1:0]
Number_frames [7:0]
Number_frames[15:8]
Output_mode[1:0]
Offset_bot[7:0]
Offset_bot[11:8]
Training_pattern[7:0]
Training pattern [11:8]
Set to 44
Set to 240
Set to 10
Do not change
Do not change
Do not change
Do not change
Do not change
Bit_mode[1:0]
Set to 9
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Temp_sensor[7:0]
Temp_sensor[15:8]
PGA_gain[2:0]
Set to 2
Channel_en[6:0]
PLL_range[7:0]
© 2016 CMOSIS bvba
Do not change
Set to 155
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Reference:CMV300-datasheet-v2.10
Page 43 of 55
CMV300 Datasheet
Address
Default
Register overview
Value
Bit[7] Bit[6] Bit[5]
Bit[4]
Bit[3] Bit[2]
Bit[1]
96
0
97
0
Offset_top[7:0]
98
0
Offset_top[11:8]
99
255
100
96
ADC_gain[6:0]
101
136
102
136
103
136
104
96
105
96
106
64
107
96
108
96
109
96
110
96
111
64
112
64
113
64
Vtfl2[6:0]
114
64
Vtfl3[6:0]
115
96
116
96
117
96
118
0
119
0
120
0
121
0
122
0
123
0
124
0
125
0
126
0
127
255
Note: The default value of the “do not change” registers should not be overwritten.
*Depends per device and clock speed.
© 2016 CMOSIS bvba
Remark/Required
value
Bit[0]
Do not change
Set to 240
Set to 10
Do not change
Set to 112*
Set to 98
Set to 34
Set to 64
Do not change
Do not change
Set to 90
Set to 110
Set to 91
Set to 82
Set to 80
Do not change
Do not change
Do not change
Do not change
Set to 91
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Do not change
Reference:CMV300-datasheet-v2.10
Page 44 of 55
CMV300 Datasheet
7 MECHANICAL SPECIFICATIONS
7.1 PACKAGE DRAWING
Top View
Bottom View
6870um ± 10um
895um ± 15um
A1
A1
994um ± 50um
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
D3
D7
D8
E1
E2
E3
E7
E8
F1
F2
F3
F4
F5
F6
F7
F8
G1
G2
G3
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
350um
B1
2800um ± 50um
402um ± 50um
Active Area: 4795 x 3611um
800um
800um
7390um ± 10um
2800um ± 50um
Optical center
635um ± 15um
H8
FIGURE 43: PACKAGE DRAWING OF THE CMV300. ALL DISTANCES IN µM
Pixel(0,0) sits in the left bottom corner of the array (top view), close to pin G8.
7.2 ASSEMBLY DRAWING
445µm
+/- 20µm
400µm
+/- 10µm
Glass lid
Spacer
540µm
+/- 45µm
Spacer
720µm
+/- 60µm
Image Sensor Die
180µm
+36µm/-30µm
Material: SAC305
FIGURE 44: ASSEMBLY DRAWING OF CMV300
7.3 COVER GLASS
The cover glass of the CMV300 is plain D263 glass with a transmittance as shown in figure 37. Refraction index of the
glass is 1.52. Scratch, bubbles and digs shall be less than or equal to 0.02 mm
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
Page 45 of 55
CMV300 Datasheet
FIGURE 45: TRANSMITTANCE OF D263 GLASS
When a color sensor is used an IR-cutoff filter should be placed in the optical path of the sensor.
7.4 COLOR FILTERS
When a color version of the CMV300 is used, the color filters are applied in a Bayer pattern. The color version of the
CMV300 always has microlenses. The typical spectral response of the CMV with color filters and D263 cover glass can
be found below. The use of an IR cut-off filter in the optical path of the CMV300 image sensor is necessary to obtain
good color separation when using light with an NIR component.
Not available yet
Figure 38: Typical spectral response of CMV300 with RGB color filters and D263 cover glass
A RGB Bayer pattern is used on the CMV300 image sensor. The order of the RGB filter can be found in the drawing
below.
FIGURE 46: RGB BAYER PATTERN ORDER
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
Page 46 of 55
CMV300 Datasheet
8 SPECTRAL RESPONSE
The typical spectral response of a monochrome and color CMV300 can be seen below.
60
CMV300 QE
50
40
Absolute QE [%]
Green1
Green2
30
Red
Blue
Mono
20
10
0
350
450
550
650
750
Wavelength [nm]
FIGURE 47: TYPICAL QUANTUM EFFICIENCY
© 2016 CMOSIS bvba
850
950
1050
Reference:CMV300-datasheet-v2.10
Page 47 of 55
CMV300 Datasheet
9 PIN LIST
A distinction is made when the sensor is used in LVDS output mode or in parallel CMOS output mode.
9.1 LVDS OUTPUT MODE PIN LIST
The pin list of the CMV300 in LVDS output mode can be found below.
Pin number
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
D3
D4
D5
D6
D7
D8
E1
E2
E3
E4
E5
E6
E7
E8
F1
F2
F3
F4
F5
F6
Pin name
Test1
GND
GND
VDDpix
GND
Output3_P
Output4_P
SPI_OUT
Test2
Enable_LVDS
VDD20
VDD33
Output3_N
Output4_N
Output_clk_P
SPI_IN
VDD33
VDDpix
R_adc2
R_adc1
Output_clk_N
Test3
SPI_EN
GND
Vref
Vramp1
Vramp2
NC
NC
NC
LVDS_CLK_N
LVDS_CLK_P
CMD_ramp
Vpch_L
Vbgap
NC
NC
NC
VDD33
GND
VDD33
VDDpix
VDD33
FRAME_REQ
Output_ctrl_N
T_EXP2
Description
No need to connect
Connect to GND
Connect to GND
Connect to 3.0V supply
Connect to GND
Image data output
Image data output
SPI output, 3.3V signaling
No need to connect
Connect to VDD33
Connect to 2.2V supply
Connect to 3.3V supply
Image data output
Image data output
LVDS clock output
SPI input, 3.3V signaling
Connect to 3.3V supply
Connect to 3.0V supply
Optional, no need to connect
Optional, no need to connect
LVDS clock output
No need to connect
SPI input, 3.3V signaling
Connect to GND
Decouple with 100nF to GND
Decouple with 100nF to GND
Decouple with 100nF to GND
Not connected
Not connected
Not connected
LVDS input clock (N), optional
LVDS input clock (P), optional
Decouple with with 100nF to VDD33
Decouple with with 100nF to GND
Decouple with with 100nF to GND
Not connected
Not connected
Not connected
Connect to 3.3V supply
Connect to GND
Connect to 3.3V supply
Connect to 3.0V supply
Connect to 3.3V supply
Digital input, 3.3V signaling
LVDS control output
Digital input, 3.3V signaling
© 2016 CMOSIS bvba
Block
Sequencer
Pixel array
LVDS
LVDS
SPI
Sequencer
Sequencer
LVDS, ADC
I/O, SPI, ADC
LVDS
LVDS
LVDS
SPI
I/O, SPI, ADC
Pixel array
ADC
ADC
LVDS
Sequencer
SPI
ADC
ADC
ADC
LVDS
LVDS
ADC
Pixel array
Pixel array
I/O, SPI, ADC
I/O, SPI, ADC
Pixel array
I/O, SPI, ADC
Sequencer
LVDS
Sequencer
Type
Test pin
GND
GND
Supply
GND
Output
Output
IO
Test pin
VDD33
Supply
Supply
output
Output
output
IO
Supply
Supply
Bias
Bias
output
Test
IO
GND
Bias
Bias
Bias
NA
NA
NA
Input
Input
Bias
Bias
Bias
NA
NA
NA
Supply
GND
Supply
Supply
Supply
IO
Output
IO
Reference:CMV300-datasheet-v2.10
Page 48 of 55
CMV300 Datasheet
Pin number
F7
F8
G1
G2
G3
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
Pin name
CLK_IN
SPI_CLK
Vtf_L
Vtf_L2
VDD20
VDD33
Output1_N
Output2_N
Output_ctrl_P
T_EXP1
Vtf_L3
GND
GND
VDDpix
GND
Output1_P
Output2_P
SYS_RES_N
Description
Master clock input (max 25MHz), 3.3V signaling
SPI input, 3.3V signaling
Decouple with with 100nF to GND
Decouple with with 100nF to GND
Connect to 2.2V supply
Connect to 3.3V supply
Image data output
Image data output
LVDS control output
Digital input, 3.3V signaling
Decouple with with 100nF to GND
Connect to GND
Connect to GND
Connect to 3.0V supply
Connect to GND
Image data output
Image data output
Digital input, 3.3V signaling
Block
Sequencer
SPI
Pixel array
Pixel array
LVDS, ADC
I/O, SPI, ADC
LVDS
LVDS
LVDS
Sequencer
Pixel array
Pixel array
LVDS
LVDS
Sequencer
Type
IO
IO
Bias
Bias
Supply
Supply
Output
Output
Output
IO
Bias
GND
GND
Supply
GND
Output
Output
IO
9.2 PARALLEL CMOS OUTPUT MODE PIN LIST
The pin list of the CMV300 in parallel CMOS output mode can be found below.
Pin number
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
D3
D4
D5
D6
D7
Pin name
Test1
GND
GND
VDDpix
GND
D4
D6
SPI_OUT
Test2
Enable_LVDS
VDD20
VDD33
D5
D7
D8
SPI_IN
VDD33
VDDpix
R_adc2
R_adc1
D9
CLK_OUT
SPI_EN
GND
Vref
Vramp1
Vramp2
NC
NC
NC
LVDS_CLK_N
Description
No need to connect
Connect to GND
Connect to GND
Connect to 3.0V supply
Connect to GND
Image data output, VDD20 signaling
Image data output, VDD20 signaling
SPI output, 3.3V signaling
No need to connect
Connect to GND
Connect to 2.2V supply
Connect to 3.3V supply
Image data output, VDD20 signaling
Image data output, VDD20 signaling
Image data output, VDD20 signaling
SPI input, 3.3V signaling
Connect to 3.3V supply
Connect to 3.0V supply
Optional, no need to connect
Optional, no need to connect
Image data output, VDD20 signaling
CMOS output, 3.3V signaling
SPI input, 3.3V signaling
Connect to GND
Decouple with 100nF to GND
Decouple with 100nF to GND
Decouple with 100nF to GND
Not connected
Not connected
Not connected
LVDS input clock (N), optional
© 2016 CMOSIS bvba
Block
Sequencer
Pixel array
CMOS Out
CMOS Out
SPI
Sequencer
Sequencer
LVDS, ADC
I/O, SPI, ADC
CMOS Out
CMOS Out
CMOS Out
SPI
I/O, SPI, ADC
Pixel array
ADC
ADC
LVDS
Sequencer
SPI
ADC
ADC
ADC
LVDS
Type
Test pin
GND
GND
Supply
GND
Output
Output
IO
Test pin
GND
Supply
Supply
Output
Output
Output
IO
Supply
Supply
Bias
Bias
Output
Output
IO
GND
Bias
Bias
Bias
NA
NA
NA
Input
Reference:CMV300-datasheet-v2.10
Page 49 of 55
CMV300 Datasheet
Pin number
D8
E1
E2
E3
E4
E5
E6
E7
E8
F1
F2
F3
F4
F5
F6
F7
F8
G1
G2
G3
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
Pin name
LVDS_CLK_P
CMD_ramp
Vpch_L
Vbgap
NC
NC
NC
VDD33
GND
VDD33
VDDpix
VDD33
FRAME_REQ
Data_valid
T_EXP2
CLK_IN
SPI_CLK
Vtf_L
Vtf_L2
VDD20
VDD33
D1
D3
Line_valid
T_EXP1
Vtf_L3
GND
GND
VDDpix
GND
D0
D2
SYS_RES_N
Description
LVDS input clock (P), optional
Decouple with with 100nF to VDD33
Decouple with with 100nF to GND
Decouple with with 100nF to GND
Not connected
Not connected
Not connected
Connect to 3.3V supply
Connect to GND
Connect to 3.3V supply
Connect to 3.0V supply
Connect to 3.3V supply
Digital input, 3.3V signaling
CMOS output, VDD20 signaling
Digital input, 3.3V signaling
Master clock input (max 25MHz), 3.3V signaling
SPI input, 3.3V signaling
Decouple with with 100nF to GND
Decouple with with 100nF to GND
Connect to 2.2V supply
Connect to 3.3V supply
Image data output, VDD20 signaling
Image data output, VDD20 signaling
CMOS output, VDD20V signaling
Digital input, 3.3V signaling
Decouple with with 100nF to GND
Connect to GND
Connect to GND
Connect to 3.0V supply
Connect to GND
Image data output, VDD20 signaling
Image data output VDD20 signaling
Digital input, 3.3V signaling
© 2016 CMOSIS bvba
Block
LVDS
ADC
Pixel array
Pixel array
I/O, SPI, ADC
I/O, SPI, ADC
Pixel array
I/O, SPI, ADC
Sequencer
CMOS Out
Sequencer
Sequencer
SPI
Pixel array
Pixel array
LVDS, ADC
I/O, SPI, ADC
LVDS
LVDS
LVDS
Sequencer
Pixel array
Pixel array
CMOS Out
CMOS Out
Sequencer
Type
Input
Bias
Bias
Bias
NA
NA
NA
Supply
GND
Supply
Supply
Supply
IO
Output
IO
IO
IO
Bias
Bias
Supply
Supply
Output
Output
Output
IO
Bias
GND
GND
Supply
GND
Output
Output
IO
Reference:CMV300-datasheet-v2.10
Page 50 of 55
CMV300 Datasheet
10 SPECIFICATION OVERVIEW
Specification
Effective pixels
Pixel pitch
Optical format
Full well charge
Conversion gain
Sensitivity
Temporal noise
(analog domain)
Dynamic range
Pixel type
Value
648 x 488
7.4 x 7.4 µm2
1/3”
20 Ke0.185LSB/e6 V/lux.s
20 e-
Shutter type
Pipelined global
shutter
<1/50 000
Parasitic light
sensitivity Shutter efficiency
Color filters
Micro lenses
QE * FF
Dark current
signal
DSNU
Fixed pattern
noise
PRNU
LVDS Output
channel
60 dB
Global shutter
pixel
>99.998%
Optional
Yes
55%
125 e/s
Pinned photodiode pixel.
12 bit mode, unity gain
With microlenses @ 550nm
Pipelined global shutter (GS) with correlated
double sampling ( CDS )
Allows fixed pattern noise correction and reset
(kTC) noise canceling through correlated
double sampling.
Exposure of next image during readout of the
previous image.
RGB Bayer pattern
@ 550 nm with micro lenses.
@ 25C die temperature
12 LSB/s
<4 LSB RMS
12 bit mode
<0.1% of full swing, 12 bit mode
< 1% RMS of
signal
4
Frame rate
480 frames/s
Timing generation
On-chip
PGA
Programmable
Registers
Yes
Sensor
parameters
Supported HDR
modes
Interleaved
integration times
ADC
Interface
Comment
Containing 4 dark reference columns and rows.
Piecewise linear
response
12bit
LVDS or CMOS
parallel
Each data output running @ 300 Mbit/s.
2 and 1 outputs selectable at reduced frame
rate.
Parallel CMOS output available
Using a 12bit/pixel and 480 Mbit/s LVDS
output. Higher frame rate possible in row
windowing mode.
Possibility to control exposure time through
external pin.
4 analog gain settings
Window coordinates, Timing parameters, Gain
& offset, Exposure time, flipped readout in x
and y direction …
Interleaved exposure times for different
columns: Odd columns (double rows for color)
have a different exposure compared to even
columns (double columns for color). Final
image is a combination of the two (through
interpolation).
Response curve with two kneepoints
Column ADC
Serial output data + synchronization signals
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
Page 51 of 55
CMV300 Datasheet
Specification
I/O logic levels
Supply voltages
Value
LVDS = 2.2V
Logic levels =
3.3V, 2.2V
2.2 & 3.3 V
Clock inputs
Power
Package
Operating range
CLK_IN
700 mW
CSP
-30C to +70C
Cover glass
ESD
D263
HBM Class 1C
Comment
3.3V for the pixel array and analog circuits
2.2V for digital circuits and the LVDS drivers
Between 10 and 40MHz
At 40MHz
Chip scale package (8 x 8 BGA pins)
Dark current and noise performance will
degrade at higher temperature
Plain glass, no IR cut-off filter on color devices
JS-001-2012
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
Page 52 of 55
CMV300 Datasheet
11 ORDERING INFO
Part Number
Chroma
Microlens
Package
Glass
Max
speed
CMV300-4E7M1WP
CMV300-4E7C1WP
Mono
RGB Bayer
yes
yes
Chip scale package BGA
Chip scale package BGA
plain
plain
40MHz
40MHz
On request the package and cover glass can be customized. For options, pricing and delivery time please contact
[email protected].
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
12 HANDLING AND SOLDERING PROCEDURE
A separate general application note (AN3) is available on handling and soldering image sensors.
12.1 SOLDERING
The CMV300 has a J-STD-020 MSL5 level. It is advised to bake the sensors prior to soldering. The bake condition would
be 12h at +125°C. Afterwards, the sensors need to be soldered within the next 48hours (stored at <30°C and <60%
RH).
12.1.1 REFLOW SOLDERING
The profile is based on standard J-STD-020. The figure below shows the maximum recommended thermal profile for a
reflow soldering system. If the temperature/time profile exceeds these recommendations, damage to the image
sensor can occur.
FIGURE 48: REFLOW SOLDER PROFILE
12.1.2 SOLDERING RECOMMENDATIONS
Image sensors with color filter arrays (CFA) and micro-lenses are especially sensitive to high temperatures. Prolonged
heating at elevated temperatures may result in deterioration of the performance of the sensor. Best solution will be
flow soldering or manual soldering of a socket (through hole or BGA) and plug in the sensor at latest stage of the
assembly/test process. (Partial) Re-Reflow of BGA Solder Joints in during a secondary solder operation (soldering
through-hole components) must be avoided. This could result in open BGA solder joints.
12.2 HANDLING IMAGE SENSORS
12.2.1 ESD
The CMV300 has a HBM Class 1C ESD level. The following are the recommended minimum ESD requirements when
handling image sensors.
1. Ground workspace (tables, floors…)
2. Ground handling personnel (wrist straps, special footwear…)
3. Minimize static charging (control humidity, use ionized air, wear gloves…)
12.2.2 GLASS CLEANING
When cleaning of the cover glass is needed we recommend the following two methods.
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
1.
2.
Blowing off the particles with ionized nitrogen
Wipe clean using IPA (isopropyl alcohol) and ESD protective wipes.
12.2.3 IMAGE SENSOR STORING
Image sensors should be stored under the following conditions
1.
2.
3.
4.
Dust free
Temperature 20°C to 40°C
Humidity between 30% and 60%.
Avoid radiation, electromagnetic fields, ESD, mechanical stress
12.2.4 EXCESSIVE LIGHT
Excessive light falling on the sensor can cause heating up the micro lenses and color filters. This heat can cause
deforming of the lenses and/or deterioration of the lenses and color filters by making them more opaque, increasing
the heat up even more. Avoid shining high intensity light upon the sensors for extended periods of time. In case of
lasers, they can cause heat up but can also damage the silicon die itself.
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Reference:CMV300-datasheet-v2.10
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CMV300 Datasheet
13 ADDITIONAL INFORMATION
For any additional questions related to the operation and specification of the CMV300 imagers or feedback with
respect to the present data sheet please contact [email protected].
© 2016 CMOSIS bvba