ATMEL ATF22V10CQZ-20PI Highperformance ee pld Datasheet

Features
•
•
•
•
•
•
•
•
•
•
•
Industry-standard Architecture
12 ns Maximum Pin-to-pin Delay
Zero Power – 25 µA Maximum Standby Power (Input Transition Detection)
CMOS and TTL Compatible Inputs and Outputs
Advanced Electrically-erasableTechnology
– Reprogrammable
– 100% Tested
Latch Feature Holds Inputs to Previous Logic State
High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-line and Surface Mount Standard Pinouts
PCI Compliant
Green Package Options (Pb/Halide-free/RoHS Compliant) Available
Highperformance
EE PLD
ATF22V10CZ
ATF22V10CQZ
1. Desscription
The ATF22V10CZ/CQZ is a high-performance CMOS (electrically-erasable)
programmable logic device (PLD) which utilizes Atmel’s proven electrically-erasable
Flash memory technology. Speeds down to 12 ns with zero standby power dissipation
are offered. All speed ranges are specified over the full 5V ±10% range for industrial
tem per ature r ang es; 5V ±5% fo r com mer cia l ra nge 5 -volt devices. The
ATF22V10CZ/CQZ provides a low voltage and edge-sensing “zero” power CMOS
PLD solution with “zero” standby power (5 µA typical). The ATF22V10CZ/CQZ provides a “zero” power CMOS PLD solution with 5V operating voltages, powering down
automatically to the zero power-mode through Atmel’s patented Input Transition
Detection (ITD) circuitry when the device is idle, offering “zero” (25 µA worst case)
standby power. This feature allows the user to manage total system power to meet
specific application requirements and enhance reliability. Pin “keeper” circuits on input
and output pins eliminate static power consumed by pull-up resistors. The “CQZ” combines the low high-frequency ICC of the “Q” design with the “Z” feature.
The ATF22V10CZ/CQZ incorporates a superset of the generic architectures, which
allows direct replacement of the 22V10 family and most 24-pin combinatorial PLDs.
Ten outputs are each allocated 8 to 16 product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be
realized.
0778J–PLD–11/07
Figure 1-1.
Block Diagram
2. Pin Configurations
Table 2-1.
Pin Configurations (All Pinouts Top View)
Pin Name
Function
CLK
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
VCC
+5V Supply
Figure 2-1.
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
Figure 2-2.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
DIP/SOIC
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
PLCC
25
24
23
22
21
20
19
12
13
14
15
16
17
18
5
6
7
8
9
10
11
I/O
I/O
I/O
GND*
I/O
I/O
I/O
IN
IN
GND
GND*
IN
I/O
I/O
IN
IN
IN
GND*
IN
IN
IN
4
3
2
1
28
27
26
IN
IN
CLK/IN
VCC*
VCC
I/O
I/O
Figure 2-3.
TSSOP
Note:
2
For PLCC, P1, P8, P15 and P22 can be
left unconnected. For superior performance, connect VCC to pin 1 and GND
to 8, 15, and 22.
ATF22V10C(Q)Z
0778J–PLD–11/07
ATF22V10C(Q)Z
3. Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
4. DC and AC Operating Conditions
Operating Temperature (Ambient)
VCC Power Supply
Commercial
Industrial
0°C - 70°C
-40°C - 85°C
5V ± 5%
5V ± 10%
3
0778J–PLD–11/07
4.1
DC Characteristics
Symbol
Parameter
IIL
Input or I/O Low
Leakage Current
IIH
Input or I/O High
Leakage Current
ICC
ISB
Clocked Power
Supply Current
Power Supply Current,
Standby
Condition
Min
Typ
0 ≤ VIN ≤ VIL (Max)
3.5 ≤ VIN ≤ VCC
VCC = Max
Outputs Open,
f = 15 MHz
VCC = Max
VIN = MAX
Outputs Open
Max
Units
-10
µA
10
µA
CZ-12, 15
Com
90
150
mA
CZ-15
Ind
90
180
mA
CQZ-20
Com
40
60
mA
CQZ-20
Ind
40
80
mA
CZ-12, 15
Com
5
25
µA
CZ-15
Ind
5
50
µA
CQZ-20
Com
5
25
µA
CQZ-20
Ind
5
50
µA
-130
mA
IOS(1)
Output Short Circuit
Current
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.75
V
VOL
Output Low Voltage
VIN = VIH or VIL
VCC = Min,
IOL = 16 mA
0.5
V
VOH
Output High Voltage
VIN = VIH or VIL
VCCIO = Min,
IOH = -4.0 mA
Note:
4
VOUT = 0.5V
2.4
V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
ATF22V10C(Q)Z
0778J–PLD–11/07
ATF22V10C(Q)Z
4.2
AC Waveforms
INPUTS, I/O
REG. FEEDBACK
SYNCH. PRESET
tS
tH
tW
tW
CP
tP
tAW
tAR
ASYNCH. RESET
tCO
tAP
REGISTERED
OUTPUTS
tER
VALID
4.3
OUTPUT
DISABLED
VALID
tPD
COMBINATORIAL
OUTPUTS
tEA
tER
VALID
VALID
tEA
OUTPUT
DISABLED
VALID
VALID
AC Characteristics(1)
-12
-15
-20
Symbol
Parameter
tPD
Input or Feedback to Non-registered Output
tCF
Clock to Feedback
tCO
Clock to Output
2
tS
Input or Feedback Setup Time
10
10
14
ns
tH
Input Hold Time
0
0
0
ns
tW
Clock Width
6
6
10
ns
fMAX
External Feedback 1/(tS + tCO)
Internal Feedback 1/(tS + tCF)
No Feedback 1/(tP)
55.5
69
83.3
38.5
45.5
50.0
MHz
MHz
MHz
tEA
Input to Output Enable - Product Term
3
12
3
15
3
20
ns
tER
Input to Output Disable - Product Term
2
15
3
15
3
20
ns
tPZX
OE Pin to Output Enable
2
12
2
15
2
20
ns
tPXZ
OE Pin to Output Disable
2
15
2
15
2
20
ns
tAP
Input or I/O to Asynchronous Reset of
Register
3
10
3
15
3
22
ns
tSP
Setup Time, Synchronous Preset
10
10
14
ns
tAW
Asynchronous Reset Width
7
8
20
ns
tAR
Asynchronous Reset Recovery Time
5
6
20
ns
tSPR
Synchronous Preset to Clock Recovery
Time
10
10
14
ns
Note:
Min
Max
Min
Max
Min
Max
Units
3
12
3
15
3
20
ns
8
ns
12
ns
6
8
4.5
2
55.5
62
83.3
8
2
1. See ordering information for valid part numbers.
5
0778J–PLD–11/07
4.4
Input Test Waveforms
4.4.1
Input Test Waveforms and Measurement Levels
4.4.2
Output Test Loads
Note:
4.5
Similar competitors devices are specified with slightly different loads. These load differences may
affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet
compatible device specification conditions.
Pin Capacitance
Table 4-1.
Typ
Max
Units
Conditions
CIN
8
10
pF
VIN = 0V; f = 1.0 MHz
CI/O
8
10
pF
VOUT = 0V; f = 1.0 MHz
Note:
4.6
Pin Capacitance (f = 1 MHz, T = 25C(1))
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%
tested.
Power-up Reset
The registers in the ATF22V10CZ/CQZ are designed to reset during power-up. At a point
delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output
state will depend on the polarity of the buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how VCC actually rises in the system, the following conditions are
required:
1. The VCC rise must be monotonic and start below 0.7V.
2. The clock must remain stable during TPR.
3. After TPR occurs, all input and feedback setup times must be met before driving the
clock pin high.
4.7
Preload of Register Outputs
The ATF22V10CZ/CQZ’s registers are provided with circuitry to allow loading of each register
with either a high or a low. This feature will simplify testing since any state can be forced into the
registers to control test sequencing. A JEDEC file with preload is generated when a source file
6
ATF22V10C(Q)Z
0778J–PLD–11/07
ATF22V10C(Q)Z
with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming.
5. Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the
device is secured. These bits can be used for user-specific data.
6. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22V10CZ/CQZ fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User
Signature remains accessible. The security fuse should be programmed last, as its effect is
immediate.
7. Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/programming.
Figure 7-1.
Programming/Erasing Timing
VRST
POWER
t PR
REGISTERED
OUTPUTS
tS
tW
CLOCK
Table 7-1.
Programming/Erasing
Parameter
Description
Typ
Max
Units
TPR
Power-up
Reset Time
600
1000
ns
VRST
Power-up
Reset Voltage
3.8
4.5
V
8. Input and I/O Pull-ups
All ATF22V10CZ/CQZ family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or I/Os are not being driven externally, they will maintain their last driven
state. This ensures that all logic array inputs and device outputs are at known states. These are
relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input
and I/O diagrams below).
7
0778J–PLD–11/07
Figure 8-1.
Input Diagram
VCC
100K
INPUT
ESD
PROTECTION
CIRCUIT
Figure 8-2.
I/O Diagram
VCC
OE
DATA
I/O
VCC
INPUT
100K
9. Compiler Mode Selection
Table 9-1.
Synario
WINCUPL
8
Compiler Mode Selection
PAL Mode
(5828 Fuses)
GAL Mode
(5892 Fuses)
ATF22V10C (DIP)
ATF22V10C (PLCC)
ATF22V10C DIP (UES)
ATF22V10C PLCC (UES)
P22V10
P22V10LCC
G22V10
G22V10LCC
ATF22V10C(Q)Z
0778J–PLD–11/07
ATF22V10C(Q)Z
10. Functional Logic Diagram Description
The Functional Logic Diagram describes the ATF22V10CZ/CQZ architecture.
The ATF22V10CZ/CQZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured
into one of four output configurations: active high/low, registered/combinatorial output.The universal architecture of the ATF22V10CZ/CQZ can be programmed to emulate most 24-pin PAL
devices.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF22V10CZ/CQZ. Eight
bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Signature is accessible regardless of the
state of the security fuse.
9
0778J–PLD–11/07
Figure 10-1. Functional Logic Diagram
10
ATF22V10C(Q)Z
0778J–PLD–11/07
ATF22V10C(Q)Z
NORMALIZED ICC VS. TEMP
ATF22V10CZ/CQZ STAND-BY ICC vs.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
NORMALIZED ICC
I CC (µA)
1.4
SUPPLY VOLTAGE (TA = 25°C)
1.0
0.8
0.6
4.5
4.8
5.0
5.3
0.4
-40.0
5.5
0.0
SUPPLY VOLTAGE (V)
ATF22V10CZ SUPPLY CURRENT vs. INPUT
FREQUENCY (VCC = 5.0V, TA = 25°C)
50.000
120.000
40.000
100.000
30.000
I CC (mA)
140.000
ICC (mA)
25.0
75.0
TEMPERATURE (C)
80.000
ATF22V10CQZ SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5V, TA = 25°C)
20.000
60.000
10.000
40.000
0.000
0.0
0.5
2.5
5.0
20.000
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.000
0.0
0.5
2.5
5.0
7.5
10.0
FREQUENCY (MHz)
25.0
37.5
50.0
ATF22V10CZ/CQZ OUTPUT SOURCE CURRENT VS
SUPPLY VOLTAGE (VOH = 2.4V)
ATF22V10CZ/CQZ OUTPUT SOURCE CURRENT
VS.
OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
0
0.0
-10.0
-20.0
-30.0
-40.0
-20
-30
IOH (mA)
I OH (mA)
-10
-40
-50
4.0
4.5
5.0
5.5
6.0
-50.0
-60.0
-70.0
-80.0
-90.0
SUPPLY VOLTAGE (V)
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
VOH (V)
48
ATF22V10CZ/CQZ OUTPUT SINK CURRENT vs.
SUPPLY VOLTAGE (V OL = 0.5V)
ATF22V10CZ/CQZ OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
140.0
120.0
44
100.0
42
I OL (mA)
I OL (mA)
46
40
38
80.0
60.0
40.0
36
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
6.0
20.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
11
0778J–PLD–11/07
0
-40
-60
-80
-100
-120
0.0
-0.2
-0.4
-0.6
INPUT VOLTAGE (V)
ATF22V10CZ/CQZ INPUT CURRENT VS
INPUT VOLTAGE (V CC = 5V, TA = 25°C)
40
-20
-0.8
-1.0
INPUT CURRENT (uA)
INPUT CURRENT (mA)
ATF22V10CZ/CQZ INPUT CLAMP CURRENT VS
INPUT VOLTAGE (V CC = 5V, TA = 35°C)
30
20
10
0
-10
-20
-30
0.0
NORMALIZED TPD vs. VCC
NORMALIZED TPD
NORMALIZED TPD
1.1
1.0
0.9
4.5
5.0
SUPPLY VOLTAGE (V)
5.3
6.0
1.0
0.9
0.8
-40.0
5.5
NORMALIZED TCO vs. VCC
0.0
25.0
TEMPERATURE (C)
75.0
NORMALIZED TCO VS TEMP
1.1
NORMALIZED TCO
NORMALIZED TCO
4.8
1.2
1.1
1.0
0.9
4.5
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
1.0
0.9
0.8
-40.0
0.8
5.5
0.0
25.0
75.0
TEMPERATURE (V)
NORMALIZED TSU VS VCC
NORMALIZED TSU vs. TEMP
1.2
1.2
NORMALIZED TSU
NORMALIZED TSU
5.0
1.1
0.8
1.1
1.0
0.9
0.8
4.5
12
2.0
3.0
4.0
INPUT VOLTAGE (V)
NORMALIZED TPD vs. TEMP
1.2
1.3
1.0
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
5.5
1.1
1.0
0.9
0.8
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
ATF22V10C(Q)Z
0778J–PLD–11/07
ATF22V10C(Q)Z
ATF22V10C DELTA TPD vs.
OUTPUT LOADING
8
ATF22V10C DELTA TCO VS.
OUTPUT LOADING
8.00
DELTA TCO (ns)
DELTA TPD (ns)
7.00
6
4
2
0
-2
6.00
5.00
4.00
3.00
2.00
1.00
0.00
0
50
100
150
200
250
300
50
100
OUTPUT LOADING (PF)
DELTA TPD vs. # OF OUTPUT SWITCHING
200
250
300
DELTA TCO vs. # OF OUTPUT SWITCHING
0.0
0.0
-0.1
-0.1
DELTA TCO (ns)
DELTA TPD (ns)
150
NUMBER OF OUTPUTS LOADING
-0.2
-0.3
-0.4
-0.1
-0.2
-0.2
-0.3
-0.5
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
NUMBER OF OUTPUTS SWITCHING
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
13
0778J–PLD–11/07
11. Ordering Information
11.1
tPD
(ns)
12
15
20
11.2
tPD
(ns)
20
11.3
Standard Package Options
tS
(ns)
10
4.5
14
tCO
(ns)
8
8
12
Ordering Code
Package
Operation Range
ATF22V10CZ-12JC
ATF22V10CZ-12PC
ATF22V10CZ-12SC
ATF22V10CZ-12XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF22V10CZ-15JC
ATF22V10CZ-15PC
ATF22V10CZ-15SC
ATF22V10CZ-15XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF22V10CZ-15JI
ATF22V10CZ-15PI
ATF22V10CZ-15SI
ATF22V10CZ-15XI
28J
24P3
24S
24X
Industrial
(-40°C to +85°C)
ATF22V10CQZ-20JC
ATF22V10CQZ-20PC
ATF22V10CQZ-20SC
ATF22V10CQZ-20XC
28J
24P3
24S
24X
ATF22V10CQZ-20JI
ATF22V10CQZ-20PI
ATF22V10CQZ-20SI
ATF22V10CQZ-20XI
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
Industrial
(-40°C to +85°C)
ATF22V10CQZ Green Package Options (Pb/Halide-free/RoHS Compliant)
tS
(ns)
14
tCO
(ns)
12
Ordering Code
Package
Operation Range
ATF22V10CQZ-20JU
ATF22V10CQZ-20PU
ATF22V10CQZ-20SU
ATF22V10CQZ-20XU
28J
24P3
24S
24X
Industrial
(-40°C to +85°C)
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade
from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3
24-pin, 0.300", Plastic Dual Inline Package (PDIP)
24S
24-lead, 0.300" Wide, Plastic Gull-Wing Small Outline (SOIC)
24X
24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
14
ATF22V10C(Q)Z
0778J–PLD–11/07
ATF22V10C(Q)Z
12. Packaging Information
12.1
28J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
12.319
–
12.573
D1
11.430
–
11.582
E
12.319
–
12.573
E1
11.430
–
11.582
D2/E2
9.906
–
10.922
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
28J
B
15
0778J–PLD–11/07
12.2
24P3 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
eC
eB
Notes:
1.
2.
This package conforms to JEDEC reference MS-001, Variation AF.
Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
SYMBOL
MIN
NOM
MAX
A
–
–
5.334
A1
0.381
–
–
D
31.623
–
32.131
E
7.620
–
8.255
E1
6.096
–
7.112
B
0.356
–
0.559
B1
1.270
–
1.651
L
2.921
–
3.810
C
0.203
–
0.356
eB
–
–
10.922
eC
0.000
–
1.524
e
NOTE
Note 2
Note 2
2.540 TYP
6/1/04
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
24P3
REV.
D
ATF22V10C(Q)Z
0778J–PLD–11/07
ATF22V10C(Q)Z
12.3
24S – SOIC
B
D1
D
PIN 1 ID
PIN 1
e
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
0º ~ 8º
L1
L
SYMBOL
MIN
NOM
MAX
A
–
–
2.65
A1
0.10
–
0.30
D
10.00
–
10.65
D1
7.40
–
7.60
E
15.20
–
15.60
B
0.33
–
0.51
L
0.40
–
1.27
L1
0.23
–
0.32
e
NOTE
1.27 BSC
06/17/2002
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC)
DRAWING NO.
REV.
24S
B
17
0778J–PLD–11/07
12.4
24X – TSSOP
Dimensions in Millimeter and (Inches)*
JEDEC STANDARD MO-153 AD
Controlling dimension: millimeters
0.30(0.012)
0.19(0.007)
4.48(0.176)
6.50(0.256)
4.30(0.169)
6.25(0.246)
PIN 1
0.65(0.0256)BSC
7.90(0.311)
1.20(0.047)MAX
7.70(0.303)
0.15(0.006)
0.05(0.002)
0.20(0.008)
0º ~ 8º
0.09(0.004)
0.75(0.030)
0.45(0.018)
04/11/2001
R
18
2325 Orchard Parkway
San Jose, CA 95131
TITLE
24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline
Package (TSSOP)
DRAWING NO.
REV.
24X
A
ATF22V10C(Q)Z
0778J–PLD–11/07
ATF22V10C(Q)Z
13. Revision History
Version No./Release Date
Revision I – November 2005
History
1. Added Green Package options
19
0778J–PLD–11/07
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0778J–PLD–11/07