CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • Single 3.3V power supply • 3.3V/2.5V I/O power supply • Fast clock-to-output time — 3.0 ns (for 250-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • CY7C1470V33, CY7C1472V33 available in JEDEC-standard lead-free 100-pin TQFP, lead-free and non-lead-free 165-ball FBGA package. CY7C1474V33 available in lead-free and non-lead-free 209 ball FBGA package • IEEE 1149.1 JTAG Boundary Scan compatible The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa–BWh for CY7C1474V33, BWa–BWd for CY7C1470V33 and BWa–BWb for CY7C1472V33) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option Logic Block Diagram-CY7C1470V33 (2M x 36) ADDRESS REGISTER 0 A0, A1, A A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 S E N S E ADV/LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWa BWb BWc BWd WRITE DRIVERS MEMORY ARRAY A M P S WE O U T P U T R E G I S T E R S E INPUT REGISTER 1 OE CE1 CE2 CE3 S T E E R I N G INPUT REGISTER 0 B U F F E R S DQs DQPa DQPb DQPc DQPd E E READ LOGIC SLEEP CONTROL ZZ Cypress Semiconductor Corporation Document #: 38-05289 Rev. *I E O U T P U T D A T A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 20, 2006 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Logic Block Diagram-CY7C1472V33 (4M x 18) ADDRESS REGISTER 0 A0, A1, A A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWa WRITE DRIVERS O U T P U T S E N S E MEMORY ARRAY R E G I S T E R S A M P S BWb WE O U T P U T D A T A B U F F E R S S T E E R I N G E E INPUT REGISTER 1 E OE CE1 CE2 CE3 DQs DQPa DQPb INPUT REGISTER 0 E READ LOGIC Sleep Control ZZ Logic Block Diagram-CY7C1474V33 (1M x 72) ADDRESS REGISTER 0 A0, A1, A A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD BWa BWb BWc BWd BWe BWf BWg BWh WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G E O U T P U T B U F F E R S E DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh WE INPUT REGISTER 1 E OE CE1 CE2 CE3 ZZ INPUT REGISTER 0 E READ LOGIC Sleep Control Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Document #: 38-05289 Rev. *I 250 MHz 3.0 500 120 200 MHz 3.0 500 120 167 MHz 3.4 450 120 Unit ns mA mA Page 2 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPb DQb DQb VDDQ VSS NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ CY7C1472V33 (4M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05289 Rev. *I A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A A A A A A A A A VSS VDD NC(288) NC(144) A A A A A A A A A VSS VDD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQb DQb DQb DQb VSS VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb NC DQa VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 CY7C1470V33 (2M x 36) NC(288) NC(144) DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS DQc DQc DQc DQc VSS VDDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 DQPc DQc DQc VDDQ A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A 100-pin TQFP Packages Page 3 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470V33 (2M x 36) 1 2 A B C D E F G H J K L M N P NC/576M A 3 NC/1G A DQPc DQc NC DQc VDDQ DQc R 4 5 6 7 8 9 10 11 A A NC BWc BWb CE3 BWa VSS CLK OE A A NC VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ BWd VSS VDD CEN WE ADV/LD VDDQ NC DQb DQPb DQb DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb CE1 CE2 DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc NC DQd DQc NC DQd VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQb NC DQa DQb ZZ DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQPd DQd NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC DQa DQPa NC/144M A A A TDI A1 TDO A A A MODE A A A TMS A0 TCK A A A A NC/288M CY7C1472V33 (4M x 18) A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 NC/576M A BWb NC NC CE3 CLK CEN ADV/LD A A A WE VSS VSS OE VSS VDD A A NC VSS VSS VDDQ VDDQ NC NC DQPa DQa VDDQ NC DQa NC/1G A CE1 CE2 NC NC NC DQb VDDQ VDDQ VSS VDD BWa VSS VSS NC DQb VDDQ VDD VSS VSS VSS VDD NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC NC DQb DQb NC NC VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQa DQa ZZ NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb DQPb NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC NC NC NC/144M A A A TDI A1 TDO A A A MODE A A A TMS A0 TCK A A A Document #: 38-05289 Rev. *I NC/288M A Page 4 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1474V33 (1M x 72) 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CE2 A ADV/LD A CE3 A DQb DQb B DQg DQg BWSc BWSg NC WE A BWSb BWSf DQb DQb C DQg DQg BWSh BWSd NC/576M CE1 NC BWSe BWSa DQb DQb D DQg DQg VSS NC NC/1G OE NC NC VSS DQb DQb E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf K NC NC CLK NC VSS CEN VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe T DQd DQd VSS NC NC MODE NC NC VSS DQe DQe U DQd DQd NC/144M A A A A A NC/288M DQe DQe V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe Document #: 38-05289 Rev. *I Page 5 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Definitions I/O Type Pin Description A0 A1 A Pin Name InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. BWa BWb BWc BWd BWe BWf BWg BWh InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQS I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX I/OSynchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQX. During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh. MODE TDO TDI Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. JTAG Serial Output Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. JTAG Serial Input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. Synchronous Document #: 38-05289 Rev. *I Page 6 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Definitions (continued) Pin Name TMS I/O Type Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous TCK JTAG Clock VDD Power Supply VDDQ Pin Description Clock input to the JTAG circuitry. Power supply inputs to the core of the device. I/O Power Supply Power supply for the I/O circuitry. VSS Ground NC – No connects. This pin is not connected to the die. NC(144M, 288M, 576M, 1G) – These pins are not connected. They will be used for expansion to the 144M, 288M, 576M, and 1G densities. InputAsynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. ZZ Ground for the device. Should be connected to ground of the system. Functional Overview The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.0 ns (250-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). BW[x] can be used to conduct Byte Write operations. Write operations are qualified by the Write Enable (WE). All Writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.0 ns Document #: 38-05289 Rev. *I (250-MHz device) provided OE is active LOW. After the first clock of the Read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise. Burst Read Accesses The CY7C1470V33, CY7C1472V33, and CY7C1474V33 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V33, DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for CY7C1472V33). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). Page 7 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 On the next clock rise the data presented to DQ and DQP for CY7C1474V33, (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 & DQa,b/DQPa,b for CY7C1472V33) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BW (BWa,b,c,d,e,f,g,h for CY7C1474V33, BWa,b,c,d for CY7C1470V33 and BWa,b for CY7C1472V33) signals. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 provides Byte Write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1470V33, CY7C1472V33, and CY7C1474V33 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V33, DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for CY7C1472V33) inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ and DQP for CY7C1474V33, (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 and DQa,b/DQPa,b for CY7C1472V33) are automatically tri-stated during the data portion of a Write cycle, regardless of the state of OE. CY7C1474V33, BWa,b,c,d for CY7C1470V33 and BWa,b for CY7C1472V33) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address Second Address Third Address Fourth Address A1,A0 A1,A0 A1,A0 A1,A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) Burst Write Accesses The CY7C1470V33, CY7C1472V33, and CY7C1474V33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for First Address Second Address Third Address Fourth Address A1,A0 A1,A0 A1,A0 A1,A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max Unit IDDZZ Sleep mode standby current ZZ > VDD − 0.2V 120 mA tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to sleep current This parameter is sampled tRZZI ZZ Inactive to exit sleep current This parameter is sampled Document #: 38-05289 Rev. *I 2tCYC ns 2tCYC 0 ns ns Page 8 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Truth Table[1, 2, 3, 4, 5, 6, 7] Operation Address Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ Deselect Cycle None H L L X X X L L-H Tri-State Continue Deselect Cycle None X L H X X X L L-H Tri-State Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D) Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D) NOP/Write Abort (Begin Burst) None L L L L H X L L-H Tri-State Write Abort (Continue Burst) Next X L H X H X L L-H Tri-State Ignore Clock Edge (Stall) Current X L X X X X H L-H - Sleep Mode None X H X X X X X X Tri-State Notes: 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details. 3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs and DQP[a:d] = tri-state when OE is inactive or when the device is deselected, and DQs= data when OE is active. Document #: 38-05289 Rev. *I Page 9 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Partial Write Cycle Description[1, 2, 3, 8] Function (CY7C1470V33) WE BWd BWc BWb BWa Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQa and DQPa) L H H H L Write Byte b – (DQb and DQPb) L H H L H Write Bytes b, a L H H L L Write Byte c – (DQc and DQPc) L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H L L H Write Bytes c, b, a L H L L L Write Byte d – (DQd and DQPd) L L H H H Write Bytes d, a L L H H L Write Bytes d, b L L H L H Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L L Function (CY7C1472V33) WE BWb BWa Read H x x Write – No Bytes Written L H H Write Byte a – (DQa and DQPa) L H L Write Byte b – (DQb and DQPb) L L H Write Both Bytes L L L Function (CY7C1474V33) WE BWx Read H x Write – No Bytes Written L H Write Byte X − (DQx and DQPx) L L Write All Bytes L All BW = L Note: 8. Table only lists a partial listing of the Byte Write combinations. Any combination of BW[a:d] is valid. Appropriate Write will be done based on which Byte Write is active. Document #: 38-05289 Rev. *I Page 10 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 IEEE 1149.1 Serial Boundary Scan (JTAG) Test MODE SELECT (TMS) The CY7C1470V33, CY7C1472V33, and CY7C1474V33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The CY7C1470V33, CY7C1472V33, and CY7C1474V33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Disabling the JTAG Feature Test Data-Out (TDO) It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) TAP Controller Block Diagram 0 TAP Controller State Diagram 1 Bypass Register TEST-LOGIC RESET 2 1 0 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 Selection Circuitry TDO Identification Register CAPTURE-IR x . . . . . 2 1 0 Boundary Scan Register SHIFT-IR 1 Instruction Register 31 30 29 . . . 2 1 0 0 SHIFT-DR 0 1 EXIT1-DR 1 EXIT1-IR 0 1 TCK 0 PAUSE-DR 0 TMS PAUSE-IR 1 TAP CONTROLLER 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 TDI 0 1 0 0 1 Selection Circuitry 0 UPDATE-IR 1 0 Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Document #: 38-05289 Rev. *I TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Page 11 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. Boundary Scan Register IDCODE The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Document #: 38-05289 Rev. *I The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still Page 12 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 BYPASS possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 2 Test Clock (TCK) 3 t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[9, 10] Parameter Description Min. Max Unit Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns 50 ns 20 MHz Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 10 ns 0 ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise 5 ns tTDIS TDI Set-up to TCK Clock Rise 5 ns tCS Capture Set-up to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Hold Times Notes: 9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document #: 38-05289 Rev. *I Page 13 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.5V Input timing reference levels......................................... 1.25V Output reference levels...................................................1.5V Output reference levels ................................................ 1.25V Test load termination supply voltage...............................1.5V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.25V 1.5V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = –4.0 mA,VDDQ = 3.3V 2.4 V IOH = –1.0 mA,VDDQ = 2.5V VOH2 Output HIGH Voltage IOH = –100 µA VOL1 Output LOW Voltage VOL2 Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IX Input Load Current 2.0 V VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 V IOL = 8.0 mA VDDQ = 3.3V 0.4 V IOL = 1.0 mA VDDQ = 2.5V 0.4 V IOL = 100 µA VDDQ = 3.3V 0.2 V VDDQ = 2.5V 0.2 V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA VDDQ = 3.3V GND < VIN < VDDQ Note: 11. All voltages referenced to VSS (GND). Document #: 38-05289 Rev. *I Page 14 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Identification Register Definitions Instruction Field CY7C1470V33 (2M x 36) CY7C1472V33 (4M x 18) CY7C1474V33 (1M x 72) Description Revision Number (31:29) 000 000 000 Device Depth (28:24)[12] 01011 01011 01011 001000 001000 001000 Defines memory type and architecture Defines width and density Architecture/Memory Type(23:18) Bus Width/Density(17:12) 100100 010100 110100 Cypress JEDEC ID Code (11:1) 00000110100 00000110100 00000110100 1 1 1 ID Register Presence Indicator (0) Describes the version number Reserved for internal use Allows unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Instruction Bit Size (x36) Bit Size (x18) Bit Size (x72) 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order - 165 FBGA 71 52 - Boundary Scan Order - 209 FBGA - - 110 Identification Codes Code Description EXTEST Instruction 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. Note: 12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device. Document #: 38-05289 Rev. *I Page 15 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1 C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4 D2 24 P6 44 H11 64 B5 5 E2 25 R6 45 G11 65 A5 6 F1 26 R8 46 F11 66 A4 7 G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9 G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 165-Ball ID Bit # 165-Ball ID Boundary Scan Exit Order (4M x 18) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 1 D2 14 R4 27 L10 40 B10 2 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 42 B8 4 G2 17 R8 30 H11 43 A7 5 J1 18 P3 31 G11 44 B7 6 K1 19 P4 32 F11 45 B6 7 L1 20 P8 33 E11 46 A6 8 M1 21 P9 34 D11 47 B5 9 N1 22 P10 35 C11 48 A4 10 R1 23 R9 36 A11 49 B3 11 R2 24 R10 37 A9 50 A3 12 R3 25 R11 38 B9 51 A2 13 P2 26 M10 39 A10 52 B2 Document #: 38-05289 Rev. *I Page 16 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 U10 85 B11 2 A2 30 T2 58 T11 86 B10 3 B1 31 U1 59 T10 87 A11 4 B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 A7 6 C2 34 V2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4 16 H2 44 V5 72 J10 100 B3 17 J1 45 U5 73 H11 101 C3 18 J2 46 U6 74 H10 102 C4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 C9 21 M1 49 U7 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79 E10 107 A4 24 N2 52 W11 80 E11 108 C6 25 P1 53 W10 81 D11 109 B7 110 A3 26 P2 54 V11 82 D10 27 R2 55 V10 83 C11 28 R1 56 U11 84 C10 Document #: 38-05289 Rev. *I Page 17 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Range Ambient Temperature Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD Commercial 0°C to +70°C DC to Outputs in Tri-State ................... –0.5V to VDDQ + 0.5V Industrial –40°C to +85°C VDD VDDQ 3.3V –5%/+10% 2.5V – 5% to VDD DC Input Voltage....................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range[13, 14] Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage[13] VIL Input LOW Voltage[13] IX Input Leakage Current except ZZ and MODE Test Conditions Min. 3.135 3.6 V 3.135 VDD V for 2.5V I/O 2.375 2.625 V for 3.3V I/O, IOH = −4.0 mA 2.4 for 2.5V I/O, IOH= −1.0 mA 2.0 for 3.3V I/O, IOL= 8.0 mA V 0.4 V 0.4 V VDD + 0.3V V for 2.5V I/O 1.7 VDD + 0.3V V for 3.3V I/O –0.3 0.8 V for 2.5V I/O –0.3 0.7 V –5 5 µA GND ≤ VI ≤ VDDQ 5 Input = VSS 30 µA 5 µA 4.0-ns cycle, 250 MHz 500 mA 5.0-ns cycle, 200 MHz 500 mA Input = VDD Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = fMAX = 1/tCYC µA µA –5 IOZ VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC µA –30 Input = VDD Automatic CE Power-down Current—TTL Inputs V 2.0 for 3.3V I/O Input Current of MODE Input = VSS ISB1 Unit for 3.3V I/O for 2.5V I/O, IOL= 1.0 mA Input Current of ZZ Max. –5 6.0-ns cycle, 167 MHz 450 mA 4.0-ns cycle, 250 MHz 245 mA 5.0-ns cycle, 200 MHz 245 mA 6.0-ns cycle, 167 MHz 245 mA ISB2 Automatic CE Max. VDD, Device Deselected, All speed grades Power-down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, Current—CMOS Inputs f = 0 120 mA ISB3 Automatic CE Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz Power-down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, 5.0-ns cycle, 200 MHz Current—CMOS Inputs f = fMAX = 1/tCYC 6.0-ns cycle, 167 MHz 245 mA 245 mA 245 mA Automatic CE Power-down Current—TTL Inputs 135 mA ISB4 Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 All speed grades Notes: 13. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2). 14. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05289 Rev. *I Page 18 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Capacitance[15] Parameter Description 100 TQFP Max. Test Conditions CADDRESS Address Input Capacitance CDATA Data Input Capacitance CCTRL Control Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 165 FBGA 209 FBGA Max. Max. Unit 6 6 6 pF 5 5 5 pF 8 8 8 pF 6 6 6 pF 5 5 5 pF Thermal Resistance[15] Parameters Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions 100 TQFP Package 165 FBGA Package 209 FBGA Package Unit 24.63 16.3 15.2 °C/W 2.28 2.1 1.7 °C/W Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω 10% 90% 10% 90% GND 5 pF R = 351Ω ≤ 1 ns ≤ 1 ns VL = 1.5V INCLUDING JIG AND SCOPE (a) (c) (b) 2.5V I/O Test Load R = 1667Ω 2.5V OUTPUT Z0 = 50Ω 10% R = 1538Ω VL = 1.25V INCLUDING JIG AND SCOPE 90% 10% 90% GND 5 pF (a) ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω (b) ≤ 1 ns ≤ 1 ns (c) Note: 15. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05289 Rev. *I Page 19 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Switching Characteristics Over the Operating Range [16, 17] –250 Parameter tPower [18] –200 Max. Min. –167 Description Min. Max. Min. Max. Unit VCC (typical) to the First Access Read or Write 1 1 1 ms 4.0 5.0 6.0 ns Clock tCYC Clock Cycle Time FMAX Maximum Operating Frequency tCH Clock HIGH 2.0 2.0 2.2 ns tCL Clock LOW 2.0 2.0 2.2 ns 250 200 167 MHz Output Times tCO Data Output Valid After CLK Rise tOEV OE LOW to Output Valid tDOH Data Output Hold After CLK Rise tCHZ Clock to High-Z[19, 20, 21] Clock to Low-Z[19, 20, 21] tCLZ 3.0 3.0 1.3 OE HIGH to Output tEOLZ OE LOW to Output Low-Z[19, 20, 21] 3.0 1.3 3.0 1.3 High-Z[19, 20, 21] tEOHZ 3.0 ns 3.4 ns 1.5 3.0 1.3 3.0 3.4 ns 3.4 1.5 3.0 ns ns 3.4 ns 0 0 0 ns 1.4 1.4 1.5 ns Set-up Times tAS Address Set-up Before CLK Rise tDS Data Input Set-up Before CLK Rise 1.4 1.4 1.5 ns tCENS CEN Set-up Before CLK Rise 1.4 1.4 1.5 ns tWES WE, BWx Set-up Before CLK Rise 1.4 1.4 1.5 ns tALS ADV/LD Set-up Before CLK Rise 1.4 1.4 1.5 ns tCES Chip Select Set-up 1.4 1.4 1.5 ns tAH Address Hold After CLK Rise 0.4 0.4 0.5 ns tDH Data Input Hold After CLK Rise 0.4 0.4 0.5 ns tCENH CEN Hold After CLK Rise 0.4 0.4 0.5 ns tWEH WE, BWx Hold After CLK Rise 0.4 0.4 0.5 ns tALH ADV/LD Hold after CLK Rise 0.4 0.4 0.5 ns tCEH Chip Select Hold After CLK Rise 0.4 0.4 0.5 ns Hold Times Notes: 16. Timing reference is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 17. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 18. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated. 19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested. Document #: 38-05289 Rev. *I Page 20 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Switching Waveforms Read/Write/Timing[22, 23, 24] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BWx A1 ADDRESS A2 tCO tAS tDS tAH Data tDH D(A1) tCLZ D(A2) D(A2+1) tDOH Q(A3) tOEV Q(A4) tCHZ Q(A4+1) D(A5) Q(A6) In-Out (DQ) tOEHZ tDOH tOELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UNDEFINED Notes: 22. For this waveform ZZ is tied LOW. 23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 24. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional. Document #: 38-05289 Rev. *I Page 21 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Switching Waveforms (continued) NOP, STALL and DESELECT Cycles[22, 23, 25] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BWx ADDRESS A5 tCHZ D(A1) Data Q(A2) D(A4) Q(A3) Q(A5) In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL DON’T CARE NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED ZZ Mode Timing[26, 27] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 25. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A Write is not performed during this cycle. 26. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 27. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05289 Rev. *I Page 22 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1470V33-167AXC Package Diagram Operating Range Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1472V33-167AXC CY7C1470V33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) CY7C1472V33-167BZC CY7C1470V33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free CY7C1472V33-167BZXC CY7C1474V33-167BGC CY7C1474V33-167BGXC CY7C1470V33-167AXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial CY7C1472V33-167AXI CY7C1470V33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) CY7C1472V33-167BZI CY7C1470V33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free CY7C1472V33-167BZXI CY7C1474V33-167BGI CY7C1474V33-167BGXI 200 CY7C1470V33-200AXC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1472V33-200AXC CY7C1470V33-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) CY7C1472V33-200BZC CY7C1470V33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free CY7C1472V33-200BZXC CY7C1474V33-200BGC CY7C1474V33-200BGXC CY7C1470V33-200AXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial CY7C1472V33-200AXI CY7C1470V33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) CY7C1472V33-200BZI CY7C1470V33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free CY7C1472V33-200BZXI CY7C1474V33-200BGI CY7C1474V33-200BGXI Document #: 38-05289 Rev. *I 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free Page 23 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 250 Ordering Code CY7C1470V33-250AXC Package Diagram Operating Range Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1472V33-250AXC CY7C1470V33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1472V33-250BZC CY7C1470V33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1472V33-250BZXC CY7C1474V33-250BGC CY7C1474V33-250BGXC CY7C1470V33-250AXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial CY7C1472V33-250AXI CY7C1470V33-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1472V33-250BZI CY7C1470V33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1472V33-250BZXI CY7C1474V33-250BGI CY7C1474V33-250BGXI Document #: 38-05289 Rev. *I 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free Page 24 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0.60±0.15 0.20 MIN. 51-85050-*B 1.00 REF. DETAIL Document #: 38-05289 Rev. *I A Page 25 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Package Diagrams (continued) 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165) PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 1 2 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.15(4X) SEATING PLANE 1.40 MAX. 0.36 C 51-85165-*A Document #: 38-05289 Rev. *I Page 26 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Package Diagrams (continued) 209-ball FBGA (14 x 22 x 1.76 mm) (51-85167) 51-85167-** NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05289 Rev. *I Page 27 of 29 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Document History Page Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05289 REV. ECN No. Issue Date Orig. of Change Description of Change ** 114676 08/06/02 PKS New Data Sheet *A 121520 01/27/03 CJM Updated features for package offering Removed 300-MHz offering Changed tCO, tEOV, tCHZ, tEOHZ from 2.4 ns to 2.6 ns (250 MHz), tDOH, tCLZ from 0.8 ns to 1.0 ns (250 MHz), tDOH, tCLZ from 1.0 ns to 1.3 ns (200 MHz) Updated ordering information Changed Advanced Information to Preliminary *B 223721 See ECN NJY Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Included IDD and ISB values Removed 250-MHz offering and included 225-MHz speed bin Changed package outline for 165FBGA package and 209-ball BGA package Removed 119-BGA package offering *C 235012 See ECN RYQ Minor Change: The data sheets do not match on the spec system and external web *D 243572 See ECN NJY Changed ball C11,D11,E11,F11,G11 from DQPb,DQb,DQb,DQb,DQb to DQPa,DQa,DQa,DQa,DQa in page 4 Modified capacitance values in page 20 *E 299511 See ECN SYT Removed 225-MHz offering and included 250-MHz speed bin Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100 TQFP Package on Page # 20 Added lead-free information for 100-Pin TQFP and 165 FBGA Packages Added comment of ‘Lead-free BG packages availability’ below the Ordering Information Add Industrial part numbers in Ordering Info section *F 323039 See ECN PCI Unshaded 250 MHz speed bin in the AC/DC Table and Selection Guide Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Modified VOL, VOH Test Conditions Changed package name from 209-ball PBGA to 209-ball FBGA on page# 5 Removed comment of ‘Lead-free BG packages availability below the Ordering Information Updated Ordering Information Table Changed from Preliminary to Final *G 351937 See ECN PCI Updated Ordering Information Table VBL Document #: 38-05289 Rev. *I Page 28 of 29 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05289 REV. ECN No. Issue Date Orig. of Change *H 416221 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed Three-state to Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 18 Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA to –30 µA and 5 µA Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA to –5 µA and 30 µA Changed VDDQ < VDD to VDDQ < VDD in page #18 Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table *I 472335 See ECN VKN Corrected the typo in the pin configuration for 209-Ball FBGA pinout (Corrected the ball name for H9 to VSS from VSSQ). Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. Document #: 38-05289 Rev. *I Description of Change Page 29 of 29 [+] Feedback