DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM SON Check for Samples: DAC8562, DAC8563, DAC8162, DAC8163, DAC7562, DAC7563 FEATURES DESCRIPTION • The DAC856x, DAC816x, and DAC756x are lowpower, voltage-output, dual-channel, 16-, 14-, and 12bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 4-ppm/°C internal reference, giving a full-scale output voltage range of 2.5 V or 5 V. The internal reference has an initial accuracy of ±5 mV and can source or sink up to 20 mA at the VREFIN/VREFOUT pin. 1 23 • • • • • • • • • • Relative Accuracy: – DAC856x (16-Bit): 4 LSB INL – DAC816x (14-Bit): 1 LSB INL – DAC756x (12-Bit): 0.3 LSB INL Glitch Energy: 0.1 nV-s Bidirectional Reference: Input or 2.5-V Output – Output Disabled by Default – ±5-mV Initial Accuracy (Max) – 4-ppm/°C Temperature Drift (Typ) – 10-ppm/°C Temperature Drift (Max) – 20-mA Sink/Source Capability Power-On Reset to Zero Scale or Mid-Scale Low-Power: 4 mW (Typ, 5-V AVDD, Including Internal Reference Current) Wide Power-Supply Range: 2.7 V to 5.5 V 50-MHz SPI With Schmitt-Triggered Inputs LDAC and CLR Functions Output Buffer With Rail-to-Rail Operation Packages: SON-10 (3x3 mm), MSOP-10 Temperature Range: –40°C to 125°C These devices are monotonic, providing excellent linearity and minimizing undesired code-to-code transient voltages (glitch). They use a versatile threewire serial interface that operates at clock rates up to 50 MHz. The interface is compatible with standard SPI™, QSPI™, Microwire™, and digital signal processor (DSP) interfaces. The DACxx62 devices incorporate a power-on-reset circuit that ensures the DAC output powers up at zero scale until a valid code is written to the device, whereas the DACxx63s similarly power up at mid-scale. These devices contain a power-down feature that reduces current consumption to typically 550 nA at 5 V. The low power consumption, internal reference, and small footprint make these devices ideal for portable, battery-operated equipment. APPLICATIONS • • • • • • • Portable Instrumentation Bipolar Outputs (reference design) PLC Analog Output Module (reference design) Closed-Loop Servo Control Voltage Controlled Oscillator Tuning Data Acquisition Systems Programmable Gain and Offset Adjustment GND AVDD DIN SCLK SYNC The DACxx62 devices are drop-in and functioncompatible with each other, as are the DACxx63s. The entire family is available in MSOP-10 and SON10 packages. Table 1. RELATED DEVICES 16-BIT 14-BIT 12-BIT Reset to zero DAC8562 DAC8162 DAC7562 Reset to mid-scale DAC8563 DAC8163 DAC7563 LDAC CLR Buffer Control Register Control Input Control Logic Control Logic DAC756x (12-Bit) DAC816x (14-Bit) DAC856x (16-Bit) VREFIN/VREFOUT 2.5-V Reference PowerDown Control Logic Data Buffer B DAC Register B DAC VOUTB Data Buffer A DAC Register A DAC VOUTA 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION (1) PRODUCT MAXIMUM RELATIVE ACCURACY (LSB) MAXIMUM DIFFERENTIAL NONLINEARITY (LSB) MAXIMUM REFERENCE DRIFT (ppm/°C) DAC8562 Zero ±12 ±1 Mid-scale DAC8162 Zero ±0.5 10 DAC8163 Mid-scale DAC7562 Zero ±0.75 ±0.25 DAC7563 2 10 DAC8563 ±3 (1) RESET TO 10 Mid-scale PACKAGELEAD PACKAGE DESIGNATOR SON-10 DSC MSOP-10 DGS SON-10 DSC MSOP-10 DGS SON-10 DSC MSOP-10 DGS SON-10 DSC MSOP-10 DGS SON-10 DSC MSOP-10 DGS SON-10 DSC MSOP-10 DGS SPECIFIED TEMPERATURE RANGE PACKAGE MARKING 8562 –40°C to 125°C 8563 8162 –40°C to 125°C 8163 7562 –40°C to 125°C 7563 For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI Web site at www.ti.com. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). AVDD to GND VALUE UNIT –0.3 to 6 V CLR, DIN, LDAC, SCLK and SYNC input voltage to GND –0.3 to AVDD + 0.3 V VOUT to GND –0.3 to AVDD + 0.3 V VREFIN/VREFOUT to GND –0.3 to AVDD + 0.3 V –40 to 125 °C 150 °C Operating temperature range Junction temperature, maximum (TJ max) (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION DAC856x, DAC816x, DAC756x THERMAL METRIC DSC DGS 10 PINS 10 PINS UNIT θJA Junction-to-ambient thermal resistance (1) 62.8 173.8 °C/W θJCtop Junction-to-case (top) thermal resistance (2) 44.3 48.5 °C/W (3) θJB Junction-to-board thermal resistance 26.5 79.9 °C/W ψJT Junction-to-top characterization parameter (4) 0.4 1.7 °C/W ψJB Junction-to-board characterization parameter (5) 25.5 68.4 °C/W (6) 46.2 N/A °C/W θJCbot (1) (2) (3) (4) (5) (6) Junction-to-case (bottom) thermal resistance The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 3 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS At AVDD = 2.7 V to 5.5 V and TA = –40°C to 125°C (unless otherwise noted). PARAMETER STATIC PERFORMANCE TEST CONDITIONS MIN Resolution DAC856x Using line passing through codes 512 and 65,024 Differential nonlinearity 16-bit monotonic UNIT ±4 ±12 LSB ±0.2 ±1 LSB ±1 ±3 LSB ±0.1 ±0.5 LSB ±0.3 ±0.75 LSB ±0.05 ±0.25 LSB ±1 ±4 Bits 14 Relative accuracy Using line passing through codes 128 and 16,256 Differential nonlinearity 14-bit monotonic Resolution DAC756x MAX 16 Relative accuracy Resolution DAC816x TYP (1) Bits 12 Relative accuracy Using line passing through codes 32 and 4,064 Differential nonlinearity 12-bit monotonic Offset error Extrapolated from two-point line Bits (1) , unloaded Offset error drift ±2 Full-scale error DAC register loaded with all 1s ±0.03 ±0.2 Zero-code error DAC register loaded with all 0s 1 4 Zero-code error drift ±2 Extrapolated from two-point line (1), unloaded Gain error ±0.01 Gain temperature coefficient mV µV/°C % FSR mV µV/°C ±0.15 % FSR ppm FSR/°C ±1 OUTPUT CHARACTERISTICS (2) Output voltage range 0 Output voltage settling time (3) Slew rate 7 RL = 1 MΩ 0.75 RL = ∞ 1 RL = 2 kΩ 3 V µs 10 Measured between 20% - 80% of a full-scale transition Capacitive load stability AVDD DACs unloaded V/µs nF Code-change glitch impulse 1-LSB change around major carry 0.1 nV-s Digital feedthrough SCLK toggling, SYNC high 0.1 nV-s Power-on glitch impulse RL = 2 kΩ, CL = 470 pF, AVDD = 5.5 V 40 mV Full-scale swing on adjacent channel, External reference 5 Full-scale swing on adjacent channel, Internal reference 15 Channel-to-channel dc crosstalk µV DC output impedance At mid-scale input 5 Ω Short-circuit current DAC outputs at full-scale, DAC outputs shorted to GND 40 mA Power-up time, including settling time Coming out of power-down mode 50 µs DAC output noise density TA = 25°C, at mid-scale input, fOUT = 1 kHz 90 nV/√Hz DAC output noise TA = 25°C, at mid-scale input, 0.1 Hz to 10 Hz 2.6 µVPP AC PERFORMANCE (2) LOGIC INPUTS (2) Input pin Leakage current –1 Logic input LOW voltage VINL Logic input HIGH voltage VINH ±0.1 1 µA 0 0.8 V 0.7 × AVDD AVDD V 3 pF Pin capacitance (1) (2) (3) 4 16-bit: codes 512 and 65,024; 14-bit: codes 128 and 16,256; 12-bit: codes 32 and 4,064 Specified by design or characterization Transition time between 1/4 scale and 3/4 scale including settling to within ±0.024% FSR Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (continued) At AVDD = 2.7 V to 5.5 V and TA = –40°C to 125°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE External VREF = 2.5 V (when internal reference is disabled), all channels active using gain = 1 External reference current VREFIN reference input range Reference input impedance 15 0 µA AVDD Internal reference disabled, gain = 1 170 Internal reference disabled, gain = 2 85 V kΩ REFERENCE OUTPUT Output voltage TA = 25°C 2.495 2.5 2.505 Initial accuracy TA = 25°C –5 ±0.1 5 mV 4 10 ppm/°C Output voltage temperature drift (4) Output voltage noise f = 0.1 Hz to 10 Hz Output voltage noise density (highfrequency noise) 12 TA = 25°C, f = 1 kHz, CL = 0 µF 250 TA = 25°C, f = 1 MHz, CL = 0 µF 30 TA = 25°C, f = 1 MHz, CL = 4.7 µF 10 V µVPP nV/√Hz Load regulation, sourcing (5) TA = 25°C 20 µV/mA Load regulation, sinking (5) TA = 25°C 185 µV/mA ±20 mA Output current load capability (6) Line regulation TA = 25°C 50 µV/V Long-term stability/drift (aging) (5) TA = 25°C, time = 0 to 1900 hours 100 ppm First cycle 200 Thermal hysteresis (5) Additional cycles ppm 50 POWER REQUIREMENTS (7) Power supply voltage 2.7 AVDD = 3.6 V to 5.5 V IDD AVDD = 2.7 V to 3.6 V AVDD = 3.6 V to 5.5 V 0.25 0.5 Normal mode, internal reference on 0.9 1.6 Power-down modes (8) 0.55 2 Power-down modes (9) 0.55 4 Normal mode, internal reference off 0.2 0.4 Normal mode, internal reference on 0.73 1.4 Power-down modes (8) 0.35 2 Power-down modes (9) 0.35 3 Normal mode, internal reference off 0.9 2.75 Normal mode, internal reference on 3.2 8.8 Power-down modes (8) 2 11 (9) 2 22 Normal mode, internal reference off 0.54 1.44 Normal mode, internal reference on 1.97 5 Power-down modes (8) 0.95 7.2 Power-down modes (9) 0.95 10.8 Power-down modes Power dissipation AVDD = 2.7 V to 3.6 V 5.5 Normal mode, internal reference off V mA µA mA µA mW µW mW µW TEMPERATURE RANGE Specified performance (4) (5) (6) (7) (8) (9) –40 125 °C Internal reference output voltage temperature drift is characterized from –40°C to 125°C. Explained in more detail in the Application Information section of this data sheet. Specified by design or characterization Input code = mid-scale, no load, VINH = AVDD, and VINL = GND Temperature range –40°C to 105°C Temperature range –40°C to 125°C Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 5 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com PIN CONFIGURATIONS DGS (Top View) DSC (Top View) VOUTA 1 10 VOUTB 2 VREFIN/VREFOUT VOUTA 1 10 9 AVDD VOUTB 2 9 AVDD GND 3 8 DIN LDAC 4 7 SCLK 6 SYNC GND 3 8 DIN LDAC 4 7 SCLK CLR 5 6 SYNC CLR 5 MSOP Package (1) Thermal Pad (1) VREFIN/VREFOUT SON Package It is recommended to connect the thermal pad to the ground plane for better thermal dissipation. Table 2. PIN DESCRIPTIONS PIN NAME AVDD DESCRIPTION NO. 9 Power-supply input, 2.7 V to 5.5 V CLR 5 Asynchronous clear input. The CLR input is falling-edge sensitive. When CLR is activated, zero scale (DACxx62) or mid-scale (DACxx63) is loaded to all input and DAC registers. This sets the DAC output voltages accordingly. The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted. DIN 8 Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input. Schmitt-trigger logic input GND 3 Ground reference point for all circuitry on the device LDAC 4 In synchronous mode, data are updated with the falling edge of the 24th SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device. In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC updates. Multiple single-channel commands can be written in order to set different channel buffers to desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output registers. SCLK 7 Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input SYNC 6 Level-triggered control input (active-low). This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output updates following the 24th clock falling edge. If SYNC is taken high before the 23rd clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC756x/DAC816x/DAC856x. Schmitt-trigger logic input VOUTA 1 Analog output voltage from DAC-A VOUTB 2 Analog output voltage from DAC-B VREFIN / VREFOUT 10 Bidirectional voltage reference pin. If internal reference is used, 2.5-V output. 6 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 TIMING DIAGRAM t2 t1 SCLK t6 t4 t5 t3 t7 t8 SYNC t10 t9 DB23 DIN DB0 t12 t11 LDAC(1) LDAC(2) t13 CLR t14 VOUT (1) Asynchronous LDAC update mode. For more information, see the LDAC Functionality section. (2) Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section. Figure 1. Serial Write Operation TIMING REQUIREMENTS (1) (2) At AVDD = 2.7 V to 5.5 V and over –40°C to 125°C (unless otherwise noted). PARAMETER DAC756x/DAC816x/DAC856x MIN TYP MAX UNIT t1 SCLK falling edge to SYNC falling edge (for successful write operation) 10 ns t2 (3) SCLK cycle time 20 ns rd t3 SYNC rising edge to 23 SCLK falling edge (for successful SYNC interrupt) 13 ns t4 Minimum SYNC HIGH time 80 ns t5 SYNC to SCLK falling edge setup time 13 ns t6 SCLK LOW time 8 ns t7 SCLK HIGH time 8 ns t8 SCLK falling edge to SYNC rising edge 10 ns t9 Data setup time 6 ns t10 Data hold time 5 ns t11 SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode 5 ns t12 LDAC pulse duration, LOW time 10 ns t13 CLR pulse duration, LOW time 80 t14 CLR falling edge to start of VOUT transition (1) (2) (3) ns 100 ns All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VINL + VINH)/2. See the Serial Write Operation timing diagram (Figure 1). Maximum SCLK frequency is 50 MHz at AVDD = 2.7 V to 5.5 V. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 7 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com TABLES OF GRAPHS Table 3. Typical Characteristics: Internal Reference Performance POWER-SUPPLY VOLTAGE MEASUREMENT FIGURE NUMBER Internal Reference Voltage vs Temperature Figure 2 Internal Reference Voltage Temperature Drift Histogram Figure 3 Internal Reference Voltage vs Load Current 5.5 V Internal Reference Voltage vs Time Figure 4 Figure 5 Internal Reference Noise Density vs Frequency Figure 6 Internal Reference Voltage vs Supply Voltage 2.7 V – 5.5 V Figure 7 Table 4. Typical Characteristics: DAC Static Performance POWER-SUPPLY VOLTAGE MEASUREMENT FIGURE NUMBER FULL-SCALE, GAIN, OFFSET AND ZERO-CODE ERRORS Full-Scale Error vs Temperature Figure 16 Gain Error vs Temperature 5.5 V Offset Error vs Temperature Figure 17 Figure 18 Zero-Code Error vs Temperature Figure 19 Full-Scale Error vs Temperature Figure 63 Gain Error vs Temperature 2.7 V Offset Error vs Temperature Zero-Code Error vs Temperature Figure 64 Figure 65 Figure 66 LOAD REGULATION DAC Output Voltage vs Load Current 5.5 V Figure 30 2.7 V Figure 74 DIFFERENTIAL NONLINEARITY ERROR T = –40°C Differential Linearity Error vs Digital Input Code T = 25°C T = 125°C Figure 9 5.5 V Differential Linearity Error vs Temperature Figure 13 Figure 15 T = –40°C Differential Linearity Error vs Digital Input Code Figure 11 T = 25°C T = 125°C Figure 56 2.7 V Differential Linearity Error vs Temperature Figure 58 Figure 60 Figure 62 INTEGRAL NONLINEARITY ERROR (RELATIVE ACCURACY) Linearity Error vs Digital Input Code T = –40°C Figure 8 T = 25°C Figure 10 T = 125°C 5.5 V Linearity Error vs Temperature Figure 14 T = –40°C Linearity Error vs Digital Input Code T = 25°C T = 125°C Figure 55 2.7 V Linearity Error vs Temperature 8 Submit Documentation Feedback Figure 12 Figure 57 Figure 59 Figure 61 Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 Table 4. Typical Characteristics: DAC Static Performance (continued) MEASUREMENT POWER-SUPPLY VOLTAGE FIGURE NUMBER POWER-DOWN CURRENT Power-Down Current vs Temperature Power-Down Current vs Power-Supply Voltage Power-Down Current vs Temperature 5.5 V Figure 28 2.7 V – 5.5 V Figure 29 2.7 V Figure 73 POWER-SUPPLY CURRENT Power-Supply Current vs Temperature Power-Supply Current vs Digital Input Code Power-Supply Current Histogram Power-Supply Current vs Power-Supply Voltage Power-Supply Current vs Temperature Power-Supply Current vs Digital Input Code Power-Supply Current Histogram Power-Supply Current vs Temperature Power-Supply Current vs Digital Input Code Power-Supply Current Histogram Copyright © 2010–2012, Texas Instruments Incorporated External VREF Figure 20 Internal VREF Figure 21 External VREF Internal VREF 5.5 V Figure 22 Figure 23 External VREF Figure 24 Internal VREF Figure 25 External VREF Internal VREF 2.7 V – 5.5 V Figure 26 Figure 27 External VREF Figure 49 Internal VREF Figure 50 External VREF Internal VREF 3.6 V Figure 51 Figure 52 External VREF Figure 53 Internal VREF Figure 54 External VREF Figure 67 Internal VREF Figure 68 External VREF Internal VREF 2.7 V Figure 69 Figure 70 External VREF Figure 71 Internal VREF Figure 72 Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 9 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com Table 5. Typical Characteristics: DAC Dynamic Performance MEASUREMENT POWER-SUPPLY VOLTAGE FIGURE NUMBER CHANNEL-TO-CHANNEL CROSSTALK Channel-to-Channel Crosstalk 5-V Rising Edge 5-V Falling Edge 5.5 V Figure 43 Figure 44 CLOCK FEEDTHROUGH Clock Feedthrough 500 kHz, Midscale 5.5 V Figure 48 2.7 V Figure 87 GLITCH ENERGY Glitch Energy, 1-LSB Step Rising Edge, Code 7FFFh to 8000h Figure 37 Falling Edge, Code 8000h to 7FFFh Figure 38 Rising Edge, Code 7FFCh to 8000h Glitch Energy, 4-LSB Step Falling Edge, Code 8000h to 7FFCh Glitch Energy, 16-LSB Step Glitch Energy, 1-LSB Step Figure 39 Figure 40 Rising Edge, Code 7FF0h to 8000h Figure 41 Falling Edge, Code 8000h to 7FF0h Figure 42 Rising Edge, Code 7FFFh to 8000h Figure 79 Falling Edge, Code 8000h to 7FFFh Figure 80 Rising Edge, Code 7FFCh to 8000h Glitch Energy, 4-LSB Step 5.5 V Falling Edge, Code 8000h to 7FFCh 2.7 V Figure 81 Figure 82 Rising Edge, Code 7FF0h to 8000h Figure 83 Falling Edge, Code 8000h to 7FF0h Figure 84 DAC Output Noise Density vs Frequency External VREF Figure 45 DAC Output Noise 0.1 Hz to 10 Hz External VREF Glitch Energy, 16-LSB Step NOISE Internal VREF 5.5 V Figure 46 Figure 47 POWER-ON GLITCH Reset to Zero Scale Power-on Glitch Reset to Midscale Reset to Zero Scale Reset to Midscale 5.5 V 2.7 V Figure 35 Figure 36 Figure 85 Figure 86 SETTLING TIME Full-Scale Settling Time Half-Scale Settling Time Full-Scale Settling Time Half-Scale Settling Time 10 Rising Edge, Code 0h to FFFFh Falling Edge, Code FFFFh to 0h Rising Edge, Code 4000h to C000h Figure 31 5.5 V Figure 32 Figure 33 Falling Edge, Code C000h to 4000h Figure 34 Rising Edge, Code 0h to FFFFh Figure 75 Falling Edge, Code FFFFh to 0h Rising Edge, Code 4000h to C000h 2.7 V Falling Edge, Code C000h to 4000h Submit Documentation Feedback Figure 76 Figure 77 Figure 78 Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS: Internal Reference At TA = 25°C, AVDD = 5.5 V, gain = 2 and VREFOUT, unloaded unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE INTERNAL REFERENCE VOLTAGE TEMPERATURE DRIFT HISTOGRAM 30 2.505 2.504 25 2.503 Population (%) 2.501 2.500 2.499 2.498 2.497 10 5 0 2.495 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Temperature Drift (ppm/ °C) Figure 2. Figure 3. INTERNAL REFERENCE VOLTAGE vs LOAD CURRENT INTERNAL REFERENCE VOLTAGE vs TIME 400 Internal Reference Voltage Shift (ppm) 2.510 2.505 VREFOUT (V) 15 60 units shown (30 MSOP, 30 SON-10) 2.496 2.500 2.495 2.490 −20 −15 −10 −5 0 5 Load Current (mA) 10 15 300 200 100 0 −100 −200 −300 −400 20 16 units shown (8 MSOP, 8 SON-10) Average shown in dashed line 0 250 500 750 1000 Elapsed Time (Hours) 1250 Figure 4. Figure 5. INTERNAL REFERENCE NOISE DENSITY vs FREQUENCY INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE 400 1500 2.505 No Load 4.7 µF Load 350 −40°C +25°C +125°C 2.504 2.503 300 2.502 250 VREFOUT (V) Voltage Noise (nV/rt−Hz) 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 VREFOUT (V) 2.502 200 150 2.501 2.500 2.499 2.498 100 2.497 50 0 2.496 10 100 1k 10k Frequency (Hz) Figure 6. Copyright © 2010–2012, Texas Instruments Incorporated 100k 1M 2.495 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 AVDD (V) Figure 7. Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 11 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 12 1.0 9 0.8 0.6 DNL Error (LSB) INL Error (LSB) 6 3 0 −3 0.4 0.2 0.0 −0.2 −0.4 −6 −0.6 −9 −12 Typical channel shown −40°C 0 Typical channel shown −40°C −0.8 −1.0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 8. Figure 9. LINEARITY ERROR vs DIGITAL INPUT CODE (25°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (25°C) 12 1.0 9 0.8 0.6 DNL Error (LSB) INL Error (LSB) 6 3 0 −3 0.4 0.2 0.0 −0.2 −0.4 −6 −0.6 −9 −12 Typical channel shown 25°C 0 Typical channel shown 25°C −0.8 −1.0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 10. Figure 11. LINEARITY ERROR vs DIGITAL INPUT CODE (125°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (125°C) 12 1.0 9 0.8 0.6 DNL Error (LSB) INL Error (LSB) 6 3 0 −3 0.4 0.2 0.0 −0.2 −0.4 −6 −0.6 −9 −12 Typical channel shown 125°C 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 12. 12 Submit Documentation Feedback Typical channel shown 125°C −0.8 −1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 13. Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 12 1.0 INL Max INL Min 9 DNL Max DNL Min 0.8 0.6 DNL Error (LSB) INL Error (LSB) 6 3 0 −3 0.4 0.2 0.0 −0.2 −0.4 −6 −0.6 −9 Typical channel shown −12 −40 −25 −10 5 20 35 50 65 Temperature (°C) −0.8 80 95 Typical channel shown −1.0 −40 −25 −10 5 20 35 50 65 Temperature (°C) 110 125 Figure 14. Figure 15. FULL-SCALE ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE 0.20 95 110 125 0.15 Ch A Ch B 0.15 Ch A Ch B 0.10 0.10 Gain Error (%FSR) Full−Scale Error (%FSR) 80 0.05 0.00 −0.05 0.05 0.00 −0.05 −0.10 −0.10 −0.15 −0.20 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 −0.15 −40 −25 −10 110 125 Figure 17. OFFSET ERROR vs TEMPERATURE ZERO-CODE ERROR vs TEMPERATURE 80 95 110 125 4.0 Ch A Ch B 3 1 0 −1 −2 −3 Ch A Ch B 3.5 Zero−Code Error (mV) 2 Offset Error (mV) 20 35 50 65 Temperature (°C) Figure 16. 4 −4 −40 −25 −10 5 3.0 2.5 2.0 1.5 1.0 0.5 5 20 35 50 65 Temperature (°C) Figure 18. Copyright © 2010–2012, Texas Instruments Incorporated 80 95 110 125 0.0 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 19. Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 13 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. 0.45 1.2 Power−Supply Current (mA) 1.3 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.9 0.8 0.7 5 20 35 50 65 Temperature (°C) 80 95 Internal reference enabled DACs at midscale code, Gain = 2 0.5 −40 −25 −10 110 125 5 20 35 50 65 Temperature (°C) 80 Figure 20. Figure 21. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 1.3 0.45 1.2 Power−Supply Current (mA) 0.50 0.40 0.35 0.30 0.25 0.20 0.15 0.10 95 110 125 1.1 1.0 0.9 0.8 0.7 0.05 0.6 0.00 0.5 Internal reference enabled, Gain = 2 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 23. POWER-SUPPLY CURRENT HISTOGRAM POWER-SUPPLY CURRENT HISTOGRAM 25 25 20 20 Population (%) 30 15 10 10 0.45 0.43 0.41 0.39 0.37 0.35 0.33 0.31 0.29 0 0.27 0 0.25 5 0.21 Internal reference enabled Gain = 2 15 5 0.19 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 22. 30 0.17 0 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 0 0.15 Power−Supply Current (mA) 1.0 DACs at midscale code 0.00 −40 −25 −10 Population (%) 1.1 0.6 0.05 14 POWER-SUPPLY CURRENT vs TEMPERATURE 0.50 0.23 Power−Supply Current (mA) POWER-SUPPLY CURRENT vs TEMPERATURE Power Supply Current (mA) Power Supply Current (mA) Figure 24. Figure 25. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. POWER-SUPPLY CURRENT vs POWER-SUPPLY VOLTAGE POWER-SUPPLY CURRENT vs POWER-SUPPLY VOLTAGE 0.50 1.2 Power−Supply Current (mA) Power−Supply Current (mA) 0.45 1.3 VREFIN = 2.5 V DACs at midscale code, Gain = 1 0.40 0.35 0.30 0.25 0.20 0.15 0.10 3.1 3.5 3.9 4.3 4.7 5.1 1.0 0.9 0.8 0.7 0.5 2.7 5.5 3.1 3.5 3.9 4.3 4.7 AVDD (V) AVDD (V) Figure 26. Figure 27. POWER-DOWN CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs POWER-SUPPLY VOLTAGE 4.0 Power−Down Current (µA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 −40 −25 −10 5.1 5.5 5.1 5.5 0.60 3.5 Power−Down Current (µA) 1.1 0.6 0.05 0.00 2.7 Internal reference enabled DACs at midscale code, Gain = 1 5 20 35 50 65 Temperature (°C) 80 95 IDD (µA) IREFIN (µA) 0.50 0.40 0.30 0.20 0.10 0.00 2.7 110 125 3.1 3.5 G028 Figure 28. 3.9 4.3 AVDD (V) 4.7 G029 Figure 29. DAC OUTPUT VOLTAGE vs LOAD CURRENT 7.0 Typical channel shown Full scale Mid scale Zero scale 6.0 Output Voltage (V) 5.0 4.0 3.0 2.0 1.0 0.0 −1.0 −20 −15 −10 −5 0 5 10 15 20 ILOAD (mA) Figure 30. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 15 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. FULL-SCALE SETTLING TIME: RISING EDGE FULL-SCALE SETTLING TIME: FALLING EDGE LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) Large Signal VOUT (2 V/div) Large Signal VOUT (2 V/div) Small Signal Settling (1.22 mV/div = 0.024% FSR) Small Signal Settling (1.22 mV/div = 0.024% FSR) From Code: FFFFh To Code: 0h From Code: 0h To Code: FFFFh Time (5 μs/div) Time (5 μs/div) Figure 31. Figure 32. HALF-SCALE SETTLING TIME: RISING EDGE HALF-SCALE SETTLING TIME: FALLING EDGE LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) Large Signal VOUT (2 V/div) Large Signal VOUT (2 V/div) Small Signal Settling (1.22 mV/div = 0.024% FSR) Small Signal Settling (1.22 mV/div = 0.024% FSR) From Code: 4000h To Code: C000h Time (5 μs/div) From Code: C000h To Code: 4000h Time (5 μs/div) Figure 33. Figure 34. POWER-ON GLITCH RESET TO ZERO SCALE POWER-ON GLITCH RESET TO MIDSCALE AVDD (2 V/div) AVDD (2 V/div) VOUTA (1 V/div) VOUTB (1 V/div) VOUTA (50 mV/div) VOUTB (50 mV/div) VREFIN shorted to AVDD VREFIN shorted to AVDD Time (1 ms/div) Figure 35. 16 Submit Documentation Feedback Time (1 ms/div) Figure 36. Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. GLITCH ENERGY RISING EDGE, 1-LSB STEP GLITCH ENERGY FALLING EDGE, 1-LSB STEP LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) LDAC Feedthrough Glitch Impulse » 0.1 nV-s VOUT (100 μV/div) VOUT (100 μV/div) LDAC Feedthrough Glitch Impulse » 0.12 nV-s From Code: 7FFFh To Code: 8000h Time (5 μs/div) From Code: 8000h To Code: 7FFFh Time (5 μs/div) Figure 37. Figure 38. GLITCH ENERGY RISING EDGE, 4-LSB STEP GLITCH ENERGY FALLING EDGE, 4-LSB STEP LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) Glitch Impulse » 0.1 nV-s LDAC Feedthrough VOUT (100 μV/div) VOUT (100 μV/div) LDAC Feedthrough Glitch Impulse » 0.14 nV-s From Code: 8000h To Code: 7FFCh From Code: 7FFCh To Code: 8000h Time (5 μs/div) Time (5 μs/div) Figure 39. Figure 40. GLITCH ENERGY RISING EDGE, 16-LSB STEP GLITCH ENERGY FALLING EDGE, 16-LSB STEP LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) Glitch Impulse » 0.1 nV-s VOUT (500 μV/div) LDAC Feedthrough LDAC Feedthrough VOUT (500 μV/div) Glitch Impulse » 0.1 nV-s From Code: 7FF0h To Code: 8000h Time (5 μs/div) Figure 41. Copyright © 2010–2012, Texas Instruments Incorporated From Code: 8000h To Code: 7FF0h Time (5 μs/div) Figure 42. Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 17 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. CHANNEL-TO-CHANNEL CROSSTALK 5-V RISING EDGE CHANNEL-TO-CHANNEL CROSSTALK 5-V FALLING EDGE LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) VOUTB (1 V/div) 6.4 μs Glitch Area (Between Cursors) = 2 nV-s VOUTA (500 μV/div) VOUTA (500 μV/div) VOUTA at Midscale Code Internal Reference Enabled Gain = 2 Glitch Area (Between Cursors) = 1.6 nV-s 7.3 μs VOUTB (1 V/div) VOUTA at Midscale Code Internal Reference Enabled Gain = 2 Time (5 μs/div) Time (5 μs/div) Figure 43. Figure 44. DAC OUTPUT NOISE DENSITY vs FREQUENCY DAC OUTPUT NOISE DENSITY vs FREQUENCY 1400 1400 Voltage Noise (nV/rt−Hz) 1200 Full Scale Mid Scale Zero Scale 1000 800 600 400 200 0 Internal reference enabled Gain = 2 1200 Voltage Noise (nV/rt−Hz) Internal reference disabled VREFIN = 5 V, Gain = 1 Full Scale Mid Scale Zero Scale 1000 800 600 400 200 10 100 1k Frequency (Hz) 10k 100k 0 10 100 1k Frequency (Hz) 10k Figure 45. Figure 46. DAC OUTPUT NOISE 0.1 Hz TO 10 Hz CLOCK FEEDTHROUGH 500 kHz, MIDSCALE 100k VNOISE (1 μV/div) SCLK (5 V/div) VOUT (500 μV/div) » 2.5 μVPP Clock Feedthrough Impulse » 0.06 nV-s DAC = Midscale Time (500 ns/div) Figure 47. 18 Submit Documentation Feedback Figure 48. Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6 V At TA = 25°C, 3.3-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. 0.50 1.3 0.45 1.2 0.40 0.35 0.30 0.25 0.20 0.15 0.10 1.0 0.9 0.8 0.7 5 20 35 50 65 Temperature (°C) 80 95 0.5 −40 −25 −10 110 125 5 20 35 50 65 Temperature (°C) 80 Figure 49. Figure 50. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 1.3 0.45 1.2 Power−Supply Current (mA) 0.50 0.40 0.35 0.30 0.25 0.20 0.15 0.10 95 110 125 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.05 Internal reference enabled, Gain = 1 0 0.4 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 52. POWER-SUPPLY CURRENT HISTOGRAM POWER-SUPPLY CURRENT HISTOGRAM 25 25 20 20 Population (%) 30 15 10 10 0.40 0.38 0.36 0.34 0.32 0.30 0.28 0.26 0.24 0.22 0.20 0 0.18 0 0.16 5 0.14 Internal reference enabled Gain = 1 15 5 0.12 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 51. 30 0.10 0 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 0.00 Internal reference enabled DACs at midscale code, Gain = 1 DACs at midscale code 0.00 −40 −25 −10 Population (%) 1.1 0.6 0.05 Power−Supply Current (mA) POWER-SUPPLY CURRENT vs TEMPERATURE Power−Supply Current (mA) Power−Supply Current (mA) POWER-SUPPLY CURRENT vs TEMPERATURE Power Supply Current (mA) Power Supply Current (mA) Figure 53. Figure 54. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 19 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7 V At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 12 1.0 9 0.8 0.6 DNL Error (LSB) INL Error (LSB) 6 3 0 −3 0.4 0.2 0.0 −0.2 −0.4 −6 −0.6 −9 −12 Typical channel shown −40°C 0 Typical channel shown −40°C −0.8 −1.0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 55. Figure 56. LINEARITY ERROR vs DIGITAL INPUT CODE (25°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (25°C) 12 1.0 9 0.8 0.6 DNL Error (LSB) INL Error (LSB) 6 3 0 −3 0.4 0.2 0.0 −0.2 −0.4 −6 −0.6 −9 −12 Typical channel shown 25°C 0 Typical channel shown 25°C −0.8 −1.0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 57. Figure 58. LINEARITY ERROR vs DIGITAL INPUT CODE (125°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (125°C) 12 1.0 9 0.8 0.6 DNL Error (LSB) INL Error (LSB) 6 3 0 −3 0.4 0.2 0.0 −0.2 −0.4 −6 −0.6 −9 −12 Typical channel shown 125°C 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 59. 20 Submit Documentation Feedback Typical channel shown 125°C −0.8 −1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 60. Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7 V (continued) At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 12 1.0 INL Max INL Min 9 DNL Max DNL Min 0.8 0.6 DNL Error (LSB) INL Error (LSB) 6 3 0 −3 0.4 0.2 0.0 −0.2 −0.4 −6 −0.6 −9 Typical channel shown −12 −40 −25 −10 5 20 35 50 65 Temperature (°C) −0.8 80 95 Typical channel shown −1.0 −40 −25 −10 5 20 35 50 65 Temperature (°C) 110 125 Figure 61. Figure 62. FULL-SCALE ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE 0.20 95 110 125 0.15 Ch A Ch B 0.15 Ch A Ch B 0.10 0.10 Gain Error (%FSR) Full−Scale Error (%FSR) 80 0.05 0.00 −0.05 0.05 0.00 −0.05 −0.10 −0.10 −0.15 −0.20 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 −0.15 −40 −25 −10 110 125 Figure 64. OFFSET ERROR vs TEMPERATURE ZERO-CODE ERROR vs TEMPERATURE 80 95 110 125 4.0 Ch A Ch B 3 1 0 −1 −2 −3 Ch A Ch B 3.5 Zero−Code Error (mV) 2 Offset Error (mV) 20 35 50 65 Temperature (°C) Figure 63. 4 −4 −40 −25 −10 5 3.0 2.5 2.0 1.5 1.0 0.5 5 20 35 50 65 Temperature (°C) Figure 65. Copyright © 2010–2012, Texas Instruments Incorporated 80 95 110 125 0.0 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 66. Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 21 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7 V (continued) At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. POWER-SUPPLY CURRENT vs TEMPERATURE 0.40 1.3 0.35 1.2 Power−Supply Current (mA) Power−Supply Current (mA) POWER-SUPPLY CURRENT vs TEMPERATURE 0.30 0.25 0.20 0.15 0.10 0.05 1.1 1.0 0.9 0.8 0.7 0.6 Internal reference enabled DACs at midscale code, Gain = 1 DACs at midscale code 5 20 35 50 65 Temperature (°C) 80 95 0.5 −40 −25 −10 110 125 5 20 35 50 65 Temperature (°C) 80 Figure 67. Figure 68. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 0.40 1.3 0.35 1.2 Power−Supply Current (mA) Power−Supply Current (mA) 0.00 −40 −25 −10 0.30 0.25 0.20 0.15 0.10 95 110 125 1.1 1.0 0.9 0.8 0.7 0.6 0.05 0.5 0.00 0.4 22 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 70. POWER-SUPPLY CURRENT HISTOGRAM POWER-SUPPLY CURRENT HISTOGRAM 25 25 20 20 Population (%) 30 15 10 10 0.40 0.38 0.36 0.34 0.32 0.30 0.28 0.26 0.24 0.22 0 0.20 0 0.18 5 0.16 Internal reference enabled Gain = 1 15 5 0.14 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 69. 30 0.12 0 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 0 0.10 Population (%) Internal reference enabled, Gain = 1 Power Supply Current (mA) Power Supply Current (mA) Figure 71. Figure 72. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7 V (continued) At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. POWER-DOWN CURRENT vs TEMPERATURE DAC OUTPUT VOLTAGE vs LOAD CURRENT 3.0 4 Full scale Mid scale Zero scale 3 2.0 Output Voltage (V) Power−Down Current (µA) Typical channel shown 2.5 1.5 1.0 0.5 2 1 0 0.0 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 110 125 G073 −1 −20 −15 −10 −5 0 5 10 15 20 ILOAD (mA) Figure 73. Figure 74. FULL-SCALE SETTLING TIME: RISING EDGE FULL-SCALE SETTLING TIME: FALLING EDGE LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) Large Signal VOUT (1 V/div) Large Signal VOUT (1 V/div) Small Signal Settling (0.61 mV/div = 0.024% FSR) Small Signal Settling (0.61 mV/div = 0.024% FSR) From Code: FFFFh To Code: 0h From Code: 0h To Code: FFFFh Time (5 μs/div) Time (5 μs/div) Figure 75. Figure 76. HALF-SCALE SETTLING TIME: RISING EDGE HALF-SCALE SETTLING TIME: FALLING EDGE LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) Large Signal VOUT (1 V/div) Large Signal VOUT (1 V/div) Small Signal Settling (0.61 mV/div = 0.024% FSR) Small Signal Settling (0.61 mV/div = 0.024% FSR) From Code: 4000h To Code: C000h Time (5 μs/div) Figure 77. Copyright © 2010–2012, Texas Instruments Incorporated From Code: C000h To Code: 4000h Time (5 μs/div) Figure 78. Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 23 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7 V (continued) At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. GLITCH ENERGY RISING EDGE, 1-LSB STEP GLITCH ENERGY FALLING EDGE, 1-LSB STEP LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) LDAC Feedthrough Glitch Impulse » 0.1 nV-s VOUT (100 μV/div) VOUT (100 μV/div) LDAC Feedthrough Glitch Impulse » 0.1 nV-s From Code: 7FFFh To Code: 8000h From Code: 8000h To Code: 7FFFh Time (5 μs/div) Time (5 μs/div) Figure 79. Figure 80. GLITCH ENERGY RISING EDGE, 4-LSB STEP GLITCH ENERGY FALLING EDGE, 4-LSB STEP LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) Glitch Impulse » 0.1 nV-s LDAC Feedthrough VOUT (100 μV/div) VOUT (100 μV/div) LDAC Feedthrough Glitch Impulse » 0.1 nV-s From Code: 7FFCh To Code: 8000h From Code: 8000h To Code: 7FFCh Time (5 μs/div) Time (5 μs/div) Figure 81. Figure 82. GLITCH ENERGY RISING EDGE, 16-LSB STEP GLITCH ENERGY FALLING EDGE, 16-LSB STEP LDAC Trigger (5 V/div) Glitch Impulse » 0.1 nV-s VOUT (200 μV/div) LDAC Trigger (5 V/div) LDAC Feedthrough LDAC Feedthrough VOUT (200 μV/div) Glitch Impulse » 0.1 nV-s From Code: 7FF0h To Code: 8000h Time (5 μs/div) Figure 83. 24 Submit Documentation Feedback From Code: 8000h To Code: 7FF0h Time (5 μs/div) Figure 84. Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7 V (continued) At TA = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted. POWER-ON GLITCH RESET TO ZERO SCALE POWER-ON GLITCH RESET TO MIDSCALE AVDD (2 V/div) AVDD (2 V/div) VOUTA (500 mV/div) VOUTB (500 mV/div) VOUTA (50 mV/div) VOUTB (50 mV/div) VREFIN shorted to AVDD VREFIN shorted to AVDD Time (1 ms/div) Time (1 ms/div) Figure 85. Figure 86. CLOCK FEEDTHROUGH 500 kHz, MIDSCALE SCLK (2 V/div) Clock Feedthrough Impulse » 0.02 nV-s VOUT (500 μV/div) Time (500 ns/div) Figure 87. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 25 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) The DAC756x, DAC816x, and DAC856x architecture consists of two string DACs, each followed by an output buffer amplifier. The devices include an internal 2.5-V reference with 4-ppm/°C temperature drift performance. Figure 88 shows a principal block diagram of the DAC architecture. Gain Register DIN n DAC Register VREFIN/ VREFOUT 150 kW REF(+) Resistor String REF(-) 150 kW VOUT GND Figure 88. DAC Architecture The input coding to the DAC756x, DAC816x, and DAC856x is straight binary, so the ideal output voltage is given by Equation 1: æD ö VO UT = ç IN ´ VREF ´ Gain n ÷ è 2 ø (1) where: n = resolution in bits; either 12 (DAC756x), 14 (DAC816x) or 16 (DAC856x) DIN = decimal equivalent of the binary code that is loaded to the DAC register. DIN ranges from 0 to 2n – 1. VREF = DAC reference voltage; either VREFOUT from the internal 2.5-V reference or VREFIN from an aaa external reference. Gain = 1 by default when internal reference is disabled (using external reference), and gain = 2 by default aaa when using internal reference. Gain can also be manually set to either 1 or 2 using the gain register. aaa See the GAIN REGISTERS section for more information. 26 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 Resistor String The resistor string section is shown in Figure 89. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. The resistor string architecture guarantees monotonicity. The RDIVIDER switch is controlled by the gain registers (see the GAIN REGISTERS section). Because the output amplifier has a gain of two, RDIVIDER is not shorted when the DAC-n gain is set to one (default if internal reference is disabled), and is shorted when the DAC-n gain is set to two (default if internal reference is enabled). VREFIN/VREFOUT RDIVIDER VREF 2 R R To Output Amplifier R R Figure 89. Resistor String Output Amplifier The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a maximum output range of 0 V to AVDD. It is capable of driving a load of 2 kΩ in parallel with 3 nF to GND. The typical slew rate is 0.75 V/µs, with a typical full-scale settling time of 14 µs as shown in Figure 31, Figure 32, Figure 75 and Figure 76. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 27 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com INTERNAL REFERENCE The DAC756x, DAC816x, and DAC856x include a 2.5-V internal reference that is disabled by default. The internal reference is externally available at the VREFIN/VREFOUT pin. The internal reference output voltage is 2.5 V and can sink and source up to 20 mA. A minimum 150-nF capacitor is recommended between the reference output and GND for noise filtering. The internal reference of the DAC756x, DAC816x, and DAC856x is a bipolar transistor based precision bandgap voltage reference. Figure 90 shows the basic bandgap topology. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater than that of Q2. The difference of the two base-emitter voltages (VBE1 – VBE2) has a positive temperature coefficient and is forced across resistor R1. This voltage is amplified and added to the base-emitter voltage of Q2, which has a negative temperature coefficient. The resulting output voltage is virtually independent of temperature. The short-circuit current is limited by design to approximately 100 mA. VREFIN/VREFOUT Reference Enable Q1 Q2 R1 R2 Figure 90. Bandgap Reference Simplified Schematic 28 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 POWER-ON RESET Power-On Reset to Zero-scale The DAC7562, DAC8162, and DAC8562 contain a power-on-reset circuit that controls the output voltage during power up. All device registers are reset as shown in Table 6. At power up all DAC registers are filled with zeros and the output voltages of all DAC channels are set to zero volts. Each DAC channel remains that way until a valid load command is written to it. The power-on reset is useful in applications where it is important to know the state of the output of each DAC while the device is in the process of powering up. No device pin should be brought high before power is applied to the device. The internal reference is disabled by default and remains that way until a valid reference-change command is executed. Power-On Reset to Mid-scale The DAC7563, DAC8163, and DAC8563 contain a power-on reset circuit that controls the output voltage during power up. At power up, all DAC registers are reset to mid-scale code and the output voltages of all DAC channels are set to VREFIN/2 volts. Each DAC channel remains that way until a valid load command is written to it. The power-on reset is useful in applications where it is important to know the state of the output of each DAC while the device is in the process of powering up. No device pin should be brought high before power is applied to the device. The internal reference is powered off/down by default and remains that way until a valid referencechange command is executed. If using an external reference, it is acceptable to power on the VREFIN either at the same time as or after AVDD is applied. Table 6. DACxx62 and DACxx63 Power-On Reset Values REGISTER DAC and Input registers DEFAULT SETTING DACxx62 Zero-scale DACxx63 Mid-scale LDAC registers LDAC pin enabled for both channels Power-down registers DACs powered up Internal reference register Internal reference disabled Gain registers Gain = 1 for both channels Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 29 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com Power-On Reset (POR) Levels When the device powers up, a POR circuit sets the device in default mode as shown in Table 6. The POR circuit requires specific AVDD levels, as indicated in Figure 91, to ensure discharging of internal capacitors and to reset the device on power up. In order to ensure a power-on reset, AVDD must be below 0.7 V for at least 1 ms. When AVDD drops below 2.2 V but remains above 0.7 V (shown as the undefined region), the device may or may not reset under all specified temperature and power-supply conditions. In this case, TI recommends a power-on reset. When AVDD remains above 2.2 V, a power-on reset does not occur. AVDD (V) 5.50 No Power-On Reset Specified Supply Voltage Range 2.70 2.20 Undefined 0.70 Power-On Reset 0.00 Figure 91. Relevant Voltage Levels for POR Circuit CLR FUNCTIONALITY The edge-triggered CLR pin can be used to set the input and DAC registers immediately according to Table 7. When the CLR pin receives a falling edge signal the clear mode is activated and changes the DAC output voltages accordingly. The part exits clear mode on the 24th falling edge of the next write to the part. If the CLR pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated and changes the input and DAC registers immediately according to Table 7. Table 7. Clear Mode Reset Values 30 DEVICE DAC Output Entering Clear Mode DAC8562, DAC8162, DAC7562 Zero-scale DAC8563, DAC8163, DAC7563 Mid-scale Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 SERIAL INTERFACE The DAC756x, DAC816x, and DAC856x have a 3-wire serial interface (SYNC, SCLK, and DIN; see the Pin Descriptions) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Serial Write Operation timing diagram (Figure 1) for an example of a typical write sequence. The DAC756x, DAC816x, or DAC856x input shift register is 24-bits wide, consisting of two don’t care bits (DB23 to DB22), three command bits (DB21 to DB19), three address bits (DB18 to DB16), and 16 data bits (DB15 to DB0). The 16 data bits comprise the 16-, 14-, or 12-bit input code. All 24 bits of data are loaded into the DAC under the control of the serial clock input, SCLK. DB23 (MSB) is the first bit that is loaded into the DAC shift register. It is followed by the rest of the 24-bit word pattern, left-aligned. This configuration means that the first 24 bits of data are latched into the shift register, and any further clocking of data is ignored. When the DAC registers are being written to, the DAC756x, DAC816x, and DAC856x receive all 24 bits of data, ignore DB23 and DB22, and decode the next three bits (DB21 to DB19) in order to determine the DAC operating/control mode (see Table 8 through Table 10). Bits DB18 to DB16 are used to address DAC channels. The next 16/14/12 bits of data that follow are decoded by the DAC to determine the equivalent analog output. For more details on these and other commands (such as write to LDAC register, power down DACs, etc.), see their respective sections. The data format is straight binary, with all 0s corresponding to 0-V output and all 1s corresponding to full-scale output. For all documentation purposes, the data format and representation used here is a true 16-bit pattern (that is, FFFFh data word for full scale) that the DAC756x, DAC816x, and DAC856x require. The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the DAC756x, DAC816x, and DAC856x compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked into the shift register and the shift register locks. Further clocking does not change the shift register data. After receiving the 24th falling clock edge, the DAC756x, DAC816x, and DAC856x decode the three command bits and three address bits and 16/14/12 data bits to perform the required function, without waiting for a SYNC rising edge. After the 24th falling edge of SCLK is received, the SYNC line may be kept low or brought high. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must be met in order to begin the next cycle properly; see the Serial Write Operation timing diagram (Figure 1). A rising edge of SYNC before the 24-bit sequence is complete resets the SPI interface; no data transfer occurs. A new write sequence starts at the next falling edge of SYNC. To assure the lowest power consumption of the device, care should be taken that the levels are as close to each rail as possible. SYNC Interrupt In a normal write sequence, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed DAC register updates on the 24th falling edge. However, if SYNC is brought high before the 23rd falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as shown in Figure 92). 24th Falling Edge 24th Falling Edge CLK SYNC DIN DB23 DB23 DB0 Invalid/Interrupted Write Sequence: Output/Mode Does Not Update on the Falling Edge DB0 Valid Write Sequence: Output/Mode Updates on the Falling Edge Figure 92. SYNC Interrupt Facility Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 31 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com Input Shift Register The input shift register (SR) of the DAC856x, DAC816x, and DAC756x is 24 bits wide (as shown in Table 8, Table 9, and Table 10, respectively), and consists of two don’t care bits (DB23 to DB22), three command bits (DB21 to DB19), three address bits (DB18 to DB16), and 16 data bits (DB15 to DB0). The 16 data bits comprise the 16-, 14-, or 12-bit input code. Table 8. DAC856x Data Input Register Format Command X (1) X C2 C1 Address C0 A2 A1 Data A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DB23 (1) D0 DB0 X' denotes don't care bits. Table 9. DAC816x Data Input Register Format Command X X C2 C1 Address C0 A2 A1 Data A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X DB23 X DB0 Table 10. DAC756x Data Input Register Format Command X X C2 C1 Address C0 A2 A1 Data A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X DB23 X X X DB0 The DAC856x, DAC816x, and DAC756x support a number of different load commands. The load commands are summarized in Table 11 and Table 12, and fully exhausted in Table 13. Table 11. Commands for the DAC856x, DAC816x, and DAC756x C2 (DB21) C1 (DB20) C0 (DB19) 0 0 0 Write to input register n (Table 12) 0 0 1 Software LDAC, update DAC register n (Table 12) 0 1 0 Write to input register n (Table 12) and update all DAC registers 0 1 1 Write to input register n and update DAC register n (Table 12) 1 0 0 Set DAC power up/down mode 1 0 1 Software reset 1 1 0 Set LDAC registers 1 1 1 Enable/disable internal reference Command Table 12. Address Select for the DAC856x, DAC816x, and DAC756x 32 A2 (DB18) A1 (DB17) A0 (DB16) 0 0 0 DAC-A 0 0 1 DAC-B 0 1 0 Gain (only use with command 000) 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 DAC-A and DAC-B Submit Documentation Feedback Channel (n) Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 Table 13. Command Matrix for the DAC856x, DAC816x, and DAC756x Command Address DB23DB22 C2 C1 C0 X (1) 0 0 0 X X X X X X X X X X X (1) 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 1 1 0 Data DB15DB6 A0 0 0 0 16/14/12 bit DAC data Write to DAC-A input register 0 0 1 16/14/12 bit DAC data Write to DAC-B input register 1 1 1 16/14/12 bit DAC data Write to DAC-A and DAC-B input registers 0 0 0 16/14/12 bit DAC data Write to DAC-A input register and update all DACs 0 0 1 16/14/12 bit DAC data Write to DAC-B input register and update all DACs 1 1 1 16/14/12 bit DAC data Write to DAC-A and DAC-B input register and update all DACs 0 0 0 16/14/12 bit DAC data Write to DAC-A input register and update DAC-A 0 0 1 16/14/12 bit DAC data Write to DAC-B input register and update DAC-B 1 1 1 16/14/12 bit DAC data Write to DAC-A and DAC-B input register and update all DACs 0 0 0 X Update DAC-A 0 0 1 X Update DAC-B 1 1 1 X 0 1 0 X 0 X 0 X 0 X 1 X 0 X 1 X DB4 DESCRIPTION A1 0 DB5 DB3DB2 A2 DB1 DB0 Update all DACs 0 0 Gain: DAC-B gain = 2, DAC-A gain = 2 (default with internal VREF) 0 1 Gain: DAC-B gain = 2, DAC-A gain = 1 1 0 Gain: DAC-B gain = 1, DAC-A gain = 2 1 1 Gain: DAC-B gain = 1, DAC-A gain = 1 (power-on default) 0 1 Power up DAC-A 1 0 Power up DAC-B 1 1 Power up DAC-A and DAC-B 0 1 Power down DAC-A; 1 kΩ to GND 1 0 Power down DAC-B; 1 kΩ to GND 1 1 Power down DAC-A and DAC-B; 1 kΩ to GND 0 1 Power down DAC-A; 100 kΩ to GND 1 0 Power down DAC-B; 100 kΩ to GND 1 1 Power down DAC-A and DAC-B; 100 kΩ to GND 0 1 Power down DAC-A; Hi-Z 1 0 Power down DAC-B; Hi-Z 1 1 Power down DAC-A and DAC-B; Hi-Z X 0 Reset DAC-A and DAC-B input register and update all DACs X 1 Reset all registers and update all DACs (Power-on-reset update) 0 0 LDAC pin active for DAC-B and DAC-A 0 1 LDAC pin active for DAC-B; inactive for DAC-A 1 0 LDAC pin inactive for DAC-B; active for DAC-A 1 1 LDAC pin inactive for DAC-B and DAC-A X 0 Disable internal reference and reset DACs to gain = 1 X 1 Enable Internal Reference & reset DACs to gain = 2 X X X X X 0 0 0 1 1 0 1 1 X X X X X X X X' denotes don't care bits. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 33 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com GAIN REGISTERS The gain register controls the GAIN setting in the DAC transfer function: æD ö VO UT = ç IN ´ VREF ´ Gain n ÷ è 2 ø (2) The DAC756x, DAC816x, and DAC856x have a gain register for each channel. The gain for each channel, in Equation 2, is either 1 or 2. This gain is automatically set to 2 when using the internal reference, and is automatically set to 1 when the internal reference is disabled (default). However, each channel can have either gain by setting the registers appropriately. The gain registers are accessible by using command bits = 000 and address bits = 010, and using DB1 for DAC-B and DB0 for DAC-A. See Table 13 or Table 14 and Table 15 for the full command structure. The gain registers are automatically reset to provide either gain of 1 or 2 when the internal reference is powered off or on, respectively. After the reference is powered off or on, the gain register is again accessible to change the gain. Table 14. Gain Register Command Structure Command X X 0 0 0 Address 0 1 Data 0 X X X X X X X X X X X X X DB23 X DAC-B DAC-A DB0 Table 15. DAC-n Selection for Gain Register Command DB1/DB0 Value DB0 0 DAC-A uses gain = 2 (default with internal reference) 1 DAC-A uses gain = 1 (default with external reference) 0 DAC-B uses gain = 2 (default with internal reference) 1 DAC-B uses gain = 1 (default with external reference) DB1 34 Submit Documentation Feedback Gain Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 POWER-DOWN MODES The DAC756x, DAC816x, and DAC856x have two separate sets of power-down commands. One set is for the DAC channels and the other set is for the internal reference. The internal reference is forced to a powered down state while both DAC channels are powered down, and is only enabled if any DAC channel is also in normal mode of operation. For more information on the internal reference control, see the INTERNAL REFERENCE ENABLE REGISTER section. DAC Power-Down Commands The DAC756x, DAC816x, and DAC856x DACs use four modes of operation. These modes are accessed by setting command bits C2, C1, and C0, and power-down register bits DB5 and DB4. The command bits must be set to 100. Once the command bits are set correctly, the four different power down modes are software programmable by setting bits DB5 and DB4 in the shift register. Table 13 or Table 16 through Table 18 shows how to control the operating mode with data bits PD1 (DB5), PD0 (DB4), DB1, and DB0. Table 16. DAC Power Mode Register Command Structure Command X X 1 0 0 Address X X Data X X X X X X X X X X X PD1 PD0 X X DAC-B DAC-A DB23 DB0 Table 17. DAC-n Operating Modes PD1 (DB5) PD0 (DB4) 0 0 Power up selected DACs (normal mode, default) DAC OPERATING MODES 0 1 Power down selected DACs 1 kΩ to GND 1 0 Power down selected DACs 100 kΩ to GND 1 1 Power down selected DACs Hi-Z to GND Table 18. DAC-n Selection for Operating Modes DB1/DB0 Operating Mode 0 DAC-n does not change operating mode 1 DAC-n operating mode set to value on PD1 and PD0 It is possible to write to the DAC register/buffer of the DAC channel that is powered down. When the DAC channel is then powered up, it powers up to this new value. The advantage of the available power-down modes is that the output impedance of the device is known while it is in power-down mode. As described in Table 17, there are three different power-down options. VOUT can be connected internally to GND through a 1-kΩ resistor, a 100-kΩ resistor, or open-circuited (Hi-Z). The DAC powerdown circuitry is shown in Figure 93. Resistor String DAC Amplifier Power-Down Circuitry VOUTX Resistor Network Figure 93. Output Stage Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 35 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com SOFTWARE RESET FUNCTION The DAC756x, DAC816x, and DAC856x contain a software reset feature. The software reset function uses command 101. The software reset command contains two reset modes which are software-programmable by setting bit DB0 in the shift register. Table 13 and/or Table 19 and Table 20 show the available software reset commands. Table 19. Software Reset Command Structure Command X X 1 0 Address 1 X X Data X X X X X X X X X X X X X DB23 X X X RST DB0 Table 20. Software Reset RST (DB0) Registers Reset to Default Values 0 DAC registers Input registers 1 DAC registers Input registers LDAC registers Power-down registers Internal reference register Gain registers LDAC FUNCTIONALITY The DAC756x, DAC816x, and DAC856x offer both a software and hardware simultaneous update and control function. The DAC double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. DAC756x, DAC816x, and DAC856x data updates can be performed either in synchronous or in asynchronous mode. In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output registers. Data buffers of all channels must be loaded with desired data before an LDAC falling edge. After a high-to-low LDAC transition, all DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is triggered. LDAC must be returned high before the next serial command is initiated. In synchronous mode, data are updated with the falling edge of the 24th SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device. 36 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 2-bit word (DB1 and DB0) using command bits C2, C1, and C0 (see Table 13 or Table 21). The default value for each bit, and therefore for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is internally tied low for that particular DAC channel) and this DAC channel updates synchronously after the falling edge of the 24th SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the LDAC pin. The combination of software and hardware simultaneous update functions is particularly useful in applications when updating a DAC channel, while keeping the other channel unaffected; see Table 13 or Table 21 and Table 22 for more information. Table 21. LDAC Register Command Structure Command X X 1 1 Address 0 X X Data X X X X X X X X X X X X X X X DAC-B DAC-A DB23 DB0 Table 22. DAC-n Selection for LDAC Register Command DB1/DB0 Value DB0 0 DAC-A uses LDAC pin 1 DAC-A operates in synchronous mode 0 DAC-B uses LDAC pin 1 DAC-B operates in synchronous mode DB1 LDAC Pin Functionality INTERNAL REFERENCE ENABLE REGISTER The internal reference in the DAC756x, DAC816x, and DAC856x is disabled by default for debugging, evaluation purposes, or when using an external reference. The internal reference can be powered up and powered down using a serial command that requires a 24-bit write sequence, as shown in Table 23 and Table 24. The internal reference is forced to a powered down state while both DAC channels are powered down, and is only enabled if any DAC channel is in normal mode of operation in addition to using the command in Table 23. During the time that the internal reference is disabled, the DAC functions normally using an external reference. At this point, the internal reference is disconnected from the VREFIN/VREFOUT pin (Hi-Z output). Enabling Internal Reference To enable the internal reference, write the 24-bit serial command shown in Table 23. When performing a power cycle to reset the device, the internal reference is switched off (default mode). In the default mode, the internal reference is powered down until a valid write sequence is applied to power up the internal reference. However, the internal reference is forced to a disabled state while both DAC channels are powered down, and remains disabled until either DAC channel is returned to the normal mode of operation. See DAC Power-Down Commands for more information on DAC channel modes of operation. Table 23. Write Sequence for Enabling Internal Reference Command X X 1 1 Address 1 X X Data X X X X X X X X X X X X X X X X DB23 1 DB0 Disabling Internal Reference To disable the internal reference, write the 24-bit serial command shown in Table 24. When performing a power cycle to reset the device, the internal reference is disabled (default mode). Table 24. Write Sequence for Disabling Internal Reference Command X X 1 1 Address 1 X X Data X X X X X X X X X X X X X X X X DB23 0 DB0 Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 37 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com APPLICATION INFORMATION INTERNAL REFERENCE The internal reference of the DAC756x, DAC816x, and DAC856x does not require an external load capacitor for stability because it is stable without any capacitive load. However, for improved noise performance, an external load capacitor of 150 nF or larger connected to the VREFIN/VREFOUT output is recommended. Figure 94 shows the typical connections required for operation of the DAC756x, DAC816x, and DAC856x internal reference. A supply bypass capacitor at the AVDD input is also recommended. DSC DGS 150 nF 1 VOUTA VREFIN/ 10 VREFOUT 2 VOUTB AVDD 9 3 GND DIN 8 7 4 LDAC SCLK 7 6 5 CLR SYNC 6 1 VOUTA VREFIN/VREFOUT 10 2 VOUTB AVDD 9 3 GND DIN 8 4 LDAC SCLK 5 CLR SYNC AVDD 1 mF 150 nF AVDD 1 mF Figure 94. Typical Connections for Operating the DAC756x/DAC816x/DAC856x Internal Reference Supply Voltage The internal reference features an extremely low dropout voltage. It can be operated with a supply of only 5 mV above the reference output voltage in an unloaded condition. For loaded conditions, refer to the Load Regulation section. The stability of the internal reference with variations in supply voltage (line regulation, DC PSRR) is also exceptional. Within the specified supply voltage range of 2.7 V to 5.5 V, the variation at VREFIN/VREFOUT is typically 50 µV/V; see Figure 7. Temperature Drift The internal reference is designed to exhibit minimal drift error, defined as the change in reference output voltage over varying temperature. The drift is calculated using the box method described by Equation 3: æ VREF _ MAX - VREF _ MIN ö 6 Drift Error = çç ÷÷ ´ 10 (ppm / °C ) ´ V T REF RANGE è ø (3) where: VREF_MAX = maximum reference voltage observed within temperature range TRANGE. VREF_MIN = minimum reference voltage observed within temperature range TRANGE. VREF = 2.5 V, target value for reference output voltage. TRANGE = the characterized range from –40°C to 125°C (165°C range) The internal reference features an exceptional typical drift coefficient of 4 ppm/°C from –40°C to 125°C. Characterizing a large number of units, a maximum drift coefficient of 10 ppm/°C is observed. Temperature drift results are summarized in Figure 3. Noise Performance Typical 0.1-Hz to 10-Hz voltage noise and noise spectral density performance are listed in the Electrical Characteristics. Additional filtering can be used to improve output noise levels, although care should be taken to ensure the output impedance does not degrade the AC performance. The output noise spectrum at the VREFIN/VREFOUT pin, both unloaded and with an external 4.7-µF load capacitor, is shown in Figure 6. Internal reference noise impacts the DAC output noise when the internal reference is used. 38 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 Load Regulation Load regulation is defined as the change in reference output voltage as a result of changes in load current. The load regulation of the internal reference is measured using force and sense contacts as shown in Figure 95. The force and sense lines reduce the impact of contact and trace resistance, resulting in accurate measurement of the load regulation contributed solely by the internal reference. Measurement results are shown in Figure 4. Force and sense lines should be used for applications that require improved load regulation. Output Pin Contact and Trace Resistance VOUT Force Line IL Sense Line Meter Load Figure 95. Accurate Load Regulation of the DAC756x/DAC816x/DAC856x Internal Reference Long-Term Stability Long-term stability/aging refers to the change of the output voltage of a reference over a period of months or years. This effect lessens as time progresses. The typical drift value for the internal reference is listed in the Electrical Charateristics and measurement results are shown in Figure 5. This parameter is characterized by powering up multiple devices and measuring them at regular intervals. Thermal Hysteresis Thermal hysteresis for a reference is defined as the change in output voltage after operating the device at 25°C, cycling the device through the operating temperature range, and returning to 25°C. Hysteresis is expressed by Equation 4: é VREF_PRE - VREF_POST ù 6 VHYST = ê ú ´ 10 (ppm/°C) V REF_NOM ëê ûú (4) Where: VHYST = thermal hysteresis. VREF_PRE = output voltage measured at 25°C pre-temperature cycling. VREF_POST = output voltage measured after the device cycles through the temperature range of –40°C to aaa 125°C, and returns to 25°C. VREF_NOM = 2.5 V, target value for reference output voltage. DAC NOISE PERFORMANCE Output noise spectral density at the VOUT-n pin versus frequency is depicted in Figure 45 and Figure 46 for fullscale, mid-scale, and zero-scale input codes. The typical noise density for mid-scale code is 90 nV/√Hz at 1 kHz. High-frequency noise can be improved by filtering the reference noise. Integrated output noise between 0.1 Hz and 10 Hz is close to 2.5 µVPP (mid-scale), as shown in Figure 47. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 39 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com UP TO ±15-V BIPOLAR OUTPUT USING THE DAC8562 The DAC8562 is designed to be operate from a single power supply providing a maximum output range of AVDD volts. However, the DAC can be placed in the configuration shown in Figure 96 in order to be designed into bipolar systems. Depending on the ratio of the resistor values, the output of the circuit can range anywhere from ±5 V to ±15 V. The design example below shows that the DAC is configured to have its internal reference enabled and the DAC8562 internal gain set to two, however, an external 2.5-V reference could also be used (with DAC8562 internal gain set to two). R G´R 5.5 V VREFOUT 18 V R + DAC8562 VOUT – OPA140 G´R –18 V Figure 96. Bipolar Output Range Circuit Using DAC8562 The transfer function shown in Equation 5 can be used to calculate the output voltage as a function of the DAC code, reference voltage and resistor ratio: DIN æ ö - 1÷ VOUT = G × VREFOUT ç 2 × 65,536 è ø (5) where: DIN = decimal equivalent of the binary code that is loaded to the DAC register, ranging from 0 to 65,535 for aaa DAC8562 (16 bit). VREFOUT = reference output voltage with the internal reference enabled from the DAC VREFIN/VREFOUT pin G = ratio of the resistors An example configuration to generate a ±10-V output range is shown below in Equation 6 with G = 4 and VREFOUT = 2.5 V: DIN VOUT = 20 × - 10 V 65,536 (6) In this example, the range is set to ±10 V by using a resistor ratio of four, VREFOUT of 2.5 V, and DAC8562 internal gain of two. The resistor sizes must be selected keeping in mind the current sink/source capability of the DAC8562 internal reference. Using larger resistor values, for example R = 10 kΩ or larger is recommended. The op amp is selectable depending on the requirements of the system. The DAC8562EVM and DAC7562EVM boards have the option to evaluate the bipolar output application by installing the components on the pre-placed footprints. For more information see either the DAC8562EVM or DAC7562EVM product folder. 40 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 PLC ANALOG OUTPUT MODULE USING THE DAC8562 The DAC8562 can be mated with one of TI's 0- to 20-mA voltage-to-current transmitters to create a low-cost, programmable current source for use in PLC applications. One specific example includes combining the DAC8562 with the XTR111 to create a voltage-to-current solution. The DAC output voltage generates a current, ISET, which is determined by the value of the external resistor, RSET. This current is internally amplified by 10 and output at the IS node. A p-channel MOSFET Q1 can be added in an application where a wide compliance voltage is required, for example, when using a high impedance load. The optional PNP transistor, Q2, along with the R4 resistor provides external current limiting in a case where the external FET is forced to low impedance. Additionally, resistors R2 and R3 can be used to scale the 3-V internal regulator to a desired voltage to power the DAC. Figure 97 shows a working 0- to 20-mA solution using one DAC8562 channel and a ±10-V voltage output using the other DAC8562 channel. For more information on the ±10-V voltage output circuit see the UP TO ±15-V BIPOLAR OUTPUT USING THE DAC8562 application. 24 V 5.5 V C1 470 nF REGF VOUTA 0 to 5 V IS R2 2.5 kΩ Q2 REGS AVDD VSP R1 2.5 kΩ XTR111 R3 3 kΩ Q1 VG VIN R5 15 Ω SET DAC8562 VOUTB VREFOUT R4 15 Ω C2 10 nF RSET 2.5 kΩ 0 to 5 V GND IOUT 0- to 20-mA Output 18 V R6 10 kΩ R7 40 kΩ + OPA140 – VOUT ±10-V Output –18 V R8 10 kΩ R9 40 kΩ Figure 97. 0- to 20-mA and ±10-V Outputs Using DAC8562 Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 41 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com MICROPROCESSOR INTERFACING DAC756x/DAC816x/DAC856x to an MSP430 USI Interface Figure 98 shows a serial interface between the DAC756x, DAC816x, or DAC856x and a typical MSP430 USI port such as the one found on the MSP430F2013. The port is configured in SPI master mode by setting bits 3, 5, 6, and 7 in USICTL0. The USI counter interrupt is set in USICTL1 to provide an efficient means of SPI communication with minimal software overhead. The serial clock polarity, source, and speed are controlled by settings in the USI clock control register (USICKCTL). The SYNC signal is derived from a bit-programmable pin on port 1; in this case, port line P1.4 is used. When data are to be transmitted to the DAC756x, DAC816x, or DAC856x, P1.4 is taken low. The USI transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P1.4 is left low after the first eight bits are transmitted; then, a second write cycle is initiated to transmit the second byte of data. P1.4 is taken high following the completion of the third write cycle. MSP430F2013 DAC P1.4/GPIO SYNC P1.5/SCLK SCLK P1.6/SDO DIN NOTE: Additional pins omitted for clarity. Figure 98. DAC756x/DAC816x/DAC856x to MSP430 Interface DAC756x/DAC816x/DAC856x to a TMS320 McBSP Interface Figure 99 shows an interface between the DAC756x, DAC816x, or DAC856x and any TMS320 series DSP from Texas Instruments with a multi-channel buffered serial port (McBSP). Serial data are shifted out on the rising edge of the serial clock and are clocked into the DAC756x, DAC816x, or DAC856x on the falling edge of the SCLK signal. TMS320F28062 DAC MFSxA SYNC MCLKxA SCLK MDxA DIN NOTE: Additional pins omitted for clarity. Figure 99. DAC756x/DAC816x/DAC856x to TMS320 McBSP Interface DAC756x/DAC816x/DAC856x to an OMAP-L1x Processor Figure 100 shows a serial interface between the DAC756x/DAC816x/DAC856x and the OMAP-L138. The transmit clock CLKx0 of the L138 drives SCLK of the DAC756x, DAC816x, or DAC856x, and the data transmit (Dx0) output drives the serial data line of the DAC. The SYNC signal is derived from the frame sync transmit (FSx0) line, similar to the TMS320 interface. DAC OMAP-L138 FSx0 SYNC CLKx0 SCLK Dx0 DIN NOTE: Additional pins omitted for clarity. Figure 100. DAC756x/DAC816x/DAC856x to OMAP-L1x Processor 42 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC756x, DAC816x, and DAC856x offer single-supply operation, and are often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output. As a result of the single ground pin of the DAC756x, DAC816x, and DAC856x, all return currents (including digital and analog return currents for the DAC) must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. The power applied to AVDD should be well-regulated and low noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, AVDD should be connected to a power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a 1-µF to 10-µF capacitor and 0.1-µF bypass capacitor are strongly recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a pi filter made up of inductors and capacitors – all designed to essentially low-pass filter the supply and remove the high-frequency noise. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 43 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com PARAMETER DEFINITIONS With the increased complexity of many different specifications listed in product data sheets, this section summarizes selected specifications related to digital-to-analog converters. STATIC PERFORMANCE Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity (INL). These are dc specifications and provide information on the accuracy of the DAC. They are most important in applications where the signal changes slowly and accuracy is required. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is defined as the maximum deviation of the real LSB step from the ideal 1 LSB step. Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. If the DNL is less than 1 LSB, the DAC is said to be monotonic. Full-Scale Error Full-scale error is defined as the deviation of the real full-scale output voltage from the ideal output voltage while the DAC register is loaded with the full-scale code (0xFFFF). Ideally, the output should be VREF – 1 LSB or 2 × VREF – 1 LSB, depending on the DAC voltage gain. The full-scale error is expressed in percent of full-scale range (% FSR). Full-Scale Error Drift Full-scale error drift is defined as the change in full-scale error with a change in temperature. Full-scale error drift is expressed in units of ppm of FSR/°C. Full-Scale Range (FSR) Full-scale range (FSR) is the difference between the maximum and minimum analog output values that the DAC is specified to provide; typically, the maximum and minimum values are also specified. For an n-bit DAC, these values are usually given as the values matching with code 0 and 2n – 1. Gain Error Gain error is defined as the deviation in the slope of the real DAC transfer characteristic from the ideal transfer function. Gain error is expressed as a percentage of full-scale range (% FSR). Gain Temperature Coefficient The gain temperature coefficient is defined as the change in gain error with changes in temperature. The gain temperature coefficient is expressed in ppm of FSR/°C. Least-Significant Bit (LSB) The least significant bit (LSB) is defined as the smallest value in a binary coded system. The value of the LSB can be calculated by dividing the full-scale output voltage by 2n, where n is the resolution of the converter. Monotonicity Monotonicity is defined as a slope whose sign does not change. If a DAC is monotonic, the output changes in the same direction or remains constant for each step increase (or decrease) in the input code. Most-Significant Bit (MSB) The most significant bit (MSB) is defined as the largest value in a binary coded system. The value of the MSB can be calculated by dividing the full-scale output voltage by 2. Its value is one-half of full-scale. Offset Error The offset error is defined as the difference between actual output voltage and the ideal output voltage in the linear region of the transfer function. This difference is calculated by using a straight line defined by two codes (code 512 and code 65,024). Because the offset error is defined by a straight line, it can have a negative or positive value. Offset error is measured in mV. Offset Error Drift Offset error drift is defined as the change in offset error with a change in temperature. Offset error drift is expressed in µV/°C. Power-Supply Rejection Ratio (PSRR) Power-supply rejection ratio (PSRR) is defined as the ratio of change in output voltage to a change in supply voltage for a full-scale output of the DAC. The PSRR of a device indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is measured in decibels (dB). 44 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy or integral nonlinearity (INL) is defined as the maximum deviation between the real transfer function and a straight line passing through the endpoints of the ideal DAC transfer function. INL is measured in LSBs. Resolution Generally, the DAC resolution can be expressed in different forms. Specifications such as IEC 60748-4 recognize the numerical, analog, and relative resolution. The numerical resolution is defined as the number of digits in the chosen numbering system necessary to express the total number of steps of the transfer characteristic, where a step represents both a digital input code and the corresponding discrete analogue output value. The most commonly-used definition of resolution provided in data sheets is the numerical resolution expressed in bits. Zero-Code Error The zero-code error is defined as the DAC output voltage, when all 0s are loaded into the DAC register. Zerocode error is a measure of the difference between actual output voltage and ideal output voltage (0 V). It is expressed in mV. It is primarily caused by offsets in the output amplifier. Zero-Code Error Drift Zero-code error drift is defined as the change in zero-code error with a change in temperature. Zero-code error drift is expressed in µV/°C. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 45 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 www.ti.com DYNAMIC PERFORMANCE Dynamic performance parameters are specifications such as settling time or slew rate, which are important in applications where the signal rapidly changes and/or high frequency signals are present. Channel-to-Channel Crosstalk Crosstalk in a multi-channel DAC is defined as a glitch coupled onto the output of a channel (victim) when the output of an adjacent channel (agressor) has a full-scale transition. It is calculated as the total area under the measured glitch on the victim channel at mid-scale code. It is expressed in nV-s. Channel-to-Channel DC Crosstalk Channel-to-channel dc crosstalk is defined as the dc change in the output level of one DAC channel in response to a change in the output of another DAC channel. It is measured with a full-scale output change on one DAC channel while monitoring another DAC channel at mid-scale. It is expressed in LSB. Code Change/Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nanovolt-seconds (nV-s), and is measured when the digital input code is changed by 1 LSB at the major carry transition. DAC Output Noise DAC output noise is defined as any voltage deviation of DAC output from the desired value (within a particular frequency band). It is measured with a DAC channel kept at mid-scale while filtering the output voltage within a band of 0.1 Hz to 10 Hz and measuring its amplitude peaks. It is expressed in terms of peak-to-peak voltage (VPP). DAC Output Noise Density Output noise density is defined as internally-generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by setting the DAC to mid-scale and measuring noise at the output. Digital Feedthrough Digital feedthrough is defined as the impulse seen at the output of the DAC from the digital inputs of the DAC. It is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus; that is, from all 0s to all 1s and vice versa. Output Voltage Settling Time Settling time is the total time (including slew time) for the DAC output to settle within an error band around its final value after a change in input. Settling times are specified to within ±0.024% FSR (or whatever value is stated) of full-scale range. Slew Rate The output slew rate (SR) of an amplifier or other electronic circuit is defined as the maximum rate of change of the output voltage for all possible input signals. SR = max DVOUT(t) Dt (7) Where ΔVOUT(t) is the output produced by the amplifier as a function of time t. 46 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719D – AUGUST 2010 – REVISED AUGUST 2012 REVISION HISTORY Changes from Revision C (June 2011, first official release) to Revision D Page • Replaced text "QFN" with "SON" (name change only, package/orderable did not change) ................................................ 1 • Typical power-down current consumption changed from 10 nA to 550 nA. ......................................................................... 1 • Changed power requirements specifications ........................................................................................................................ 5 • Power-down current vs Temperature typical characteristic plot updated, AVDD = 5.5 V .................................................... 15 • Power-down current vs Power-supply voltage typical characteristic plot updated ............................................................. 15 • Power-down current vs Temperature typical characteristic plot updated, AVDD = 2.7 V .................................................... 23 • Added Power-On Reset (POR) Levels section ................................................................................................................... 30 Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 47 PACKAGE OPTION ADDENDUM www.ti.com 25-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DAC7562SDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7562 DAC7562SDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7562 DAC7562SDSCR ACTIVE WSON DSC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7562 DAC7562SDSCT ACTIVE WSON DSC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7562 DAC7563SDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7563 DAC7563SDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7563 DAC7563SDSCR ACTIVE WSON DSC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7563 DAC7563SDSCT ACTIVE WSON DSC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7563 DAC8162SDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8162 DAC8162SDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8162 DAC8162SDSCR ACTIVE WSON DSC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8162 DAC8162SDSCT ACTIVE WSON DSC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8162 DAC8163SDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8163 DAC8163SDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8163 DAC8163SDSCR ACTIVE WSON DSC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8163 DAC8163SDSCT ACTIVE WSON DSC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8163 DAC8562SDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8562 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 25-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DAC8562SDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8562 DAC8562SDSCR ACTIVE WSON DSC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8562 DAC8562SDSCT ACTIVE WSON DSC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8562 DAC8563SDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8563 DAC8563SDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8563 DAC8563SDSCR ACTIVE WSON DSC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8563 DAC8563SDSCT ACTIVE WSON DSC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8563 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DAC8562 : • Automotive: DAC8562-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DAC7562SDGSR VSSOP DGS 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC7562SDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC7562SDSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC7562SDSCT WSON DSC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC7563SDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC7563SDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC7563SDSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC7563SDSCT WSON DSC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC8162SDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC8162SDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC8162SDSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC8162SDSCT WSON DSC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC8163SDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC8163SDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC8163SDSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC8163SDSCT WSON DSC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC8562SDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC8562SDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8562SDSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC8562SDSCT WSON DSC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC8563SDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC8563SDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 DAC8563SDSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC8563SDSCT WSON DSC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7562SDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 DAC7562SDGST VSSOP DGS 10 250 195.0 200.0 45.0 DAC7562SDSCR WSON DSC 10 3000 367.0 367.0 35.0 DAC7562SDSCT WSON DSC 10 250 210.0 185.0 35.0 DAC7563SDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 DAC7563SDGST VSSOP DGS 10 250 220.0 205.0 50.0 DAC7563SDSCR WSON DSC 10 3000 367.0 367.0 35.0 DAC7563SDSCT WSON DSC 10 250 210.0 185.0 35.0 DAC8162SDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 DAC8162SDGST VSSOP DGS 10 250 220.0 205.0 50.0 DAC8162SDSCR WSON DSC 10 3000 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8162SDSCT WSON DSC 10 250 210.0 185.0 35.0 DAC8163SDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 DAC8163SDGST VSSOP DGS 10 250 220.0 205.0 50.0 DAC8163SDSCR WSON DSC 10 3000 367.0 367.0 35.0 DAC8163SDSCT WSON DSC 10 250 210.0 185.0 35.0 DAC8562SDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 DAC8562SDGST VSSOP DGS 10 250 220.0 205.0 50.0 DAC8562SDSCR WSON DSC 10 3000 367.0 367.0 35.0 DAC8562SDSCT WSON DSC 10 250 210.0 185.0 35.0 DAC8563SDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 DAC8563SDGST VSSOP DGS 10 250 220.0 205.0 50.0 DAC8563SDSCR WSON DSC 10 3000 367.0 367.0 35.0 DAC8563SDSCT WSON DSC 10 250 210.0 185.0 35.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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