ATMEL ATSAM4SD32BA-AU Arm-based flash mcu Datasheet

Features
• Core
•
•
•
•
•
•
•
– ARM® Cortex®-M4 with a 2Kbytes cache running at up to 120 MHz
– Memory Protection Unit (MPU)
– DSP Instruction Set
– Thumb®-2 instruction set
Pin-to-pin compatible with SAM3N, SAM3S products (64- and 100- pin versions) and
SAM7S legacy products (64-pin version)
Memories
– Up to 2048 Kbytes embedded Flash with optional dual bank and cache memory
– Up to 160 Kbytes embedded SRAM
– 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support
System
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
Detection and optional low-power 32.768 kHz for RTC or device clock
– RTC with Gregorian and Persian Calendar mode, waveform generation in lowpower modes
– RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
frequency for device startup. In-application trimming access for frequency
adjustment
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– Two PLLs up to 240 MHz for device clock and for USB
– Temperature Sensor
– Up to 22 Peripheral DMA (PDC) Channels
Low Power Modes
– Sleep and Backup Modes, down to 1 µA in Backup Mode
– Ultra low-power RTC
Peripherals
– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip
Transceiver
– Up to 2 USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode
– Two 2-wire UARTs
– Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller
(I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)
– 2 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM
mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper
Motor
– 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time
Generator Counter for Motor Control
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 16-channel, 1Msps ADC with differential input mode and programmable gain
stage and auto calibration
– One 2-channel 12-bit 1Msps DAC
– One Analog Comparator with flexible input selection, Selectable input hysteresis
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
– Write Protected Registers
I/O
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel
Capture Mode
Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/ 100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm/
100-ball VFBGA, 7 x 7 mm, pitch 0.65 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/ 64-pad QFN 9x9 mm, pitch 0.5 mm
AT91SAM
ARM-based
Flash MCU
SAM4S Series
Preliminary
Summary
NOTE: This is a summary document.
The complete document is currently not
available. For more information, please
contact your local Atmel sales office.
11100BS–ATARM–31-Jul-12
1.
Description
The Atmel SAM4S series is a member of a family of Flash microcontrollers based on the high
performance 32-bit ARM Cortex-M4 RISC processor. It operates at a maximum speed of
120 MHz and features up to 2048 Kbytes of Flash, with optional dual bank implementation and
cache memory, and up to 160 Kbytes of SRAM. The peripheral set includes a Full Speed USB
Device port with embedded transceiver, a High Speed MCI for SDIO/SD/MMC, an External Bus
Interface featuring a Static Memory Controller providing connection to SRAM, PSRAM, NOR
Flash, LCD Module and NAND Flash, 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, an I2S, as well
as 1 PWM timer, 2x three channel general-purpose 16-bit timers (with stepper motor and
quadrature decoder logic support), an RTC, a 12-bit ADC, a 12-bit DAC and an analog
comparator.
The SAM4S series is ready for capacitive touch thanks to the QTouch® library, offering an easy
way to implement buttons, wheels and sliders.
The SAM4S device is a medium range general purpose microcontroller with the best ratio in
terms of reduced power consumption, processing power and peripheral set. This enables the
SAM4S to sustain a wide range of applications including consumer, industrial control, and PC
peripherals.
It operates from 1.62V to 3.6V.
The SAM4S series is pin-to-pin compatible with the SAM3N, SAM3S series (64- and 100-pin
versions) and SAM7S legacy series (64-pin versions).
2
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
1.1
Configuration Summary
The SAM4S series devices differ in memory size, package and features. Table 1-1 summarizes
the configurations of the device family.
Table 1-1.
Feature
Configuration Summary
SAM4SD32C
SAM4SD32B
SAM4SD16C
SAM4SD16B
SAM4SA16C
SAM4SA16B
SAM4S16C
SAM4S16B
SAM4S8C
SAM4S8B
Flash
2 x 1024
Kbytes
2 x 1024
Kbytes
2 x 512
Kbytes
2 x 512
Kbytes
1024 Kbytes
1024
Kbytes
1024
Kbytes
1024
Kbytes
512 Kbytes
512
Kbytes
SRAM
160 Kbytes
160 Kbytes
160 Kbytes
160 Kbytes
160 Kbytes
160 Kbytes
128 Kbytes
128
Kbytes
128 Kbytes
128
Kbytes
HCACHE
2Kbytes
2Kbytes
2Kbytes
2Kbytes
2Kbytes
2Kbytes
-
-
-
-
Package
LQFP 100
TFBGA 100
VFBGA 100
LQFP 64
QFN 64
LQFP 100
TFBGA 100
VFBGA 100
LQFP 64
QFN 64
LQFP 100
TFBGA 100
VFBGA 100
LQFP 64
QFN 64
LQFP 100
TFBGA 100
VFBGA 100
LQFP 64
LFBGA 64
LQFP 100
TFBGA 100
VFBGA 100
LQFP 64
QFN 64
Number
of PIOs
79
47
79
47
79
47
79
47
79
47
8-bit data,
4chip selects,
24-bit address
-
8-bit data,
4chip selects,
24-bit address
-
8-bit data,
4chip selects,
24-bit address
-
8-bit data,
4chip selects,
24-bit address
-
8-bit data,
4chip selects,
24-bit address
-
6
4
6
4
6
4
6
4
6
6
12-bit
ADC
16 ch.(1)
11 ch.(1)
16 ch.(1)
11 ch.(1)
16 ch.(1)
11 ch.(1)
16 ch.(1)
11 ch.(1)
16 ch.(1)
11 ch.(1)
12-bit
DAC
2 ch.
2 ch.
2 ch.
2 ch.
2 ch.
2 ch.
2 ch.
2 ch.
2 ch.
2 ch.
6
3
6
3
6
3
6
3
6
3
22
22
22
22
22
22
22
22
22
22
2/2(2)
2/2(2)
2/2(2)
2/2(2)
2/2(2)
2/2(2)
2/2(2)
2/2(2)
2/2(2)
2/2(2)
1 port
4 bits
1 port
4 bits
1 port
4 bits
1 port
4 bits
1 port
4 bits
1 port
4 bits
1 port
4 bits
1 port
4 bits
1 port
4 bits
1 port
4 bits
External
Bus
Interface
Central
DMA
Timer
Counter
Channels
PDC
Channels
USART/
UART
HSMCI
Notes:
1. One channel is reserved for internal temperature sensor.
2. Full Modem support on USART1.
3
11100BS–ATARM–31-Jul-12
2. Block Diagram
TST
Voltage
Regulator
PCK0-PCK2
PLLA
PLLB
PMC
RC Osc
12/8/4 MHz
XIN
XOUT
O
IN
VD
D
JT
AG
System Controller
VD
D
SE
L
UT
SAM4S16/S8 Series 100-pin version Block Diagram
TD
TDI
TMO
TC S/S
K/ WD
SW IO
CL
K
Figure 2-1.
Flash
Unique
Identifier
JTAG & Serial Wire
User
Signature
In-Circuit Emulator
3-20 MHz
Osc
SUPC
24-Bit
Cortex M-4 Processor SysTick Counter
Fmax 120 MHz
DSP
N
V
I
C
SRAM
ROM
128 Kbytes 16 Kbytes
FLASH
1024 Kbytes
512 Kbytes
MPU
XIN32
XOUT32
Osc 32 kHz
ERASE
RC 32 kHz
VDDIO
8 GPBREG
I/D
S
4-layer AHB Bus Matrix Fmax 120 MHz
VDDCORE
RTT
VDDPLL
RTCOUT0
POR
RSTC
WDT
Peripheral
Bridge
SM
2668 USB 2.0
Bytes
Full
FIFO Speed
PIOA / PIOB / PIOC
TWCK0
TWD0
TWCK1
TWD1
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
TWI0
PDC
TWI1
PDC
UART0
PDC
UART1
DDP
DDM
External Bus
Interface
NAND Flash
Logic
PDC
PIO
NRST
Transceiver
RTC
RTCOUT1
Static Memory
Controller
USART0
PDC
PDC
PIODC[7:0]
PIODCEN1
PIODCEN2
PIODCCLK
PIO
USART1
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
TF
TK
TD
RD
RK
RF
PDC
PDC
TCLK[0:2]
Timer Counter A
TIOA[0:2]
TIOB[0:2]
TC[0..2]
SPI
PDC
SSC
TCLK[3:5]
Timer Counter B
TIOA[3:5]
TIOB[3:5]
PDC
PWML[0:3]
PWMFI0
ADTRG
AD[0..14]
ADVREF
DAC0
DAC1
DATRG
4
MCCK
MCCDA
MCDA[0..3]
TC[3..5]
High Speed MCI
PWMH[0:3]
PWM
PDC
Temp. Sensor
12-bit ADC
Analog
Comparator
D[7:0]
A[0:23]
A21/NANDALE
A22/NANDCLE
NCS0
NCS1
NCS2
NCS3
NRD
NWE
NANDOE
NANDWE
NWAIT
ADVREF
ADC Ch.
CRC Unit
PDC
12-bit DAC
PDC
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
TST
Voltage
Regulator
PCK0-PCK2
PLLA
PLLB
PMC
RC Osc
12/8/4 MHz
O
UT
IN
VD
D
System Controller
VD
D
JT
AG
SE
L
SAM4S16/S8 Series 64-pin version Block Diagram
TD
TDI
TMO
TC S/S
K/ WD
SW IO
CL
K
Figure 2-2.
Flash
Unique
Identifier
JTAG & Serial Wire
User
Signature
In-Circuit Emulator
XIN
XOUT
3-20 MHz
Osc
XIN32
XOUT32
Osc 32 kHz
ERASE
RC 32 kHz
VDDIO
8 GPBREG
SUPC
24-Bit
Cortex M-4 Processor SysTick Counter
Fmax 120 MHz
DSP
N
V
I
C
FLASH
1024 Kbytes
512 Kbytes
SRAM
128 Kbytes
ROM
16 Kbytes
MPU
I/D
S
4-layer AHB Bus Matrix Fmax 120 MHz
VDDCORE
RTT
VDDPLL
RTCOUT0
POR
RSTC
NRST
WDT
Peripheral
Bridge
SM
2668 USB 2.0
Bytes
Full
FIFO Speed
PIOA / PIOB
TWCK0
TWD0
TWI0
TWCK1
TWD1
TWI1
URXD0
UTXD0
UART0
URXD1
UTXD1
UART1
RXD0
TXD0
SCK0
RTS0
CTS0
DDP
DDM
PDC
PDC
PDC
PDC
PIODC[7:0]
PIODCEN1
PIODCEN2
PIODCCLK
PIO
PDC
USART0
PDC
PDC
SPI
PIO
USART1
PIO
RXD1
TXD1
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
Transceiver
RTC
RTCOUT1
PDC
PDC
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
ADTRG
AD[0..9]
SSC
TC[0..2]
PDC
PWM
PDC
MCCK
MCCDA
MCDA[0..3]
High Speed MCI
Temp. Sensor
12-bit ADC
ADVREF
DAC0
DAC1
DATRG
TF
TK
TD
RD
RK
RF
Timer Counter A
PWMH[0:3]
PWML[0:3]
PWMFI0
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
PDC
Analog
Comparator
PDC
CRC Unit
12-bit DAC
ADVREF
ADC Ch.
5
11100BS–ATARM–31-Jul-12
VD
VD
DI
N
TST
DO
L
JTA
G
SE
TD
TDI
TMO
TC S/S
K/ W
SW DI
CL O
K
UT
SAM4SD32/SD16/SA16 100-pin version Block Diagram
RT
C
RT OU
CO T0
UT
1
Figure 2-3.
Voltage
Regulator
PCK0-PCK2
PLLA
PLLB
PMC
JTAG & Serial Wire
RC
12/8/4 M
In-Circuit Emulator
24-Bit
N
Cortex-M4 Processor SysTick Counter V
Fmax 120 MHz
I
C
DSP
3-20 MHz
Osc.
XIN
XOUT
Flash
Unique
Identifier
SUPC
MPU
XIN32
XOUT32
OSC 32k
ERASE
RC 32k
I
VDDIO
RTT
RTC
VDDPLL
POR
SRAM
160 KBytes
D
4-layer AHB Bus Matrix Fmax 120 MHz
Peripheral
Bridge
SM
2668 USB 2.0
Bytes
Full
FIFO
Speed
PIOA / PIOB / PIOC
TWI0
PDC
TWI1
PDC
UART0
PDC
UART1
PDC
PDC
USART1
PDC
TIOA[0:2]
TIOB[0:2]
TC[0..2]
TCLK[3:5]
Timer Counter B
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
TF
TK
TD
RD
RK
RF
PDC
SPI
PDC
TC[3..5]
SSC
PWMH[0:3]
PWML[0:3]
PWMFI0
ADTRG
AD[0..14]
ADVREF
DAC0
DAC1
DATRG
6
D[7:0]
A[0:23]
A21/NANDALE
A22/NANDCLE
NCS0
NCS1
NCS2
NCS3
NRD
NWE
NANDOE
NANDWE
NWAIT
PIODC[7:0]
PIODCEN1
PIODCEN2
PIODCCLK
PIO
Timer Counter A
TIOB[3:5]
NAND Flash
Logic
Static Memory
Controller
TCLK[0:2]
TIOA[3:5]
External Bus
Interface
PDC
USART0
DDP
DDM
PIO
WDT
Transceiver
RSTC
NRST
TWCK0
TWD0
TWCK1
TWD1
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
ROM
16 KBytes
CMCC
(2 KB cache)
8 GPBREG
VDDCORE
FLASH
2*1024 KBytes
2*512 KBytes
1024 KBytes
PWM
PDC
PDC
Temp. Sensor
ADC
PDC
DAC
PDC
MCCK
MCCDA
MCDA[0..3]
High Speed MCI
Analog
Comparator
ADC
DAC
Temp Sensor
ADVREF
CRC Unit
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
PMC
RC Osc
12/8/4 MHz
XIN
XOUT
JTAG & Serial Wire
UT
O
IN
Flash
Unique
Identifier
In-Circuit Emulator
3-20 MHz
Osc
Cortex M-4 Processor
Fmax 120 MHz
SUPC
24-Bit
N
SysTick Counter V
I
DSP
C
MPU
XIN32
XOUT32
Osc 32 kHz
ERASE
RC 32 kHz
I
VDDCORE
RTT
VDDPLL
RTCOUT0
POR
FLASH
2*1024 KBytes
2*512 KBytes
1024 KBytes
SRAM
160 KBytes
D
4-layer AHB Bus Matrix Fmax 120 MHz
RTC
RTCOUT1
RSTC
NRST
WDT
Peripheral
Bridge
SM
2668 USB 2.0
Bytes
Full
FIFO Speed
PIOA / PIOB
TWCK0
TWD0
TWI0
TWCK1
TWD1
TWI1
URXD0
UTXD0
UART0
URXD1
UTXD1
UART1
RXD0
TXD0
SCK0
RTS0
CTS0
DDP
DDM
PDC
PDC
PDC
PDC
PIODC[7:0]
PIODCEN1
PIODCEN2
PIODCCLK
PIO
PDC
USART0
PDC
PDC
SPI
PIO
USART1
PIO
RXD1
TXD1
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
ROM
16 KBytes
CMCC
(2 KB cache)
8 GPBREG
VDDIO
VD
D
Voltage
Regulator
PLLA
PLLB
VD
D
JT
AG
System Controller
PCK0-PCK2
Transceiver
TST
SE
L
SAM4SD32/SD16/SA16 64-pin version Block Diagram
TD
TDI
TMO
TC S/S
K/ WD
SW IO
CL
K
Figure 2-4.
PDC
PDC
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
ADTRG
AD[0..9]
SSC
TC[0..2]
PDC
PWM
PDC
MCCK
MCCDA
MCDA[0..3]
High Speed MCI
Temp. Sensor
12-bit ADC
ADVREF
DAC0
DAC1
DATRG
TF
TK
TD
RD
RK
RF
Timer Counter A
PWMH[0:3]
PWML[0:3]
PWMFI0
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
PDC
Analog
Comparator
PDC
CRC Unit
12-bit DAC
ADVREF
ADC Ch.
7
11100BS–ATARM–31-Jul-12
3. Signal Description
Table 3-1 gives details on signal names classified by peripheral.
Table 3-1.
Signal Description List
Signal Name
Function
Type
Active
Level
Voltage
reference
Comments
Power Supplies
VDDIO
Peripherals I/O Lines and USB transceiver
Power Supply
Power
1.62V to 3.6V
VDDIN
Voltage Regulator Input, ADC, DAC and
Analog Comparator Power Supply
Power
1.62V to 3.6V(4)
VDDOUT
Voltage Regulator Output
Power
1.2V Output
VDDPLL
Oscillator and PLL Power Supply
Power
1.08 V to 1.32V
VDDCORE
Power the core, the embedded memories
and the peripherals
Power
GND
Ground
Ground
1.08V to 1.32V
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
XOUT32
Slow Clock Oscillator Output
PCK0 - PCK2
Input
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
Output
Input
Output
Programmable Clock Output
VDDIO
Reset State:
- PIO Input
- Internal Pull-up enabled
- Schmitt Trigger enabled(1)
Output
Real Time Clock
RTCOUT0
Programmable RTC waveform output
Output
RTCOUT1
Programmable RTC waveform output
Output
VDDIO
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
Serial Wire/JTAG Debug Port - SWJ-DP
TCK/SWCLK
Test Clock/Serial Wire Clock
Input
TDI
Test Data In
Input
TDO/TRACESWO
Test Data Out / Trace Asynchronous Data
Out
Output
TMS/SWDIO
Test Mode Select /Serial Wire Input/Output
Input / I/O
JTAGSEL
JTAG Selection
8
Input
VDDIO
High
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled(5)
- Schmitt Trigger enabled(1)
Permanent Internal
pull-down
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Voltage
reference
Comments
Flash Memory
Reset State:
ERASE
Flash and NVM Configuration Bits Erase
Command
Input
High
VDDIO
- Erase Input
- Internal pull-down enabled
- Schmitt Trigger enabled(1)
Reset/Test
NRST
Synchronous Microcontroller Reset
I/O
Low
VDDIO
TST
Test Select
Permanent Internal
pull-up
Permanent Internal
pull-down
Input
Universal Asynchronous Receiver Transceiver - UARTx
URXDx
UART Receive Data
Input
UTXDx
UART Transmit Data
Output
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31
Parallel IO Controller A
I/O
PB0 - PB14
Parallel IO Controller B
I/O
PC0 - PC31
Parallel IO Controller C
I/O
VDDIO
Reset State:
- PIO or System IOs(2)
- Internal pull-up enabled
- Schmitt Trigger enabled(1)
PIO Controller - Parallel Capture Mode
PIODC0-PIODC7
Parallel Capture Mode Data
Input
PIODCCLK
Parallel Capture Mode Clock
Input
PIODCEN1-2
Parallel Capture Mode Enable
Input
VDDIO
External Bus Interface
D0 - D7
Data Bus
I/O
A0 - A23
Address Bus
NWAIT
External Wait Signal
Output
Input
Low
Static Memory Controller - SMC
NCS0 - NCS3
Chip Select Lines
Output
Low
NRD
Read Signal
Output
Low
NWE
Write Enable
Output
Low
NAND Flash Logic
NANDOE
NAND Flash Output Enable
Output
Low
NANDWE
NAND Flash Write Enable
Output
Low
High Speed Multimedia Card Interface - HSMCI
MCCK
Multimedia Card Clock
I/O
MCCDA
Multimedia Card Slot A Command
I/O
MCDA0 - MCDA3
Multimedia Card Slot A Data
I/O
9
11100BS–ATARM–31-Jul-12
Table 3-1.
Signal Name
Signal Description List (Continued)
Function
Type
Active
Level
Voltage
reference
Comments
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
USARTx Serial Clock
I/O
TXDx
USARTx Transmit Data
I/O
RXDx
USARTx Receive Data
Input
RTSx
USARTx Request To Send
CTSx
USARTx Clear To Send
DTR1
USART1 Data Terminal Ready
DSR1
USART1 Data Set Ready
DCD1
USART1 Data Carrier Detect
RI1
USART1 Ring Indicator
Output
Input
I/O
Input
Output
Input
Synchronous Serial Controller - SSC
TD
SSC Transmit Data
Output
RD
SSC Receive Data
Input
TK
SSC Transmit Clock
I/O
RK
SSC Receive Clock
I/O
TF
SSC Transmit Frame Sync
I/O
RF
SSC Receive Frame Sync
I/O
Timer/Counter - TC
TCLKx
TC Channel x External Clock Input
Input
TIOAx
TC Channel x I/O Line A
I/O
TIOBx
TC Channel x I/O Line B
I/O
Pulse Width Modulation Controller- PWMC
PWMHx
PWM Waveform Output High for channel x
PWMLx
PWM Waveform Output Low for channel x
PWMFI0
PWM Fault Input
Output
The only output in
complementary mode
when dead time insertion
is enabled.
Output
Input
Serial Peripheral Interface - SPI
MISO
Master In Slave Out
I/O
MOSI
Master Out Slave In
I/O
SPCK
SPI Serial Clock
I/O
SPI_NPCS0
SPI Peripheral Chip Select 0
I/O
Low
SPI_NPCS1 SPI_NPCS3
SPI Peripheral Chip Select
Output
Low
10
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Voltage
reference
Comments
Two-Wire Interface- TWI
TWDx
TWIx Two-wire Serial Data
I/O
TWCKx
TWIx Two-wire Serial Clock
I/O
Analog
ADVREF
ADC, DAC and Analog Comparator
Reference
Analog
12-bit Analog-to-Digital Converter - ADC
AD0-AD14
Analog Inputs
ADTRG
ADC Trigger
Analog,
Digital
Input
VDDIO
12-bit Digital-to-Analog Converter - DAC
DAC0 - DAC1
Analog output
DACTRG
DAC Trigger
Analog,
Digital
Input
VDDIO
Fast Flash Programming Interface - FFPI
PGMEN0PGMEN2
Programming Enabling
Input
PGMM0-PGMM3
Programming Mode
Input
PGMD0-PGMD15
Programming Data
I/O
PGMRDY
Programming Ready
Output
High
PGMNVALID
Data Direction
Output
Low
PGMNOE
Programming Read
Input
Low
PGMCK
Programming Clock
Input
PGMNCMD
Programming Command
Input
VDDIO
VDDIO
Low
USB Full Speed Device
DDM
USB Full Speed Data -
DDP
Note:
USB Full Speed Data +
Analog,
Digital
VDDIO
Reset State:
- USB Mode
- Internal Pull-down(3)
1. Schmitt Triggers can be disabled through PIO registers.
2. Some PIO lines are shared with System I/Os.
3. Refer to USB Section of the product Electrical Characteristics for information on Pull-down value in USB Mode.
4. See “Typical Powering Schematics” Section for restrictions on voltage range of Analog Cells.
5. TDO pin is set in input mode when the Cortex-M4 Core is not in debug mode. Thus the internal pull-up corresponding to this
PIO line must be enabled to avoid current consumption due to floating input.
11
11100BS–ATARM–31-Jul-12
4. Package and Pinout
SAM4S devices are pin-to-pin compatible with SAM3N, SAM3S products in 64- and 100-pin versions, and AT91SAM7S legacy products in 64-pin versions.
4.1
4.1.1
SAM4SD32/SD16/SA16/S16/S8C Package and Pinout
100-Lead LQFP Package Outline
Figure 4-1.
Orientation of the 100-lead LQFP Package
75
51
76
50
100
26
1
4.1.2
25
100-ball TFBGA Package Outline
The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its
dimensions are 9 x 9 x 1.1 mm. Figure 4-2 shows the orientation of the 100-ball TFBGA
Package.
Figure 4-2.
Orientation of the 100-ball TFBGA Package
TOP VIEW
10
9
8
7
6
5
4
3
2
1
BALL A1
12
A
B
C
D
E
F
G
H
J
K
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
4.1.3
100-ball VFBGA Package Outline
Figure 4-3.
Orientation of the 100-ball VFBGA Package
13
11100BS–ATARM–31-Jul-12
4.1.4
100-Lead LQFP Pinout
Table 4-1.
SAM4SD32/SD16/SA16/S16/S8C 100-lead LQFP pinout
1
ADVREF
26
GND
51
TDI/PB4
76
TDO/TRACESWO/
PB5
2
GND
27
VDDIO
52
PA6/PGMNOE
77
JTAGSEL
3
PB0/AD4
28
PA16/PGMD4
53
PA5/PGMRDY
78
PC18
4
PC29/AD13
29
PC7
54
PC28
79
TMS/SWDIO/PB6
5
PB1/AD5
30
PA15/PGMD3
55
PA4/PGMNCMD
80
PC19
6
PC30/AD14
31
PA14/PGMD2
56
VDDCORE
81
PA31
7
PB2/AD6
32
PC6
57
PA27/PGMD15
82
PC20
8
PC31
33
PA13/PGMD1
58
PC8
83
TCK/SWCLK/PB7
9
PB3/AD7
34
PA24/PGMD12
59
PA28
84
PC21
10
VDDIN
35
PC5
60
NRST
85
VDDCORE
11
VDDOUT
36
VDDCORE
61
TST
86
PC22
12
PA17/PGMD5/
AD0
37
PC4
62
PC9
87
ERASE/PB12
13
PC26
38
PA25/PGMD13
63
PA29
88
DDM/PB10
14
PA18/PGMD6/
AD1
39
PA26/PGMD14
64
PA30
89
DDP/PB11
15
PA21/PGMD9/
AD8
40
PC3
65
PC10
90
PC23
16
VDDCORE
41
PA12/PGMD0
66
PA3
91
VDDIO
17
PC27
42
PA11/PGMM3
67
PA2/PGMEN2
92
PC24
18
PA19/PGMD7/
AD12
43
PC2
68
PC11
93
PB13/DAC0
19
PC15/AD11
44
PA10/PGMM2
69
VDDIO
94
PC25
20
PA22/PGMD10/
AD9
45
GND
70
GND
95
GND
21
PC13/AD10
46
PA9/PGMM1
71
PC14
96
PB8/XOUT
22
PA23/PGMD11
47
PC1
72
PA1/PGMEN1
97
PB9/PGMCK/XIN
23
PC12/AD12
48
PA8/XOUT32/
PGMM0
73
PC16
98
VDDIO
24
PA20/PGMD8/
AD3
49
PA7/XIN32/
PGMNVALID
74
PA0/PGMEN0
99
PB14/DAC1
25
PC0
50
VDDIO
75
PC17
100
VDDPLL
14
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
4.1.5
100-Ball TFBGA Pinout
Table 4-2.
SAM4SD32/SD16/SA16/S16/S8 100-ball TFBGA pinout
A1
PB1/AD5
C6
TCK/SWCLK/PB7
F1
PA18/PGMD6/
AD1
H6
PC4
A2
PC29
C7
PC16
F2
PC26
H7
PA11/PGMM3
A3
VDDIO
C8
PA1/PGMEN1
F3
VDDOUT
H8
PC1
A4
PB9/PGMCK/XIN
C9
PC17
F4
GND
H9
PA6/PGMNOE
A5
PB8/XOUT
C10
PA0/PGMEN0
F5
VDDIO
H10
TDI/PB4
A6
PB13/DAC0
D1
PB3/AD7
F6
PA27/PGMD15
J1
PC15/AD11
A7
DDP/PB11
D2
PB0/AD4
F7
PC8
J2
PC0
A8
DDM/PB10
D3
PC24
F8
PA28
J3
PA16/PGMD4
A9
TMS/SWDIO/PB6
D4
PC22
F9
TST
J4
PC6
A10
JTAGSEL
D5
GND
F10
PC9
J5
PA24/PGMD12
B1
PC30
D6
GND
G1
PA21/PGMD9/AD8
J6
PA25/PGMD13
B2
ADVREF
D7
VDDCORE
G2
PC27
J7
PA10/PGMM2
B3
GNDANA
D8
PA2/PGMEN2
G3
PA15/PGMD3
J8
GND
B4
PB14/DAC1
D9
PC11
G4
VDDCORE
J9
VDDCORE
B5
PC21
D10
PC14
G5
VDDCORE
J10
VDDIO
B6
PC20
E1
PA17/PGMD5/
AD0
G6
PA26/PGMD14
K1
PA22/PGMD10/
AD9
B7
PA31
E2
PC31
G7
PA12/PGMD0
K2
PC13/AD10
B8
PC19
E3
VDDIN
G8
PC28
K3
PC12/AD12
B9
PC18
E4
GND
G9
PA4/PGMNCMD
K4
PA20/PGMD8/
AD3
B10
TDO/TRACESWO/
PB5
E5
GND
G10
PA5/PGMRDY
K5
PC5
C1
PB2/AD6
E6
NRST
H1
PA19/PGMD7/
AD2
K6
PC3
C2
VDDPLL
E7
PA29/AD13
H2
PA23/PGMD11
K7
PC2
C3
PC25
E8
PA30/AD14
H3
PC7
K8
PA9/PGMM1
C4
PC23
E9
PC10
H4
PA14/PGMD2
K9
PA8/XOUT32/
PGMM0
C5
ERASE/PB12
E10
PA3
H5
PA13/PGMD1
K10
PA7/XIN32/
PGMNVALID
15
11100BS–ATARM–31-Jul-12
4.1.6
100-Ball VFBGA Pinout
Table 4-3.
SAM4SD32/SD16/SA16/S16/S8 100-ball VFBGA pinout
A1
ADVREF
C6
PC9
F1
VDDOUT
H6
PA12/PGMD0
A2
VDDPLL
C7
TMS/SWDIO/PB6
F2
PA18/PGMD6/
AD1
H7
PA9/PGMM1
A3
PB9/PGMCK/XIN
C8
PA1/PGMEN1
F3
PA17/PGMD5/
AD0
H8
VDDCORE
A4
PB8/XOUT
C9
PA0/PGMEN0
F4
GND
H9
PA6/PGMNOE
A5
JTAGSEL
C10
PC16
F5
GND
H10
A6
DDP/PB11
D1
PB1/AD5
F6
PC26
J1
PA20/AD3
A7
DDM/PB10
D2
PC30
F7
PA4/PGMNCMD
J2
PC12/AD12
A8
PC20
D3
PC31
F8
PA28
J3
PA16/PGMD4
A9
PC19
D4
PC22
F9
TST
J4
PC6
A10
TDO/TRACESWO/
PB5
D5
PC5
F10
PC8
J5
PA24
B1
GNDANA
D6
PA29/AD13
G1
PC15/AD11
J6
PA25
B2
PC25
D7
PA30/AD14
G2
PA19/PGMD7/
AD2
J7
PA11/PGMM3
B3
PB14/DAC1
D8
GND
G3
PA21/AD8
J8
VDDCORE
B4
PB13/DAC0
D9
PC14
G4
PA15/PGMD3
J9
VDDCORE
B5
PC23
D10
PC11
G5
PC3
J10
TDI/PB4
B6
PC21
E1
VDDIN
G6
PA10/PGMM2
K1
PA23
B7
TCK/SWCLK/PB7
E2
PB3/AD7
G7
PC1
K2
PC0
B8
PA31
E3
PB2/AD6
G8
PC28
K3
PC7
B9
PC18
E4
GND
G9
NRST
K4
PA13/PGMD1
B10
PC17
E5
GND
G10
PA27
K5
PA26
C1
PB0/AD4
E6
GND
H1
PC13/AD10
K6
PC2
C2
PC29
E7
VDDIO
H2
PA22/AD9
K7
VDDIO
C3
PC24
E8
PC10
H3
PC27
K8
VDDIO
C4
ERASE/PB12
E9
PA2/PGMEN2
H4
PA14/PGMD2
K9
PA8/XOUT32/
PGMM0
C5
VDDCORE
E10
PA3
H5
PC4
K10
PA7/XIN32/
PGMNVALID
16
PA5/PGMRDY
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
4.2
4.2.1
SAM4SD32/SD16/SA16/S16/S8 Package and Pinout
64-Lead LQFP Package Outline
Figure 4-4.
Orientation of the 64-lead LQFP Package
33
48
49
32
64
17
16
1
4.2.2
64-lead QFN Package Outline
Figure 4-5.
Orientation of the 64-lead QFN Package
64
49
1
48
16
33
17
TOP VIEW
32
17
11100BS–ATARM–31-Jul-12
4.2.3
64-Lead LQFP and QFN Pinout
Table 4-4.
64-pin SAM4SD32/SD16/SA16/S16/S8 pinout
1
ADVREF
17
GND
33
TDI/PB4
49
TDO/TRACESWO/
PB5
2
GND
18
VDDIO
34
PA6/PGMNOE
50
JTAGSEL
3
PB0/AD4
19
PA16/PGMD4
35
PA5/PGMRDY
51
TMS/SWDIO/PB6
4
PB1/AD5
20
PA15/PGMD3
36
PA4/PGMNCMD
52
PA31
5
PB2/AD6
21
PA14/PGMD2
37
PA27/PGMD15
53
TCK/SWCLK/PB7
6
PB3/AD7
22
PA13/PGMD1
38
PA28
54
VDDCORE
7
VDDIN
23
PA24/PGMD12
39
NRST
55
ERASE/PB12
8
VDDOUT
24
VDDCORE
40
TST
56
DDM/PB10
9
PA17/PGMD5/
AD0
25
PA25/PGMD13
41
PA29
57
DDP/PB11
10
PA18/PGMD6/
AD1
26
PA26/PGMD14
42
PA30
58
VDDIO
11
PA21/PGMD9/
AD8
27
PA12/PGMD0
43
PA3
59
PB13/DAC0
12
VDDCORE
28
PA11/PGMM3
44
PA2/PGMEN2
60
GND
13
PA19/PGMD7/
AD2
29
PA10/PGMM2
45
VDDIO
61
XOUT/PB8
14
PA22/PGMD10/
AD9
30
PA9/PGMM1
46
GND
62
XIN/PGMCK/PB9
15
PA23/PGMD11
31
PA8/XOUT32/
PGMM0
47
PA1/PGMEN1
63
PB14/DAC1
16
PA20/PGMD8/
AD3
32
PA7/XIN32/
PGMNVALID
48
PA0/PGMEN0
64
VDDPLL
Note:
18
The bottom pad of the QFN package must be connected to ground.
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
5. Power Considerations
5.1
Power Supplies
The SAM4S has several types of power supply pins:
• VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage
ranges from 1.08V to 1.32V.
• VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers), USB transceiver, Backup
part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V.
• VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply.
Voltage ranges from 1.62V to 3.6V.
• VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator. Voltage
ranges from 1.08V to 1.32V.
5.2
Voltage Regulator
The SAM4S embeds a voltage regulator that is managed by the Supply Controller.
This internal regulator is designed to supply the internal core of SAM4S. It features two operating modes:
• In Normal mode, the voltage regulator consumes less than 500 µA static current and draws
80 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current
depending on the required load current. In Wait Mode quiescent current is only 5 µA.
• In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT)
is driven internally to GND. The default output voltage is 1.20V and the start-up time to reach
Normal mode is less than 300 µs.
For adequate input and output power supply decoupling/bypassing, refer to the “Voltage Regulator” section in the “Electrical Characteristics” section of the datasheet.
5.3
Typical Powering Schematics
The SAM4S supports a 1.62V-3.6V single supply mode. The internal regulator input is connected to the source and its output feeds VDDCORE. Figure 5-1 below shows the power
schematics.
As VDDIN powers the voltage regulator, the ADC, DAC and the analog comparator, when the
user does not want to use the embedded voltage regulator, it can be disabled by software via
the SUPC (note that this is different from Backup mode).
19
11100BS–ATARM–31-Jul-12
Figure 5-1.
Single Supply
VDDIO
Main Supply
(1.8V-3.6V)
USB
Transceivers.
ADC, DAC
Analog Comp.
VDDIN
VDDOUT
Voltage
Regulator
VDDCORE
VDDPLL
Note:
Restrictions
For USB, VDDIO needs to be greater than 3.0V.
For ADC, VDDIN needs to be greater than 2.0V.
For DAC, VDDIN needs to be greater than 2.4V.
Figure 5-2.
Core Externally Supplied
VDDIO
Main Supply
(1.62V-3.6V)
USB
Transceivers.
Can be the
same supply
ADC, DAC, Analog
Comparator Supply
(2.0V-3.6V)
ADC, DAC
Analog Comp.
VDDIN
VDDOUT
VDDCORE Supply
(1.08V-1.32V)
Voltage
Regulator
VDDCORE
VDDPLL
Note:
Restrictions
For USB, VDDIO needs to be greater than 3.0V.
For ADC, VDDIN needs to be greater than 2.0V.
For DAC, VDDIN needs to be greater than 2.4V.
Figure 5-3 below provides an example of the powering scheme when using a backup battery.
Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch
off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after
backup reset). External wake-up of the system can be from a push button or any signal. See
Section 5.6 “Wake-up Sources” for further details.
20
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 5-3.
Backup Battery
ADC, DAC, Analog
Comparator Supply
(2.0V-3.6V)
Backup
Battery
VDDIO
USB
Transceivers.
+
ADC, DAC
Analog Comp.
VDDIN
Main Supply
IN
OUT
3.3V
LDO
VDDOUT
Voltage
Regulator
VDDCORE
ON/OFF
VDDPLL
PIOx (Output)
WAKEUPx
External wakeup signal
Note: The two diodes provide a “switchover circuit” (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
5.4
Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator,
the main crystal oscillator or the PLLA. The power management controller can be used to adapt
the frequency and to disable the peripheral clocks.
5.5
Low-Power Modes
The various low-power modes of the SAM4S are described below:
5.5.1
Backup Mode
The purpose of backup mode is to achieve the lowest power consumption possible in a system
which is performing periodic wake-ups to perform tasks but not requiring fast startup time. Total
current consumption is 1 µA typical (VDDIO = 1.8V to 25°C).
The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz
oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The
regulator and the core supply are off.
Backup mode is based on the Cortex-M4 deep sleep mode with the voltage regulator disabled.
The SAM4S can be awakened from this mode through WUP0-15 pins, the supply monitor (SM),
the RTT or RTC wake-up event.
Backup mode is entered by writing the Supply Controller Control Register (SUPC_CR) with the
VROFF bit at 1 (a key is needed to write the VROFF bit, please refer to the “Supply Controller
(SUPC)” section of the product datasheet) and with the SLEEPDEEP bit in the Cortex-M4 System Control Register set to 1. (See the Power management description in the “ARM Cortex-M4
Processor” section of the product datasheet).
21
11100BS–ATARM–31-Jul-12
Entering Backup mode:
• Set the SLEEPDEEP bit of Cortex_M4 to 1
• Set the VROFF bit of SUPC_CR to 1
Exit from Backup mode happens if one of the following enable wake up events occurs:
• WKUPEN0-15 pins (level transition, configurable debouncing)
• Supply Monitor alarm
• RTC alarm
• RTT alarm
5.5.2
Wait Mode
The purpose of the wait mode is to achieve very low power consumption while maintaining the
whole device in a powered state for a startup time of less than 10 µs. Current Consumption in
Wait mode is typically 32 µA (total current consumption) if the internal voltage regulator is used.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core,
peripherals and memories power supplies are still powered. From this mode, a fast start up is
available.
This mode is entered by setting WAITMODE bit to 1 (in PMC clock generator Main Oscillator
register) with LPM = 1 (Low Power Mode bit in PMC_FSMR) and with FLPM = 00 or FLPM=01
(Flash Low Power Mode bits in PMC_FSMR).
The Cortex-M4 is able to handle external events or internal events in order to wake-up the core.
This is done by configuring the external lines WUP0-15 as fast startup wake-up pins (refer to
Section 5.7 “Fast Startup”). RTC or RTT Alarm and USB wake-up events can be used to wake
up the CPU.
Entering Wait Mode:
• Select the 4/8/12 MHz fast RC oscillator as Main Clock
• Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR)
• Set the FLPM bitfield in the PMC Fast Startup Mode Register (PMC_FSMR)
• Set Flash Wait State at 0.
• Set the WAITMODE bit = 1 in PMC Main Oscillator Register (CKGR_MOR)
• Wait for Master Clock Ready MCKRDY = 1 in the PMC Status Register (PMC_SR)
Note:
Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN
bit and the effective entry in Wait mode. Depending on the user application, waiting for
MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired
instructions.
Depending on Flash Low Power Mode (FLPM) value, the Flash will enter in three different
modes:
• FLPM[00] in Standby mode
• FLPM[01] in Deep Power Down mode
• FLPM[10] in mode Idle.
Following the Flash mode selection, the consumption in wait mode will decrease. In Deep Power
Down mode the recovery time of the Flash in Standby mode will be less than the power up
delay.
22
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
5.5.3
Sleep Mode
The purpose of sleep mode is to optimize power consumption of the device versus response
time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The
current consumption in this mode is application dependent.
This mode is entered via Wait for Interrupt (WFI) instructions with LPM = 0 in PMC_FSMR.
The processor can be awakened from an interrupt if WFI instruction of the Cortex-M4 is used.
5.5.4
Low Power Mode Summary Table
The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake up sources can be individually configured. Table 5-1 below shows a summary
of the configurations of the low-power modes.
Table 5-1.
Mode
Backup
Mode
Wait
Mode
w/Flash
in
Standby
mode
Wait
Mode
w/Flash
in Deep
Power
Down
mode
Sleep
Mode
Notes:
Low-power Mode Configuration Summary
SUPC,
32 kHz Osc,
RTC, RTT
Backup
Registers,
Core
POR
Memory
(Backup
Region)
Regulator Peripherals
ON
ON
ON
ON
OFF
OFF
(Not powered)
Mode Entry
VROFF bit = 1
+SLEEPDEEP
bit = 1
PIO State
Potential Wake Up Core at while in Low PIO State Consumption Wake-up
(1) (2)
Time(3)
Sources
Wake Up Power Mode at Wake Up
WUP0-15 pins
SM alarm
RTC alarm
RTT alarm
Reset
Previous
state saved
PIOA &
PIOB &
PIOC
Inputs with
pull ups
1 µA typ(4)
300 ms
ON
WAITMODE bit
=1
+SLEEPDEEP
Powered
bit = 0
(Not clocked)
+LPM bit = 1
FLPM0 bit = 0
FLPM1 bit = 0
Any Event from:
Fast startup through
WUP0-15 pins
Clocked
RTC alarm
back
RTT alarm
USB wake-up
Previous
state saved
Unchanged 32.2 µA(5)
< 10 µs
ON
WAITMODE bit
=1
+SLEEPDEEP
Powered
bit = 0
(Not clocked)
+LPM bit = 1
FLPM0 bit = 0
FLPM1 bit = 1
Any Event from:
Fast startup through
WUP0-15 pins
Clocked
RTC alarm
back
RTT alarm
USB wake-up
Previous
state saved
Unchanged 27.6 µA
< 10µs
WFI
Powered(6) +SLEEPDEEP
(Not clocked) bit = 0
+LPM bit = 0
Entry mode =WFI
Interrupt Only;
Any Enabled
Interrupt and/or Any
Event from: Fast
Clocked
start-up through
back
WUP0-15 pins
RTC alarm
RTT alarm
USB wake-up
Previous
state saved
Unchanged
ON
(7)
(7)
1. The external loads on PIOs are not taken into account in the calculation.
2. Supply Monitor current consumption is not included.
23
11100BS–ATARM–31-Jul-12
3. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works
with the 4/8/12 MHz fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up
time is defined as the time taken for wake up until the first instruction is fetched.
4. Total Current consumption, 1 µA typ to 1.8V on VDDIO to 25°C.
5. 20.4 µA on VDDCORE, 32.2 µA for total current consumption
6. In this mode the core is supplied and not clocked but some peripherals can be clocked.
7. Depends on MCK frequency. In this mode, the core is supplied but some peripherals can be clocked.
5.6
Wake-up Sources
The wake-up events allow the device to exit the backup mode. When a wake-up event is
detected, the Supply Controller performs a sequence which automatically reenables the core
power supply and the SRAM power supply, if they are not already enabled.
Figure 5-4.
Wake-up Source
SMEN
sm_out
RTCEN
rtc_alarm
Core
Supply
Restart
RTTEN
rtt_alarm
WKUPT0
WKUP0
24
WKUPDBC
WKUPEN1
WKUPIS1
SLCK
WKUPS
Debouncer
Falling/Rising
Edge
Detector
WKUPT15
WKUP15
WKUPIS0
Falling/Rising
Edge
Detector
WKUPT1
WKUP1
WKUPEN0
WKUPEN15
WKUPIS15
Falling/Rising
Edge
Detector
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
5.7
Fast Startup
The SAM4S allows the processor to restart in a few microseconds while the processor is in wait
mode or in sleep mode. A fast start up can occur upon detection of a low level on one of the 19
wake-up inputs (WKUP0 to 15 + SM + RTC + RTT).
The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast startup signal to the Power Management Controller. As soon as the fast start-up signal is asserted,
the PMC automatically restarts the embedded 4/8/12 MHz Fast RC oscillator, switches the master clock on this 4 MHz clock and reenables the processor clock.
Figure 5-5.
Fast Start-Up Sources
FSTT0
WKUP0
FSTP0
FSTT1
WKUP1
FSTP1
FSTT15
WKUP15
fast_restart
FSTP15
RTTAL
RTT Alarm
RTCAL
RTC Alarm
USBAL
USB Alarm
25
11100BS–ATARM–31-Jul-12
6. Input/Output Lines
The SAM4S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO)
and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the
PIO controllers. The same PIO line can be used whether in I/O mode or by the multiplexed
peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs.
6.1
General Purpose I/O Lines
GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such
as pull-up or pull-down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing
or input change interrupt. Programming of these modes is performed independently for each I/O
line through the PIO controller user interface. For more details, refer to the product “PIO Controller” section.
The input/output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM4S embeds high speed pads able to handle up to 70 MHz for HSMCI (MCK/2), 70 MHz
for SPI clock lines and 46 MHz on other lines. See the “AC Characteristics” sub-section of the
product Electrical Characteristics. Typical pull-up and pull-down value is 100 kΩ for all I/Os.
Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1 below). It consists of
an internal series resistor termination scheme for impedance matching between the driver output (SAM4S) and the PCB trace impedance preventing signal reflection. The series resistor
helps to reduce IOs switching current (di/dt) thereby reducing in turn, EMI. It also decreases
overshoot and undershoot (ringing) due to inductance of interconnect between devices or
between boards. In conclusion ODT helps diminish signal integrity issues.
Figure 6-1.
On-Die Termination
Z0 ~ Zout + Rodt
ODT
36 Ohms Typ.
Rodt
Receiver
SAM4 Driver with
Zout ~ 10 Ohms
6.2
PCB Trace
Z0 ~ 50 Ohms
System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few.
Described below in Table 6-1 are the SAM4S system I/O lines shared with PIO lines.
These pins are software configurable as general purpose I/O or system pins. At startup the
default function of these pins is always used.
26
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Table 6-1.
System I/O Configuration Pin List.
SYSTEM_IO
bit number
Notes:
Default function
after reset
Other function
Constraints for
normal start
Configuration
(1)
12
ERASE
PB12
Low Level at startup
10
DDM
PB10
-
11
DDP
PB11
-
7
TCK/SWCLK
PB7
-
6
TMS/SWDIO
PB6
-
5
TDO/TRACESWO
PB5
-
4
TDI
PB4
-
-
PA7
XIN32
-
-
PA8
XOUT32
-
-
PB9
XIN
-
-
PB8
XOUT
-
In Matrix User Interface Registers
(Refer to the System I/O
Configuration Register in the “Bus
Matrix” section of the datasheet.)
See footnote (2) below
See footnote (3) below
1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the
user application sets PB12 into PIO mode,
2. In the product Datasheet refer to: “Slow Clock Generator” of the “Supply Controller” section.
3. In the product Datasheet refer to: “3 to 20 MHZ Crystal Oscillator” information in the “PMC” section.
6.2.1
Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on
a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference
and reset state, refer to Table 3-1 on page 8.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging
probe. Please refer to the “Debug and Test” Section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins
when the debug port is not needed in the end application. Mode selection between SWJ-DP
mode (System IO mode) and general IO mode is performed through the AHB Matrix Special
Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing
and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire
Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous
trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and
JTAG-DP switching, please refer to the “Debug and Test” Section.
27
11100BS–ATARM–31-Jul-12
6.3
Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming
mode of the SAM4S series. The TST pin integrates a permanent pull-down resistor of about 15
kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming
mode, see the Fast Flash Programming Interface (FFPI) section. For more details on the manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet.
6.4
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components or asserted low externally to reset the
microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT
and Supply Controller). There is no constraint on the length of the reset pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up
resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.
6.5
ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased
state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so
that it can be left unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high
during less than 100 ms, it is not taken into account. The pin must be tied high during more than
220 ms to perform a Flash erase operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE
pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of
this pin must be low to prevent unwanted erasing. Refer to Section 10.16 “Peripheral Signal Multiplexing on I/O Lines” on page 48. Also, if the ERASE pin is used as a standard I/O output,
asserting the pin to low does not erase the Flash.
28
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
7. Processor and Architecture
7.1
ARM Cortex-M4 Processor
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store
• Three-stage pipeline
• Saturating arithmetic for signal processing
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Thumb and Debug states
• Handler and Thread modes
• Low latency ISR entry and exit
7.2
APB/AHB bridge
The SAM4S embeds One Peripheral bridge.
The peripherals of the bridge are clocked by MCK.
7.3
Matrix Masters
The Bus Matrix of the SAM4S manages 4 masters, which means that each master can perform
an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings.
Table 7-1.
7.4
List of Bus Matrix Masters
Master 0
Cortex-M4 Instruction/Data
Master 1
Cortex-M4 System
Master 2
Peripheral DMA Controller (PDC)
Master 3
CRC Calculation Unit
Matrix Slaves
The Bus Matrix of the SAM4S manages 5 slaves. Each slave has its own arbiter, allowing a different arbitration per slave.
Table 7-2.
List of Bus Matrix Slaves
Slave 0
Internal SRAM
Slave 1
Internal ROM
Slave 2
Internal Flash
Slave 3
External Bus Interface
Slave 4
Peripheral Bridge
29
11100BS–ATARM–31-Jul-12
7.5
Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M4 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired, and shown as “-” in the following table.
Table 7-3.
SAM4S Master to Slave Access
Masters
Slaves
7.6
0
1
2
3
Cortex-M4 I/D
Bus
Cortex-M4 S
Bus
PDC
CRCCU
0
Internal SRAM
-
X
X
X
1
Internal ROM
X
-
X
X
2
Internal Flash
X
-
-
X
3
External Bus Interface
-
X
X
X
4
Peripheral Bridge
-
X
X
-
Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities):
Table 7-4.
30
Peripheral DMA Controller
Instance name
Channel T/R
PWM
Transmit
TWI1
Transmit
TWI0
Transmit
UART1
Transmit
UART0
Transmit
USART1
Transmit
USART0
Transmit
DACC
Transmit
SPI
Transmit
SSC
Transmit
HSMCI
Transmit
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Table 7-4.
7.7
Peripheral DMA Controller
Instance name
Channel T/R
PIOA
Receive
TWI1
Receive
TWI0
Receive
UART1
Receive
UART0
Receive
USART1
Receive
USART0
Receive
ADC
Receive
SPI
Receive
SSC
Receive
HSMCI
Receive
Debug and Test Features
• Debug access to all memory and registers in the system, including Cortex-M4 register bank
when the core is running, halted, or held in reset.
• Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
• Data Watchpoint and Trace (DWT) unit for implementing watch points, data tracing, and
system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• IEEE®1149.1 JTAG Boundary scan on All Digital Pins
31
11100BS–ATARM–31-Jul-12
8. Product Mapping
Figure 8-1.
SAM4S Product Mapping
0x00000000
Code
0x00000000
Address memory space
Peripherals
0x40000000
HSMCI
Boot Memory
Code
0x00400000
Internal Flash
0x00800000
Internal ROM
0x00C00000
1 MByte
bit band
regiion
SSC
0x20000000
22
0x40008000
0x20100000
SRAM
SPI
Reserved
Undefined
0x40010000
TC0
0x24000000
0x40000000
21
0x4000C000
0x20400000
Reserved
0x1FFFFFFF
18
0x40004000
32 MBytes
bit band alias
23
TC0
24
TC0
External RAM
0x60000000
0x61000000
TC2
25
0x40014000
TC1
SMC Chip Select 0
TC1
+0x80
Peripherals
0x60000000
TC0
+0x40
External SRAM
TC3
26
+0x40
TC1
SMC Chip Select 1
0xA0000000
0x62000000
TC1
0x63000000
SMC Chip Select 3
27
+0x80
Reserved
SMC Chip Select 2
TC4
TC5
28
0x40018000
0xE0000000
0x64000000
TWI0
System
Reserved
0x9FFFFFFF
19
0x4001C000
0xFFFFFFFF
TWI1
20
0x40020000
0x400E0000
System Controller
PWM
USART1
0x400E0400
Reserved
5
0x400E0600
0x40030000
UART0
Reserved
8
0x400E0740
15
0x4002C000
PMC
ID
14
0x40028000
MATRIX
block
peripheral
USART0
10
0x400E0200
offset
31
0x40024000
SMC
1 MByte
bit band
regiion
0x40034000
CHIPID
UDP
0x400E0800
ADC
9
0x400E0A00
DACC
6
ACC
0x400E0E00
CRCCU
11
Reserved
12
0x400E0000
PIOC
System Controller
13
0x400E2600
RSTC
Reserved
1
+0x10
35
0x40048000
PIOB
0x400E1400
34
0x40044000
PIOA
0x400E1200
30
0x40040000
EFC1
0x400E1000
29
0x4003C000
EFC
0x400E0C00
33
0x40038000
UART1
0x40100000
SUPC
Reserved
+0x30
0x40200000
RTT
3
+0x50
0x40400000
32 MBytes
bit band alias
WDT
Reserved
4
+0x60
0x60000000
RTC
2
+0x90
GPBR
0x400E1600
Reserved
0x4007FFFF
32
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
9. Memories
9.1
9.1.1
Embedded Memories
Internal SRAM
The SAM4SD32 device (2x1024 Kbytes) embeds a total of 160-Kbytes high-speed SRAM.
The SAM4SD16 device (2x512Kbytes)embeds a total of 160-Kbytes high-speed SRAM.
The SAM4SA16 device (1024 Kbytes) embeds a total of 160-Kbytes high-speed SRAM.
The SAM4S16 device (1024 Kbytes) embeds a total of 128-Kbytes high-speed SRAM.
The SAM4S8 device (512 Kbytes) embeds a total of 128-Kbytes high-speed SRAM.
The SRAM is accessible over System Cortex-M4 bus at address 0x2000 0000.
The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 to
0x23FF FFFF.
9.1.2
Internal ROM
The SAM4S embeds an Internal ROM, which contains the SAM Boot Assistant (SAM-BA®), In
Application Programming routines (IAP) and Fast Flash Programming Interface (FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
9.1.3
9.1.3.1
Embedded Flash
Flash Overview
The memory is organized in sectors. Each sector has a size of 64 Kbytes. The first sector of 64
Kbytes is divided into 3 smaller sectors.
The three smaller sectors are organized to consist of 2 sectors of 8 Kbytes and 1 sector of 48
Kbytes. Refer to Figure 9-1, "Global Flash Organization" below.
33
11100BS–ATARM–31-Jul-12
Figure 9-1.
Global Flash Organization
Sector size
Sector name
8 KBytes
Small Sector 0
8 KBytes
Small Sector 1
48 KBytes
Larger Sector
64 KBytes
Sector 1
64 KBytes
Sector n
Sector 0
Each Sector is organized in pages of 512 Bytes.
For sector 0:
• The smaller sector 0 has 16 pages of 512Bytes
• The smaller sector 1 has 16 pages of 512 Bytes
• The larger sector has 96 pages of 512 Bytes
From Sector 1 to n:
The rest of the array is composed of 64-Kbyte sectors of 128 pages, each page of 512 bytes.
Refer to Figure 9-2, "Flash Sector Organization" below.
34
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 9-2.
Flash Sector Organization
A sector size is 64 KBytes
Sector 0
16 pages of 512 Bytes
Smaller sector 0
16 pages of 512 Bytes
Smaller sector 1
96 pages of 512 Bytes
Larger sector
Sector 1
128 pages of 512 Bytes
Sector n
128 pages of 512 Bytes
Flash size varies by product:
• SAM4S8: the Flash size is 512 Kbytes
– Internal Flash address is 0x0040_0000
• SAM4SD16/SA16: the Flash size is 2 x 512 Kbytes
– Internal Flash0 address is 0x0040_0000
– Internal Flash1 address is 0x0048_0000
• SAM4SD32: the Flash size is 2 x 1024 Kbytes
– Internal Flash0 address is 0x0040_0000
– Internal Flash1 address is 0x0050_0000
Refer to Figure 9-3, "Flash Size" below for the organization of the Flash following its size.
35
11100BS–ATARM–31-Jul-12
Figure 9-3.
Flash Size
Flash 1 MBytes
Flash 512 KBytes
Flash 256 KBytes
2 * 8 KBytes
2 * 8 KBytes
2 * 8 KBytes
1 * 48 KBytes
1 * 48 KBytes
1 * 48 KBytes
3 * 64 KBytes
7 * 64 KBytes
15 * 64 KBytes
Erasing the memory can be performed as follows:
• on a 512-byte page inside a sector, of 8Kbytes
Note:
EWP and EWPL commands can be only used in 8Kbytes sectors.
• on a 4-Kbyte Block inside a sector of 8 Kbytes/48 Kbytes/64 Kbytes
• on a sector of 8 Kbytes/48 Kbytes/64 Kbytes
• on chip
9.1.3.2
Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller manages accesses performed by the masters of the
system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block.
It manages the programming, erasing, locking and unlocking sequences of the Flash using a full
set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system
about the Flash organization, thus making the software generic.
9.1.3.3
Flash Speed
The user needs to set the number of wait states depending on the frequency used:
For more details, refer to the “AC Characteristics” sub-section of the product “Electrical
Characteristics”.
36
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
9.1.3.4
Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is
composed of several consecutive pages, and each lock region has its associated lock bit.
Table 9-1.
Lock bit number
Product
Number of lock bits
Lock region size
SAM4SD32
256 (128 + 128)
8 Kbytes
SAM4SD16
128 (64 + 64)
8 Kbytes
SAM4SA16
128
8 Kbytes
SAM4S8
64
8 Kbytes
If a locked-region’s erase or program command occurs, the command is aborted and the EEFC
triggers an interrupt.
The lock bits are software programmable through the EEFC User Interface. The command “Set
Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.1.3.5
Security Bit Feature
The SAM4SD32 and SAM4SD16 feature 2 security bits, the SAM4S16/SA16/S8 feature a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When one of the security
bits is enabled, any access to the Flash, SRAM, Core Registers and Internal Peripherals either
through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This
ensures the confidentiality of the code programmed in the Flash.
This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of
the EEFC User Interface. Disabling the security bit can only be achieved by asserting the
ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated,
all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
operation. However, it is safer to connect it directly to GND for the final application.
9.1.3.6
Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are
factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
9.1.3.7
Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory configured and
cannot be changed by the user. The ERASE pin has no effect on the unique identifier.
9.1.3.8
User Signature
Each part contains a User Signature of 512 bytes. It can be used by the user to store user information such as trimming, keys, etc., that the customer does not want to be erased by asserting
the ERASE pin or by software ERASE command. Read, write and erase of this area is allowed.
37
11100BS–ATARM–31-Jul-12
9.1.3.9
Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through a multiplexed
fully-handshaked parallel port. It allows gang programming with market-standard industrial
programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
9.1.3.10
SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the
on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
9.1.3.11
GPNVM Bits
The SAM4S features two GPNVM bits. These bits can be cleared or set respectively through the
commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
The Flash of the SAM4S16/SA16 is composed of 1024 Kbytes in a single bank. The Flash of the
SAM4S8 is composed of 512Kbytes in a single bank.
The SAM4SD32/SD16 features 3 GPNVM bits that can be cleared or set respectively through
the "Clear GPNVM Bit" and "Set GPNVM Bit" commands of the EEFC User Interface. The
GPNVM0 is the security bit. The GPNVM1 is used to select the boot mode (boot always at 0x00)
on ROM or FLASH. The SAM4SD32/16 embeds an additional GPNVM bit: GPNVM2. This
GPNVM bit is used only to swap the Flash0 and Flash1. If GPNVM bit 2 is:
ENABLE: the Flash1 is mapped at address 0x0040_0000 (Flash1 and Flash0 are continuous).
DISABLE: the Flash0 is mapped at address 0x0040_0000 (Flash0 and Flash1 are continuous).
Table 9-2.
9.1.4
General-purpose Non volatile Memory Bits
GPNVMBit[#]
Function
0
Security bit
1
Boot mode selection
2
Flash selection (Flash 0 or Flash 1)
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory
layout can be changed via GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the
Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM.
Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.
38
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting
ERASE clears the GPNVM Bit 2 and thus selects the boot from bank 0 by default.
9.2
External Memories
The SAM4S features one External Bus Interface to provide an interface to a wide range of external memories and to any parallel peripheral.
9.2.1
Static Memory Controller
• 16-Mbyte Address Space per Chip Select
• 8- bit Data Bus
• Word, Halfword, Byte Transfers
• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
• Programmable Data Float Time per Chip Select
• External Wait Request
• Automatic Switch to Slow Clock Mode
• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
• NAND Flash additional logic supporting NAND Flash with Multiplexed Data/Address buses
• Hardware Configurable number of chip selects from 1 to 4
• Programmable timing on a per chip select basis
10. System Controller
The System Controller is a set of peripherals which allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc...
See the system controller block diagram in Figure 10-1 on page 40.
39
11100BS–ATARM–31-Jul-12
Figure 10-1. System Controller Block Diagram
VDDIO
VDDOUT
vr_on
vr_mode
Software Controlled
Voltage Regulator
VDDIO
Supply
Controller
Zero-Power
Power-on Reset
PIOA/B/C
Input/Output Buffers
ON
Supply
Monitor
(Backup)
VDDIN
PIOx
out
Analog
Comparator
WKUP0 - WKUP15
General Purpose
Backup Registers
ADVREF
rtc_nreset
SLCK
RTC
ADx
ADC Analog
Circuitry
DAC Analog
Circuitry
rtc_alarm
DACx
VDDIO
rtt_nreset
SLCK
RTT
rtt_alarm
XIN32
Xtal 32 kHz
Oscillator
Embedded
32 kHz RC
Oscillator
Slow Clock
SLCK
bod_core_on
lcore_brown_out
Brownout
Detector
(Core)
osc32k_rc_en
VDDCORE
SRAM
vddcore_nreset
Backup Power Supply
DDM
vddcore_nreset
XTALSEL
XOUT32
DDP
USB
Transeivers
osc32k_xtal_en
Reset
Controller
NRST
proc_nreset
periph_nreset
ice_nreset
Peripherals
Matrix
Peripheral
Bridge
Cortex-M4
FSTT0 - FSTT15
SLCK
Embedded
12 / 8 / 4 MHz
RC
Oscillator
XIN
XOUT
Flash
Main Clock
MAINCK
3 - 20 MHz
XTAL Oscillator
Power
Management
Controller
Master Clock
MCK
PLLACK
MAINCK
PLLA
SLCK
VDDIO
MAINCK
Watchdog
Timer
PLLBCK
PLLB
Core Power Supply
FSTT0 - FSTT15 are possible Fast Startup sources, generated by WKUP0 - WKUP15 pins,
but are not physical pins.
40
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
10.1
System Controller and Peripheral Mapping
Refer to Figure 8-1, "SAM4S Product Mapping".
All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2
Power-on-Reset, Brownout and Supply Monitor
The SAM4S embeds three features to monitor, warn and/or reset the chip:
• Power-on-Reset on VDDIO
• Brownout Detector on VDDCORE
• Supply Monitor on VDDIO
10.2.1
Power-on-Reset
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but
also during power down. If VDDIO goes below the threshold voltage, the entire chip is reset. For
more information, refer to the “Electrical Characteristics” section of the datasheet.
10.2.2
Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the Supply Controller (SUPC_MR). It is especially recommended to disable it
during low-power modes such as wait or sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to the “Supply Controller (SUPC)” and “Electrical Characteristics” sections of the
datasheet.
10.2.3
10.3
Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software
and is fully programmable with 16 steps for the threshold (between 1.6V to 3.4V). It is controlled
by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply monitor power consumption by a factor of up to 2048. For more information, refer to the “Supply
Controller (SUPC)” and “Electrical Characteristics” sections of the datasheet.
Reset Controller
The Reset Controller is based on a Power-on-Reset cell, and a Supply Monitor on VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a
general reset, a wake-up reset, a software reset, a user reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin input/output. It
is capable to shape a reset signal for the external devices, simplifying to a minimum connection
of a push-button on the NRST pin to implement a manual reset.
The configuration of the Reset Controller is saved as supplied on VDDIO.
10.4
Supply Controller (SUPC)
The Supply Controller controls the power supplies of each section of the processor and the
peripherals (via Voltage regulator control).
The Supply Controller has its own reset circuitry and is clocked by the 32 kHz Slow clock
generator.
41
11100BS–ATARM–31-Jul-12
The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell.
The zero-power power-on reset allows the Supply Controller to start properly, while the software-programmable brownout detector allows detection of either a battery discharge or main
voltage loss.
The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC
oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal
oscillator and select it as the Slow Clock source.
The Supply Controller starts up the device by sequentially enabling the internal power switches
and the Voltage Regulator, then it generates the proper reset signals to the core power supply.
It also enables to set the system in different low-power modes and to wake it up from a wide
range of events.
10.5
Clock Generator
The Clock Generator is made up of:
• One Low-power 32768 Hz Slow Clock Oscillator with bypass mode
• One Low-power RC Oscillator
• One 3-20 MHz Crystal Oscillator, which can be bypassed
• One Fast RC Oscillator, factory programmed. Three output frequencies can be selected: 4, 8
or 12 MHz. By default 4 MHz is selected.
• One 80 to 240 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller
• One 80 to 240 MHz programmable PLL (PLLA), provides the clock, MCK to the processor
and peripherals. The PLLA input frequency is from 3 MHz to 32 MHz.
42
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 10-2. Clock Generator Block Diagram
Clock Generator
XTALSEL
On Chip
32k RC OSC
XIN32
XOUT32
XIN
Slow Clock
SLCK
Slow Clock
Oscillator
12M Main
Oscillator
Main Clock
MAINCK
XOUT
On Chip
12/8/4 MHz
RC OSC
MAINSEL
PLL and
Divider B
PLLB Clock
PLLBCK
PLL and
Divider A
PLLA Clock
PLLACK
Status
Control
Power
Management
Controller
10.6
Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
• the Processor Clock, HCLK
• the Free running processor clock, FCLK
• the Cortex SysTick external clock
• the Master Clock, MCK, in particular to the Matrix and the memory interfaces
• the USB Clock, UDPCK
• independent peripheral clocks, typically at the frequency of MCK
• three programmable clock outputs: PCK0, PCK1 and PCK2
The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The
unused oscillator is disabled automatically so that power consumption is optimized.
By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at
4 MHz.
The user can trim the 8 and 12 MHz RC Oscillator frequency by software.
43
11100BS–ATARM–31-Jul-12
Figure 10-3. Power Management Controller Block Diagram
Processor
Clock
Controller
HCK
int
Sleep Mode
Divider
/8
SystTick
FCLK
Master Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
Prescaler
/1,/2,/4,...,/64
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
ON/OFF
Prescaler
/1,/2,/4,...,/64
pck[..]
USB Clock Controller
ON/OFF
PLLBCK
UDPCK
The SysTick calibration value is fixed at 12500, which allows the generation of a time base of
1 ms with SysTick clock at 12.5 MHz (max HCLK/8 = 100 MHz/8 = 12500, so STCALIB =
0x30D4).
10.7
Watchdog Timer
• 16-bit key-protected only-once Programmable Counter
• Windowed, prevents the processor to be in a deadlock on the watchdog access
10.8
SysTick Timer
• 24-bit down counter
• Self-reload capability
• Flexible System timer
44
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
10.9
Real-Time Timer
• Real-Time Timer, allowing backup of time with different accuracies
– 32-bit Free-running backup Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm Register capable to generate a wake-up of the system through the Shut Down
Controller
10.10 Real Time Clock
• Low power consumption
• Full asynchronous design
• Two hundred year Gregorian and Persian calendar
• Programmable Periodic Interrupt
• Trimmable 32.7682 kHz crystal oscillator clock source
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
• Waveform output capability on GPIO pins in low power modes
10.11 General-Purpose Backup Registers
• Eight 32-bit backup general-purpose registers
10.12 Nested Vectored Interrupt Controller
• Thirty maskable external interrupts
• Sixteen priority levels
• Processor state automatically saved on interrupt entry, and restored on
• Dynamic reprioritizing of interrupts
• Priority grouping.
– selection of pre-empting interrupt levels and non pre-empting interrupt levels.
• Support for tail-chaining and late arrival of interrupts.
– back-to-back interrupt processing without the overhead of state saving and
restoration between interrupts.
• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no
instruction overhead.
45
11100BS–ATARM–31-Jul-12
10.13 Chip Identification
• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
Table 10-1.
SAM4S Chip IDs Register
Chip Name
Flash Size
(Kbytes)
RAM Size
(Kbytes)
Pin Count
CHIPID_CIDR
SAM4SD32C
2*1024
160
100
0X29A7_0EE0
SAM4SD32B
2*1024
160
64
0X2997_0EE0
SAM4SD16C
2*512
160
100
0X29A7_0CE0
SAM4SD16B
2*512
160
64
0X2997_0CE0
SAM4SA16C
1024
160
100
0X28A7_0CE0
0x0
SAM4SA16B
1024
160
64
0X2897_0CE0
0x0
SAM4S16B
1024
128
64
0x289C_0CE0
0x0
SAM4S16C
1024
128
100
0x28AC_0CE0
0x0
SAM4S8B
512
128
64
0x289C_0AE0
0x0
SAM4S8C
512
128
100
0x28AC_0AE0
0x0
CHIPID_EXID
• JTAG ID: 05B3_203F
10.14 PIO Controllers
• 3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79
I/O Lines
• Each PIO Controller controls up to 32 programmable I/O Lines
• Fully programmable through Set/Clear Registers
Table 10-2.
PIO available according to pin count
Version
64 pin
100 pin
PIOA
32
32
PIOB
15
15
PIOC
-
32
• Multiplexing of four peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change interrupt
– Programmable Glitch filter
– Programmable debouncing filter
– Multi-drive option enables driving in open drain
– Programmable pull-up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
– Additional interrupt modes on a programmable event: rising edge, falling edge, low
level or high level
– Lock of the configuration by the connected peripheral
• Synchronous output, provides set and clear of several I/O lines in a single write
46
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
• Write Protect Registers
• Programmable Schmitt trigger inputs
• Parallel capture mode
– Can be used to interface a CMOS digital image sensor, an ADC....
– One clock, 8-bit parallel data and two data enable on I/O lines
– Data can be sampled one time out of two (for chrominance sampling only)
– Supports connection of one Peripheral DMA Controller channel (PDC) which offers
buffer reception without processor intervention
10.15 Peripheral Identifiers
Table 10-3 defines the Peripheral Identifiers of the SAM4S. A peripheral identifier is required for
the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of
the peripheral clock with the Power Management Controller.
Table 10-3.
Peripheral Identifiers
PMC
Clock Control
Instance ID
Instance Name
NVIC Interrupt
Instance Description
0
SUPC
X
Supply Controller
1
RSTC
X
Reset Controller
2
RTC
X
Real Time Clock
3
RTT
X
Real Time Timer
4
WDT
X
Watchdog Timer
5
PMC
X
Power Management Controller
6
EEFC0
X
Enhanced Embedded Flash Controller 0
7
EEFC1
-
Enhanced Embedded Flash Controller 1
8
UART0
X
X
UART 0
9
UART1
X
X
UART 1
10
SMC
X
X
Static Memory Controller
11
PIOA
X
X
Parallel I/O Controller A
12
PIOB
X
X
Parallel I/O Controller B
13
PIOC
X
X
Parallel I/O Controller C
14
USART0
X
X
USART 0
15
USART1
X
X
USART 1
16
-
-
-
Reserved
17
-
-
-
Reserved
18
HSMCI
X
X
Multimedia Card Interface
19
TWI0
X
X
Two Wire Interface 0
20
TWI1
X
X
Two Wire Interface 1
21
SPI
X
X
Serial Peripheral Interface
22
SSC
X
X
Synchronous Serial Controller
23
TC0
X
X
Timer/Counter 0
47
11100BS–ATARM–31-Jul-12
Table 10-3.
Peripheral Identifiers (Continued)
Instance ID
Instance Name
NVIC Interrupt
PMC
Clock Control
24
TC1
X
X
Timer/Counter 1
25
TC2
X
X
Timer/Counter 2
26
TC3
X
X
Timer/Counter 3
27
TC4
X
X
Timer/Counter 4
28
TC5
X
X
Timer/Counter 5
29
ADC
X
X
Analog To Digital Converter
30
DACC
X
X
Digital To Analog Converter
31
PWM
X
X
Pulse Width Modulation
32
CRCCU
X
X
CRC Calculation Unit
33
ACC
X
X
Analog Comparator
34
UDP
X
X
USB Device Port
Instance Description
10.16 Peripheral Signal Multiplexing on I/O Lines
The SAM4S features 2 PIO controllers on 64-pin version (PIOA and PIOB) or 3 PIO controllers
on the 100-pin version (PIOA, PIOB and PIOC), that multiplex the I/O lines of the peripheral set.
The SAM4S 64-pin and 100-pin PIO Controllers control up to 32 lines. Each line can be
assigned to one of three peripheral functions: A, B or C. The multiplexing tables in the following
paragraphs define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO
Controllers. The column “Comments” has been inserted in this table for the user’s own comments; it may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the tables.
48
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
10.16.1
PIO Controller A Multiplexing
Table 10-4.
I/O Line
Multiplexing on PIO Controller A (PIOA)
Peripheral A
Peripheral B
Peripheral C
Extra Function
PA0
PWMH0
TIOA0
A17
WKUP0
PA1
PWMH1
TIOB0
A18
WKUP1
PA2
PWMH2
SCK0
DATRG
WKUP2
PA3
TWD0
NPCS3
PA4
TWCK0
TCLK0
WKUP3
PA5
RXD0
NPCS3
WKUP4
PA6
TXD0
PCK0
PA7
RTS0
PWMH3
PA8
CTS0
ADTRG
PA9
URXD0
NPCS1
PA10
UTXD0
NPCS2
PA11
NPCS0
PWMH0
PA12
MISO
PWMH1
PA13
MOSI
PWMH2
PA14
SPCK
PWMH3
PA15
TF
TIOA1
PWML3
WKUP14/PIODCEN1
PA16
TK
TIOB1
PWML2
WKUP15/PIODCEN2
PA17
TD
PCK1
PWMH3
AD0
PA18
RD
PCK2
A14
AD1
PA19
RK
PWML0
A15
AD2/WKUP9
PA20
RF
PWML1
A16
AD3/WKUP10
PA21
RXD1
PCK1
PA22
TXD1
NPCS3
PA23
SCK1
PA24
System Function
Comments
XIN32
WKUP5
PWMFI0
XOUT32
WKUP6
WKUP7
WKUP8
AD8
64/100 pins versions
NCS2
AD9
64/100 pins versions
PWMH0
A19
PIODCCLK
64/100 pins versions
RTS1
PWMH1
A20
PIODC0
64/100 pins versions
PA25
CTS1
PWMH2
A23
PIODC1
64/100 pins versions
PA26
DCD1
TIOA2
MCDA2
PIODC2
64/100 pins versions
PA27
DTR1
TIOB2
MCDA3
PIODC3
64/100 pins versions
PA28
DSR1
TCLK1
MCCDA
PIODC4
64/100 pins versions
PA29
RI1
TCLK2
MCCK
PIODC5
64/100 pins versions
PA30
PWML2
NPCS2
MCDA0
WKUP11/PIODC6
64/100 pins versions
PA31
NPCS1
PCK2
MCDA1
PIODC7
64/100 pins versions
49
11100BS–ATARM–31-Jul-12
10.16.2
PIO Controller B Multiplexing
Table 10-5.
I/O
Line
Multiplexing on PIO Controller B (PIOB)
Peripheral A
Peripheral B
Peripheral C
Extra Function
PB0
PWMH0
AD4/RTCOUT0
PB1
PWMH1
AD5/RTCOUT1
PB2
URXD1
NPCS2
AD6/WKUP12
PB3
UTXD1
PCK2
AD7
PB4
TWD1
PWMH2
PB5
TWCK1
PWML0
System Function
Comments
TDI
WKUP13
TDO/TRACESWO
PB6
TMS/SWDIO
PB7
TCK/SWCLK
PB8
XOUT
PB9
XIN
PB10
DDM
PB11
DDP
PB12
PWML1
PB13
PWML2
PCK0
DAC0
64/00 pins versions
PB14
NPCS1
PWMH3
DAC1
64/100 pins versions
50
ERASE
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
10.16.3
PIO Controller C Multiplexing.
Table 10-6.
I/O Line
Multiplexing on PIO Controller C (PIOC)
System
Function
Peripheral B
PC0
D0
PWML0
100 pin version
PC1
D1
PWML1
100 pin version
PC2
D2
PWML2
100 pin version
PC3
D3
PWML3
100 pin version
PC4
D4
NPCS1
100 pin version
PC5
D5
100 pin version
PC6
D6
100 pin version
PC7
D7
100 pin version
PC8
NWE
100 pin version
PC9
NANDOE
100 pin version
PC10
NANDWE
100 pin version
PC11
NRD
100 pin version
PC12
NCS3
PC13
NWAIT
PC14
NCS0
PC15
NCS1
PC16
A21/NANDALE
100 pin version
PC17
A22/NANDCLE
100 pin version
PC18
A0
PWMH0
100 pin version
PC19
A1
PWMH1
100 pin version
PC20
A2
PWMH2
100 pin version
PC21
A3
PWMH3
100 pin version
PC22
A4
PWML3
100 pin version
PC23
A5
TIOA3
100 pin version
PC24
A6
TIOB3
100 pin version
PC25
A7
TCLK3
100 pin version
PC26
A8
TIOA4
100 pin version
PC27
A9
TIOB4
100 pin version
PC28
A10
TCLK4
100 pin version
PC29
A11
TIOA5
AD13
100 pin version
PC30
A12
TIOB5
AD14
100 pin version
PC31
A13
TCLK5
PWML0
Peripheral C
Extra
Function
Peripheral A
Comments
AD12
100 pin version
AD10
100 pin version
100 pin version
PWML1
AD11
100 pin version
100 pin version
51
11100BS–ATARM–31-Jul-12
11. Embedded Peripherals Overview
11.1
Serial Peripheral Interface (SPI)
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash® and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Connection to PDC channel capabilities optimizes data transfers
– One channel for the receiver, one channel for the transmitter
– Next buffer support
11.2
Two Wire Interface (TWI)
• Master, Multi-Master and Slave Mode Operation
• Compatibility with Atmel two-wire interface, serial memory and I2C compatible devices
• One, two or three bytes for slave address
• Sequential read/write operations
• Bit Rate: Up to 400 kbit/s
• General Call Supported in Slave Mode
• Connecting to PDC channel capabilities optimizes data transfers in Master Mode only
– One channel for the receiver, one channel for the transmitter
– Next buffer support
11.3
Universal Asynchronous Receiver Transceiver (UART)
• Two-pin UART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
52
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
11.4
USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
– Full modem line support on USART1 (DCD-DSR-DTR-RI)
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
• SPI Mode
– Master or Slave
– Serial Clock programmable Phase and Polarity
– SPI Serial Clock (SCK) Frequency up to MCK/4
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
11.5
Synchronous Serial Controller (SSC)
• Provides serial synchronous communication links used in audio and telecom applications
(with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader)
• Contains an independent receiver and transmitter and a common clock divider
• Offers configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
11.6
Timer Counter (TC)
• Six 16-bit Timer Counter Channels
• Wide range of functions including:
– Frequency Measurement
– Event Counting
53
11100BS–ATARM–31-Jul-12
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Two global registers that act on all three TC Channels
• Quadrature decoder
– Advanced line filtering
– Position / revolution / speed
• 2-bit Gray Up/Down Counter for Stepper Motor
11.7
Pulse Width Modulation Controller (PWM)
• One Four-channel 16-bit PWM Controller, 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– High Frequency Asynchronous clocking mode
• Independent channel programming
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Independent Output Override for each channel
– Independent complementary Outputs with 12-bit dead time generator for each
channel
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
• Synchronous Channel mode
– Synchronous Channels share the same counter
– Mode to update the synchronous channels registers after a programmable number
of periods
• Connection to one PDC channel
– Provides Buffer transfer without processor intervention, to update duty cycle of
synchronous channels
• Two independent event lines which can send up to 4 triggers on ADC within a period
54
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
• One programmable Fault Input providing an asynchronous protection of outputs
• Stepper motor control (2 Channels)
11.8
High Speed Multimedia Card Interface (HSMCI)
• 4-bit or 1-bit Interface
• Compatibility with MultiMedia Card Specification Version 4.3
• Compatibility with SD and SDHC Memory Card Specification Version 2.0
• Compatibility with SDIO Specification Version V1.1.
• Compatibility with CE-ATA Specification 1.1
• Cards clock rate up to Master Clock divided by 2
• Boot Operation Mode support
• High Speed mode support
• Embedded power management to slow down clock rate when not used
• MCI has one slot supporting
– One MultiMediaCard bus (up to 30 cards) or
– One SD Memory Card
– One SDIO Card
• Support for stream, block and multi-block data read and write
11.9
USB Device Port (UDP)
• USB V2.0 full-speed compliant,12 Mbits per second.
• Embedded USB V2.0 full-speed transceiver
• Embedded 2688-byte dual-port RAM for endpoints
• Eight endpoints
– Endpoint 0: 64bytes
– Endpoint 1 and 2: 64 bytes ping-pong
– Endpoint 3: 64 bytes
– Endpoint 4 and 5: 512 bytes ping-pong
– Endpoint 6 and 7: 64 bytes ping-pong
– Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints
• Suspend/resume logic
• Integrated Pull-up on DDP
• Pull-down resistor on DDM and DDP when disabled
11.10 Analog-to-Digital Converter (ADC12B)
• up to 16 Channels, 12-bit ADC
• 10/12-bit resolution
• up to 1 MSample/s
• Programmable conversion sequence conversion on each channel
• Integrated temperature sensor
• Automatic calibration mode
55
11100BS–ATARM–31-Jul-12
• Single ended/differential conversion
• Programmable gain: 1, 2, 4
11.11 Digital-to-Analog Converter (DAC)
• Up to 2 channel 12-bit DAC
• Up to 2 mega-samples conversion rate in single channel mode
• Flexible conversion range
• Multiple trigger sources for each channel
• 2 Sample/Hold (S/H) outputs
• Built-in offset and gain calibration
• Possible to drive output to ground
• Possible to use as input to analog comparator or ADC (as an internal wire and without S/H
stage)
• Two PDC channels
• Power reduction mode
11.12 Static Memory Controller
• 16-Mbyte Address Space per Chip Select
• 8- bit Data Bus
• Word, Halfword, Byte Transfers
• Byte Write or Byte Select Lines
• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
• Programmable Data Float Time per Chip Select
• Compliant with LCD Module
• External Wait Request
• Automatic Switch to Slow Clock Mode
• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
• NAND Flash additional logic supporting NAND Flash with Multiplexed Data/Address buses
• Hardware Configurable number of chip select from 1 to 4
• Programmable timing on a per chip select basis
11.13 Analog Comparator
• One analog comparator
• High speed option vs. low-power option
– 170 µA/xx ns active current consumption/propagation delay
– 20 µA/xx ns active current consumption/propagation delay
• Selectable input hysteresis
– 0, 15 mV, 30mV (Typ)
• Minus input selection:
– DAC outputs
56
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
– Temperature Sensor
– ADVREF
– AD0 to AD3 ADC channels
• Plus input selection:
– All analog inputs
• output selection:
– Internal signal
– external pin
– selectable inverter
• window function
• Interrupt on:
– Rising edge, Falling edge, toggle
– Signal above/below window, signal inside/outside window
11.14 Cyclic Redundancy Check Calculation Unit (CRCCU)
• 32-bit cyclic redundancy check automatic calculation
• CRC calculation between two addresses of the memory
57
11100BS–ATARM–31-Jul-12
12. Package Drawings
The SAM4S series devices are available in LQFP, QFN, TFBGA and VFBGA packages.
Figure 12-1. 100-lead LQFP Package Mechanical Drawing
Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
58
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 12-2. 100-ball TFBGA Package Mechanical Drawing
59
11100BS–ATARM–31-Jul-12
Figure 12-3. 100-ball VFBGA Package Drawing
60
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 12-4. 64-lead LQFP Package Mechanical Drawing
61
11100BS–ATARM–31-Jul-12
Figure 12-5. 64-lead QFN Package Mechanical Drawing
62
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
13. Ordering Information
Table 13-1.
Ordering Codes for SAM4S Devices
Ordering Code
MRL
Flash
(Kbytes)
Package
Package Type
Temperature
Operating Range
ATSAM4SD32CA-CU
A
2*1024
TFBGA100
Green
Industrial
(-40°C to +85°C)
ATSAM4SD32CA-CFU
A
2*1024
VFBGA100
Green
Industrial
(-40°C to +85°C)
ATSAM4SD32CA-AU
A
2*1024
LQFP100
Green
Industrial
(-40°C to +85°C)
ATSAM4SD32BA-MU
A
2*1024
QFN64
Green
Industrial
(-40°C to +85°C)
ATSAM4SD32BA-AU
A
2*1024
LQFP64
Green
Industrial
(-40°C to +85°C)
ATSAM4SD16CA-CU
A
2*512
TFBGA100
Green
Industrial
(-40°C to +85°C)
ATSAM4SD16CA-CFU
A
2*512
VFBGA100
Green
Industrial
(-40°C to +85°C)
ATSAM4SD16CA-AU
A
2*512
LQFP100
Green
Industrial
(-40°C to +85°C)
ATSAM4SD16BA-MU
A
2*512
QFN64
Green
Industrial
(-40°C to +85°C)
ATSAM4SD16BA-AU
A
2*512
LQFP64
Green
Industrial
(-40°C to +85°C)
ATSAM4SA16CA-CU
A
1024
TFBGA100
Green
Industrial
(-40°C to +85°C)
ATSAM4SA16CA-CFU
A
1024
VFBGA100
Green
Industrial
(-40°C to +85°C)
ATSAM4SA16CA-AU
A
1024
LQFP100
Green
Industrial
(-40°C to +85°C)
ATSAM4SA16BA-MU
A
1024
QFN64
Green
Industrial
(-40°C to +85°C)
ATSAM4SA16BA-AU
A
1024
LQFP64
Green
Industrial
(-40°C to +85°C)
ATSAM4S16CA-CU
A
1024
TFBGA100
Green
Industrial
(-40°C to +85°C)
ATSAM4S16CA-CFU
A
1024
VFBGA100
Green
Industrial
(-40°C to +85°C)
ATSAM4S16CA-AU
A
1024
LQFP100
Green
Industrial
(-40°C to +85°C)
ATSAM4S16BA-MU
A
1024
QFN64
Green
Industrial
(-40°C to +85°C)
ATSAM4S16BA-AU
A
1024
LQFP64
Green
Industrial
(-40°C to +85°C)
63
11100BS–ATARM–31-Jul-12
Table 13-1.
Ordering Codes for SAM4S Devices
Ordering Code
MRL
Flash
(Kbytes)
Package
Package Type
ATSAM4S8CA-CU
A
512
TFBGA100
Green
Industrial
(-40°C to +85°C)
ATSAM4S8CA-CFU
A
512
VFBGA100
Green
Industrial
(-40°C to +85°C)
ATSAM4S8CA-AU
A
512
LQFP100
Green
Industrial
(-40°C to +85°C)
ATSAM4S8BA-MU
A
512
QFN64
Green
Industrial
(-40°C to +85°C)
ATSAM4S8BA-AU
A
512
LQFP64
Green
Industrial
(-40°C to +85°C)
64
Temperature
Operating Range
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Revision History
In the table that follows, the most recent version of the document appears first.
“rfo” indicates changes requested during document review and approval loop.
Doc. Rev
11100BS
Comments
48-pin package references removed from Section “Features”, Section 1. “Description”, Section 1.1
“Configuration Summary” (updated Table 1-1), Section 2. “Block Diagram” (deleted Fig. 2-3), Section 4.
“Package and Pinout” (deleted the entire section 4.3 SAM4S16/S8A Package and Pinout), Section 10.13
“Chip Identification” (updated Table 10-1), Section 10.14 “PIO Controllers” (updated Table 10-2), Section
10.16 “Peripheral Signal Multiplexing on I/O Lines”, Section 12. “Package Drawings” (deleted Fig. 12-5
and Fig. 12-6).
VFBGA100 package information added to Section “Features”, Section 1.1 “Configuration Summary”
(updated Table 1-1), and Section 4.1 “SAM4SD32/SD16/SA16/S16/S8C Package and Pinout” (added
Figure 4-3 and Table 4-3).
References to WFE instructions replaced by relevant bits precise descriptions in Section 5.5 “Low-Power
Modes”.
SRAM upper address changed to 0x20400000 in Figure 8-1 on page 32.
New devices features added in Section 9.1.1 “Internal SRAM”Section 9.1.3.1 “Flash Overview”,Section
9.1.3.4 “Lock Regions”, Section 9.1.3.5 “Security Bit Feature”, Section 9.1.3.11 “GPNVM Bits”, and Table
10-1 on page 46.
Note added in Section 9.1.3.1 “Flash Overview”.
Table 10-3 updated in Section 10.15 “Peripheral Identifiers”.
Dual bank and cache memory references added to Section “Features” and Section 1. “Description”.
Deleted LFBGA references from Section “Features” and Section 1. “Description” (updated Table 1-1).
Section 2. “Block Diagram”: added references to SAM4S16/S8 and SAM4SD16/SA16 in the figure titles,
updated Figure 2-3 for colors, and added Figure 2-4, "SAM4SD32/SD16/SA16 64-pin version Block
Diagram".
Section 12. “Package Drawings”: updated the introduction text and added Figure 12-3, "100-ball VFBGA
Package Drawing".
Section 13. “Ordering Information”: updated the headings row and added new rows with the
SAM4SD32/SD16/A16/16/8 features in Table 13-1.
Consumption data updated in Section “Features”, Section 5.2 “Voltage Regulator”, Section 5.5.1 “Backup
Mode”, Section 5.5.2 “Wait Mode”, and in Section 5.5.4 “Low Power Mode Summary Table”(Table 5-1 and
the corresponding footnotes).
Added 2 KB cache information in Figure 2-3, "SAM4SD32/SD16/SA16 100-pin version Block Diagram"
and Figure 2-4, "SAM4SD32/SD16/SA16 64-pin version Block Diagram".
Changed the temperature operating range (+105°C replaced with +85°C) in Section 13. “Ordering
Information”.
Section 6.1 “General Purpose I/O Lines”, updated electrical characteristics for I/O lines.
Section 9.1.3.1 “Flash Overview”, added Internal Flash addresses in the description of Flash size (Figure 93).
Section 9.1.3.11 “GPNVM Bits”, updated bits information (SAM4S16/SA16 and SAM4S8).
Deleted the entire section 10.14 UART.
Section 10.15 “Peripheral Identifiers”, updated information for EEFC0 and EEFC1 in Table 10-3 on page
47.
Section “Features”, added “Write Protected Registers” to thePeripherals list.
Section 2. “Block Diagram”, replaced “Time Counter B” by “Time Counter A” in Figure 2-1 on page 4.
Specified the preliminary status of the datasheet.
Change
Request
Ref.
8099
rfo
rfo
rfo
rfo
rfo
rfo
8213
rfo
rfo
65
11100BS–ATARM–31-Jul-12
Doc. Rev
11100AS
Comments
Change
Request
Ref.
Initial release.
66
SAM4S Series [Preliminary]
11100BS–ATARM–31-Jul-12
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: (+1) (408) 441-0311
Fax: (+1) (408) 487-2600
Atmel Asia Limited
Unit 01-5 & 16, 19F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
HONG KONG
Tel: (+852) 2245-6100
Fax: (+852) 2722-1369
Atmel Munich GmbH
Business Campus
Parkring 4
D-85748 Garching b. Munich
GERMANY
Tel: (+49) 89-31970-0
Fax: (+49) 89-3194621
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
JAPAN
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Technical Support
AT91SAM Support
Atmel technical support
Sales Contacts
www.atmel.com/contacts/
Product Contact
Web Site
www.atmel.com
www.atmel.com/AT91SAM
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted
for use as components in applications intended to support or sustain life.
© 2012 Atmel Corporation. All rights reserved. Atmel ®, Atmel logo and combinations thereof, QTouch ®, DataFlash ®, SAM-BA ® and others are
registered trademarks or trademarks of Atmel Corporation or its subsidiaries.Windows® and others, are registered trademarks or trademarks of
Microsoft Corporation in the US and/or other countries. ARM ®, ARM ®Powered logo, Cortex ®, Thumb ®-2 and others are registered trademarks or
trademarks of ARM Ltd. Other terms and product names may be trademarks of others.
11100BS–ATARM–31-Jul-12
Similar pages