ON NCP7662P Inductorless voltage converter Datasheet

NCP7662
Inductorless Voltage
Converter
The NCP7662 is a pin–compatible upgrade to the industry standard
TC7660 charge pump voltage converter. It converts a +1.5 V to +15 V
input to a corresponding –1.5 to –15 V output using only two low–cost
capacitors, eliminating inductors and their associated cost, size and
EMI.
The on–board oscillator operates at a nominal frequency of 10 kHz.
Frequency is increased to 35 kHz when pin 1 is connected to V+,
allowing the use of smaller external capacitors. Operation below 10 kHz
(for lower supply current applications) is also possible by connecting an
external capacitor from OSC to ground (with pin 1 open).
The NCP7662 is available in both 8–pin DIP and 8–pin small outline
(SO) packages in commercial and extended temperature ranges.
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MARKING
DIAGRAMS
8
8
1
1
Features
•
Wide Operating Voltage Range: 1.5 V to 15 V
Boost Pin (Pin 1) for Higher Switching Frequency
High Power Efficiency is 96%
Easy to Use – Requires Only 2 External Non–Critical Passive
Components
Improved Direct Replacement for Industry Standard ICL7660 and
Other Second Source Devices
Applications
•
•
•
•
•
"
"
Simple Conversion of +5 V to 5 V Supplies
Voltage Multiplication VOUT = nVIN
Negative Supplies for Data Acquisition Systems and Instrumentation
RS232 Power Supplies
Supply Splitter, VOUT = VS/2
"
8
NCP7662
YYWWXZ
CO
PDIP–8
P SUFFIX
CASE 626
8
1
1
YY, Y
WW
X
Z
CO
= Year
= Work Week
= Assembly ID Code
= Subcontractor ID Code
= Country of Orgin
PIN CONNECTIONS
BOOST 1
CAP+ 2
GND 3
CAP– 4
8 V+
NCP7662
•
•
•
•
NCP
7662
YWWXZ
SO–8
D SUFFIX
CASE 751
7 OSC
6 LOW
VOLTAGE (LV)
5 VOUT
ORDERING INFORMATION
Device
NCP7662DR2
NCP7662P
 Semiconductor Components Industries, LLC, 2000
June, 2000 – Rev. 0
1
Package
Shipping
SO–8
2500 Tape & Reel
PDIP–8
50 Units/Rail
Publication Order Number:
NCP7662/D
NCP7662
Functional Block Diagram
V+
CAP +
8
BOOST
1
7
RC
OSCILLATOR
OSC
LV
2
B2
4
VOLTAGE
LEVEL
TRANSLATOR
6
CAP –
5
V OUT
INTERNAL
VOLTAGE
REGULATOR
LOGIC
NETWORK
NCP7662
3
GND
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Supply Voltage
LV, Boost and OSC Inputs Voltage (Note 1.)
V+
5.5 V
5.5 V
u
Value
Unit
+16.5
V
V
t
–0.3 V to (V+ + 0.3 V)
(V+ –5.5 V) to (V+ + 0.3 V)
Current into LV (Note 1.)
V+
3.5 V
u
Output Short Duration
(VSUPPLY
5.5 V)
v
Power Dissipation (Note 2.)
Plastic DIP
SO
20
µA
Continuous
V
mW
730
470
Operating Temperature Range
–40 to +85
°C
Storage Temperature Range
–65 to +150
°C
+300
°C
Lead Temperature (Soldering, 10 sec)
Static–sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses
above those listed under “Absolute Maximum Ratings’’ may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latch–up. It is recommended that no inputs
from sources operating from external supplies be applied prior to “power up’’ of the NCP7662.
2. Derate linearly above 50°C by 5.5 mW/°C.
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2
NCP7662
ELECTRICAL CHARACTERISTICS (V+ = 5 V, TA = +25°C, OSC = Free running, Test Circuit Figure 2, unless otherwise specified.)
Characteristics
Supply Current (Note 3.)
(Boost Pin OPEN or GND)
Supply Current
(Boost Pin = V+)
Supply Voltage Range, High (Note 4.)
Supply Voltage Range, Low
Output Source Resistance
Test Conditions
Symbol
Min
Typ
Max
Unit
RL = ∞, +25°C
0°C
TA
+70°C
–40°C
TA
+85°C
I+
–
80
160
µA
–
–
180
–
–
180
–
–
300
–
–
350
v v
v v
0°C v TA v +70°C
–40°C v TA v +85°C
I+
RL = 10 kΩ,
LV Open, TMIN
TA
V+H
3.0
–
15
V
RL = 10 kΩ,
LV to GND, TMIN
TA
V+L
1.5
–
3.5
V
ROUT
–
65
100
Ω
v v TMAX
v v TMAX
IOUT = 20 mA, 0°C v TA v +70°C
IOUT = 20 mA, –40°C v TA v +85°C
–
–
120
IOUT = 3 mA, V+ = 2 V, LV to GND,
0°C
TA
+70°C
–
–
250
IOUT = 3 mA, V+ = 2 V, LV to GND,
–40°C
TA
+85°C
–
–
300
v v
v v
Oscillator Frequency
µA
COSC = 0, Pin 1 Open or GND
Pin 1 = V+
fOSC
5.0
–
10
35
–
–
kHz
RL = 5 kΩ,
TMIN
TA
TMAX
v v
PEff
96
96
–
%
95
97
–
Voltage Conversion Efficiency
RL = ∞
VOUTEff
99
99.9
–
%
Oscillator Impedance
V+ = 2 V
V+ = 5 V
ZOSC
–
–
1.0
100
–
–
MΩ
kΩ
Power Efficiency
3. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a
very small but finite stray capacitance present, of the order of 5 pF.
4. The NCP7662 can operate without an external diode over the full temperature and voltage range. This device will function in existing designs
which incorporate an external diode with no degradation in overall circuit performance.
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3
NCP7662
DETAILED DESCRIPTION
THEORETICAL POWER EFFICIENCY
CONSIDERATIONS
The NCP7662 contains all the necessary circuitry to
complete a negative voltage converter, with the exception of
two external capacitors which may be inexpensive 1 µF
polarized electrolytic types. The mode of operation of the
device may be best understood by considering Figure 2,
which shows an idealized negative voltage converter.
Capacitor C1 is charged to a voltage V+ for the half cycle
when switches S1 and S3 are closed. (Note: Switches S2 and
S4 are open during this half cycle.) During the second half
cycle of operation, switches S2 and S4 are closed, with S1
and S3 open, thereby shifting capacitor C1 negatively by V+
volts. Charge is then transferred from C1 to C2 such that the
voltage on C2 is exactly V+, assuming ideal switches and no
load on C2. The NCP7662 approaches this ideal situation
more closely than existing non–mechanical circuits.
In the NCP7662 the four switches of Figure 2 are MOS
power switches; S1 is a P–channel device and S2, S3 and S4
are N–channel devices. The main difficulty with this
approach is that in integrating the switches, the substrates of
S3 and S4 must always remain reverse biased with respect to
their sources, but not so much as to degrade their “ON’’
resistances. In addition, at circuit start up, and under output
short circuit conditions (VOUT = V+), the output voltage
must be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.
The problem is eliminated in the NCP7662 by a logic
network which senses the output voltage (VOUT) together
with the level translators, and switches the substrates of S3
and S4 to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the NCP7662 is an
integral part of the anti–latchup circuitry; however, its
inherent voltage drop can degrade operation at low voltages.
Therefore, to improve low voltage operation, the “LV’’ pin
should be connected to GND, disabling the regulator. For
supply voltages greater than 3.5 volts, the LV terminal must
be left open to insure latchup proof operation and prevent
device damage.
1
2
C1
10 µF
+
3
4
NCP7662
V+
8
7
In theory, a voltage converter can approach 100%
efficiency if certain conditions are met:
A. The drive circuitry consumes minimal power.
B. The output switches have extremely low ON resistance
and virtually no offset.
C. The impedances of the pump and reservoir capacitors
are negligible at the pump frequency.
The NCP7662 approaches these conditions for negative
voltage conversion if large values of C1 and C2 are used.
Energy is lost only in the transfer of charge between
capacitors if a change in voltage occurs. The energy lost
is defined by:
E = 1/2 C1 (V12 – V22)
where V1 and V2 are the voltages on C1 during the pump and
transfer cycles. If the impedances of C1 and C2 are relatively
high at the pump frequency (refer to Figure 2) compared to
the value of RL, there will be a substantial difference in
voltages V1 and V2. Therefore, it is desirable not only to
make C2 as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
C1 in order to achieve maximum efficiency of operation.
Dos and Don’ts
1. Do not exceed maximum supply voltages.
2. Do not connect the LV terminal to GND for supply
voltages greater than 3.5 volts.
3. Do not short circuit the output to V+ supply for voltages
above 5.5 volts for extended periods; however, transient
conditions including start–up are okay.
4. When using polarized capacitors in the inverting mode,
the + terminal of C1 must be connected to pin 2 of the
NCP7662 and the – terminal of C2 must be connected to
GND.
5. If the voltage supply driving the NCP7662 has a large
source impedance (25–30 ohms), then a 2.2 µF capacitor
from pin 8 to ground may be required to limit the rate of
rise of the input voltage to less than 2 V/µs.
V IN
IS
S1
V+
I L (+5 V)
S2
C1
6
5
RL
S3
VO
S4
C2
V OUT = – VIN
C2
+ 10 µF
Figure 2. Idealized Negative Voltage Capacitor
Figure 1. Test Circuit
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NCP7662
TYPICAL APPLICATIONS
R
O
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
NCP7662 for generation of negative supply voltages.
Figure 3 shows typical connections to provide a negative
supply where a positive supply of +1.5 V to +15 V is
available. Keep in mind that pin 6 (LV) is tied to the supply
negative (GND) for supply voltages below 3.5 volts.
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(fPUMP
C1) term,
rendering an increase in switching frequency or filter
capacitance ineffective. Typical electrolytic capacitors may
have ESRs as high as 10 Ω.
V+
+
–
1
8
NCP7662
10 µF
2
3
7
5
4
10 µF
Output Ripple
RO
6
VOUT = –V+
–
+
(a)
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown
in Figure 4. Segment A is the voltage drop across the ESR
of C2 at the instant it goes from being charged by C1 (current
flowing into C2) to being discharged through the load
(current flowing out of C2). The magnitude of this current
change is 2
IOUT, hence the total drop is 2
IOUT
ESRC2 volts. Segment B is the voltage change across C2
during time t2, the half of the cycle when C2 supplies current
to the load. The drop at B is IOUT
t2/C2 volts. The
peak–to–peak ripple voltage is the sum of these voltage
drops:
VOUT
–
V+
+
(b)
Figure 3. Simple Negative Converter
and its Output Equivalent
The output characteristics of the circuit in Figure 3 can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 3b. The voltage source has a
value of –(V+). The output impedance (RO) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 2), the switching frequency, the value of C1 and C2,
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for RO is:
R
O
V
RIPPLE
^
ǒ
1
2
f
^ 2(RSW1 ) RSW3 ) ESRC1) ) 2(RSW2 ) RSW4
) ESRC1) ) f 1 C ) ESRC2
PUMP
(f
^ 2 23 ) 5 103 110 10–6)
) 4 ESRC1 ) ESRC2
R ^ (46 ) 20 ) 5 ESR ) Ω
O
C
+
PUMP
f
OSC , R
SWX
2
t2
^2
R
)
SW f
0
+ MOSFET switch resistance)
1
PUMP
) ESRC2Ω
C2
) ESRC2
I
Ǔ
OUT
t1
1
B
V
Combining the four RSWX terms as RSW, we see that:
R
O
PUMP
C1
)4
ESR
A
–(V+)
C1
Figure 4. Output Ripple
RSW, the total switch resistance, is a function of supply
voltage and temperature (see the Output Source Resistance
graphs), typically 23 Ω at +25°C and 5 V. Careful selection
of C1 and C2 will reduce the remaining terms, minimizing
the output impedance. High value capacitors will reduce the
1/(fPUMP C1) component, and low ESR capacitors will
lower the ESR term. Increasing the oscillator frequency will
reduce the 1/(fPUMP
C1) term, but may have the side
effect of a net increase in output impedance when C1
10 µF and there is not enough time to fully charge the
capacitors every cycle. In a typical application when fOSC =
10 kHz and C = C1 = C2 = 10 µF:
Paralleling Devices
Any number of NCP7662 voltage converters may be
paralleled to reduce output resistance (Figure 5). The
reservoir capacitor, C2, serves all devices, while each device
requires its own pump capacitor, C1. The resultant output
resistance would be approximately:
OUT
+ n (number
of devices)
R
u
R
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5
OUT
(of NCP7662)
NCP7662
V+
+
–
3
7
1
6
2
5
4
C1
+
–
NCP7662
2
C1
shown in Figure 7. In order to prevent device latchup, a 1 kΩ
resistor must be used in series with the clock output. In a
situation where the designer has generated the external clock
frequency using TTL logic, the addition of a 10 kΩ pullup
resistor to V+ supply is required. Note that the pump
frequency with external clocking, as with internal clocking,
will be 1/2 of the clock frequency. Output transitions occur
on the positive–going edge of the clock.
8
NCP7662
1
3
4
8
RL
7
6
5
C2
+
V+
Figure 5. Paralleling Devices
2
10 µF
+
3
Cascading Devices
+ * n(VIN)
4
“1”
5
7
6
1
10 µF +
2
3
4
*VOUT = –nV+
NCP7662
3
NCP7662
2
8
8
It is also possible to increase the conversion efficiency of
the NCP7662 at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 8. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the pump
(C1) and reservoir (C2) capacitors; this is overcome by
increasing the values of C1 and C2 by the same factor that the
frequency has been reduced. For example, the addition of a
100 pF capacitor between pin 7 (Osc) and V+ will lower the
oscillator frequency to 1 kHz from its nominal frequency of
10 kHz (multiple of 10), and thereby necessitate a
corresponding increase in the value of C1 and C2 (from
10 µF to 100 µF).
“n”
5
7
6
V OUT *
+
VOUT
10 µF
Figure 7. External Clocking
V+
10 µF +
6
+
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual NCP7662
ROUT values.
1
CMOS
GATE
5
10 µF
V+
10 µF
1
2
+
Figure 6. Cascading Devices
for Increased Output Voltage
C1
3
4
NCP7662
OUT
V+
1 kΩ
7
4
The NCP7662 may be cascaded as shown to produce
larger negative multiplication of the initial supply voltage.
However, due to the finite efficiency of each device, the
practical limit is 10 devices for light loads. The output
voltage is defined by:
V
8
NCP7662
1
8
C OSC
7
6
5
+
C2
VOUT
Changing the NCP7662 Oscillator Frequency
It may be desirable in some applications (due to noise or
other considerations) to increase the oscillator frequency.
This is achieved by one of several methods described below:
By connecting the Boost Pin (Pin 1) to V+, the oscillator
charge and discharge current is increased and, hence the
oscillator frequency is increased by approximately 3–1/2
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface mount
applications where capacitor size and cost are critical.
Smaller capacitors, e.g., 0.1 µF, can be used in conjunction
with the Boost Pin in order to achieve similar output currents
compared to the device free running with C1 = C2 = 1 µF or
10 µF. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).
Increasing the oscillator frequency can also be achieved
by overdriving the oscillator from an external clock as
Figure 8. Lowering Oscillator Frequency
Positive Voltage Doubling
The NCP7662 may be employed to achieve positive
voltage doubling using the circuit shown in Figure 9. In this
application, the pump inverter switches of the NCP7662 are
used to charge C1 to a voltage level of V+ – VF (where V+
is the supply voltage and VF is the forward voltage on C1 plus
the supply voltage (V+) applied through diode D2 to
capacitor C2). The voltage thus created on C2 becomes
(2 V+) – (2 VF), or twice the supply voltage minus the
combined forward voltage drops of diodes D1 and D2.
The source impedance of the output (VOUT) will depend
on the output current, but for V+ = 5 V and an output current
of 10 mA, it will be approximately 60 Ω.
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6
NCP7662
V+
3
D1
7
D2
X
6
4
+
5
C1
+
C2
V+
50 µF
R L1
Figure 9. Positive Voltage Multiplier
VOUT =
(V+) – (V–)
2
Combined Negative Voltage Conversion and Positive
Supply Multiplication
NCP7662
1
2
3
+
C1
4
+
D2
VOUT =
(2 V+) – (2 VF)
5
+
50 µF
+
6
5
+
–
In some cases, the output impedance of the NCP7662 can
be a problem, particularly if the load current varies
substantially. The circuit of Figure 12 can be used to
overcome this by controlling the input voltage, via the
MC33201 op amp, in such a way as to maintain a nearly
constant output voltage. Direct feedback is advisable, since
the NCP7662’s output does not respond instantaneously to
change in input, but only after the switching delay. The
circuit shown supplies enough delay to accommodate the
NCP7662, while maintaining adequate feedback. An
increase in pump and storage capacitors is desirable, and the
values shown provide an output impedance of less than 5 Ω
to a load of 10 mA.
50 k
+8 V
C2
7
Regulated Negative Voltage Supply
C3
D1
3
Figure 11. Splitting a Supply in Half
8
6
2
+
–
8
V–
VOUT =
–(V+) – (VF)
7
1
4
R L2
Figure 10 combines the functions shown in Figures 3 and
9 to provide negative voltage conversion and positive
voltage doubling simultaneously. This approach would be,
for example, suitable for generating +9 V and –5 V from an
existing +5 V supply. In this instance, capacitors C1 and C3
perform the pump and reservoir functions, respectively, for
the generation of the negative voltage, while capacitors C2
and C4 are pump and reservoir, respectively, for the doubled
positive voltage. There is a penalty in this configuration
which combines both functions, however, in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge
pump driver at pin 2 of the device.
V+
50
µF
+
–
NCP7662
2
can be drawn from the device. By using this circuit, and then
the circuit of Figure 6, +15 V can be converted (via +7.5 V
and –7.5 V) to a nominal –15 V, though with rather high
series resistance ( 250 Ω).
VOUT =
(2 V+) – (2 VF)
C4
56 k
50 k
+8 V
–
+
Figure 10. Combined Negative Converter and
Positive Doubler
100 k
The bidirectional characteristics can also be used to split
a higher supply in half, as shown in Figure 11. The combined
load will be evenly shared between the two sides and a high
value resistor to the LV pin ensures start–up. Because the
switches share the load in parallel, the output impedance is
much lower than in the standard circuits, and higher currents
10 µF
V+
MC33201
1
100 µF
Voltage Splitting
100 Ω
+
–
2
3
NCP7662
NCP7662
8
+
–
1
4
800 k
8
7
6
5
250 K
VOLTAGE
ADJUST
VOUT
100 µF
Figure 12. Regulating the Output Voltage
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VOLTAGE CONVERSION EFFICIENCY (%)
NCP7662
1000
I DD( m A )
800
600
VIN = 12 V
400
200
VIN = 5 V
0
–40
–20
0
20
40
60
80
100
100.5
Without Load
100.0
99.5
10 K Load
99.0
98.5
98.0
TA = 25°C
1
2
3
4
6
7
8
9
10
INPUT VOLTAGE VIN (V)
Figure 13. Supply Current vs. Temperature
(with Boost Pin = VIN)
Figure 14. Voltage Conversion
11
12
100
OUTPUT SOURCE RESISTANCE (Ω )
70
50
30
IOUT = 20 mA
TA = 25°C
10
1.5
2.5 3.5 4.5
80
60
VIN = 5.5 V
40
20
0
–40
5.5 6.5 7.5 8.5 9.5 10.5 11.5 12
VIN = 2.5 V
–20
0
20
40
60
80
100
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 15. Output Source Resistance
vs. Supply Voltage
Figure 16. Output Source Resistance
vs. Temperature
200
SUPPLY CURRENT IDD ( m A )
0
OUTPUT VOLTAGE VOUT (V)
5
TEMPERATURE (°C)
100
OUTPUT SOURCE RESISTANCE (Ω )
101.0
–2
–4
–6
–8
–10
10
20
30
40
50
60
70
80
90
150
125
100
100
VIN = 12.5 V
75
50
VIN = 5.5 V
25
0
–40
–12
0
175
–20
0
20
40
60
80
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
Figure 17. Output Voltage vs. Output Current
Figure 18. Supply Current vs. Temperature
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8
100
NCP7662
60
OSCILLATOR FREQUENCY (kHz)
OSCILLATOR FREQUENCY (kHz)
12
10
8
6
VIN = 5 V
4
VIN = 12 V
2
0
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
50
40
VIN = 5 V
30
VIN = 12 V
20
10
0
–40
100
Figure 19. Unloaded Oscillator Frequency
vs. Temperature
–20
0
20
40
60
TEMPERATURE (°C)
80
Figure 20. Unloaded Oscillator Frequency
vs. Temperature with Boost Pin = VIN
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100
NCP7662
PACKAGE DIMENSIONS
PDIP–8
P SUFFIX
CASE 626–05
ISSUE K
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
–––
10_
0.76
1.01
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
–––
10_
0.030
0.040
N
SEATING
PLANE
D
M
K
G
H
0.13 (0.005)
M
T A
M
B
M
SO–8
D SUFFIX
CASE 751–06
ISSUE T
D
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
5
0.25
H
E
M
B
M
1
4
h
B
e
X 45 _
q
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
S
A
S
DIM
A
A1
B
C
D
E
e
H
h
L
q
http://onsemi.com
10
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
NCP7662
Notes
http://onsemi.com
11
NCP7662
ON Semiconductor and
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