AD ADG5462F User defined fault protection and detection,10 î© ron, quad channel protector Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD
User defined secondary supplies set overvoltage level
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source pins
Minimum secondary supply level: 4.5 V single-supply
Interrupt flag indicates fault status
Low on resistance: 10 Ω typical
On-resistance flatness: 0.5 Ω maximum
4 kV human body model (HBM) ESD rating
Latch-up immune under any circumstance
VSS to VDD analog signal range
±5 V to ±22 V dual supply operation
8 V to 44 V single-supply operation
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VSS
S1
D1
S2
D2
S3
D3
S4
D4
VIN
ADG5462F
POSFV NEGFV
DR
VOUT
FF
12698-001
Data Sheet
User Defined Fault Protection and
Detection,10 Ω RON, Quad Channel Protector
ADG5462F
Figure 1.
APPLICATIONS
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
GENERAL DESCRIPTION
The ADG5462F contains four channels that are overvoltage
protected. The channel protector is placed in series with the signal
path and protects sensitive components from overvoltage faults
in that path. The channel protector prevents overvoltages when
powered and unpowered, and it is ideal for use in applications
where correct power supply sequencing cannot always be guaranteed.
The primary supply voltages define the on-resistance profile,
while the secondary supply voltages define the voltage level at
which the overvoltage protection engages.
When no power supplies are present, the channel remains in the off
condition, and the channel inputs are high impedance. Under
normal operating conditions, if the analog input signal levels on
any Sx pin exceed positive fault voltage (POSFV) or negative fault
voltage (NEGFV) by a threshold voltage (VT), the channel turns
off and that Sx pin becomes high impedance. If the DR pin is
driven low, the drain pin (Dx) is pulled to the secondary supply
voltage that was exceeded. The output profile for each DR voltage
level is shown in Figure 49. Input signal levels up to −55 V or
+55 V relative to ground are blocked in both the powered and
unpowered conditions.
Rev. B
The low on-resistance of these switches, combined with the
on-resistance flatness over a significant portion of the signal
range make them an ideal solution for data acquisition and
instrumentation applications where excellent linearity and low
distortion are critical.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Source pins (Sx) are protected against voltages greater than
the secondary supply rails (POSFV and NEGFV), up to
−55 V and +55 V.
In an unpowered state, source pins (Sx) are protected
against voltages from −55 V to +55 V.
Overvoltage detection with digital output indicates the
operating state of the channels.
Trench isolation guards against latch-up.
Optimized for low on-resistance and on-resistance flatness.
The ADG5462F operates from a dual power supply range of
±5 V to ±22 V or a single power supply range of 8 V to 44 V.
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ADG5462F
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .................................................................................... 23
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 24
Functional Block Diagram .............................................................. 1
Switch Architecture .................................................................... 24
General Description ......................................................................... 1
User Defined Fault Protection .................................................. 25
Product Highlights ........................................................................... 1
Applications Information .............................................................. 27
Revision History ............................................................................... 2
Power Supply Rails ..................................................................... 27
Specifications..................................................................................... 3
Power Supply Sequencing Protection ...................................... 27
±15 V Dual Supply ....................................................................... 3
Power Supply Recommendations............................................. 27
±20 V Dual Supply ....................................................................... 5
User Defined Signal Range ....................................................... 27
12 V Single Supply ........................................................................ 7
Low Impedance Channel Protection ....................................... 27
36 V Single Supply ........................................................................ 9
High Voltage Surge Suppression .............................................. 27
Continuous Current per Channel, Sx or Dx ........................... 10
Intelligent Fault Detection ........................................................ 28
Absolute Maximum Ratings .......................................................... 11
Large Voltage, High Frequency Signals ................................... 28
ESD Caution ................................................................................ 11
Outline Dimensions ....................................................................... 29
Pin Configurations and Function Descriptions ......................... 12
Ordering Guide .......................................................................... 29
Typical Performance Characteristics ........................................... 13
Test Circuits ..................................................................................... 19
REVISION HISTORY
1/16—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Channel On Leakage, ID (On), IS (On) Maximum
Parameter, Table 2.............................................................................. 5
Changes to Table 3 ............................................................................ 7
Changes to Table 4 ............................................................................ 9
5/15—Rev. 0 to Rev. A
Added 16-Lead LFCSP Package........................................ Universal
Changes to Drain Leakage Current, ID, with Overvoltage
Parameter Test Condition/Comment, Table 3 .............................. 7
Changes to Drain Leakage Current, ID, with Overvoltage
Parameter Test Condition/Comment, Table 4 .............................. 9
Changes to Table 5 .......................................................................... 10
Changes to Table 6 .......................................................................... 11
Added Figure 3; Renumbered Sequentially ................................ 12
Changes to Table 7 .......................................................................... 12
Added Figure 54.............................................................................. 29
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 29
1/15—Revision 0: Initial Version
Rev. B | Page 2 of 29
Data Sheet
ADG5462F
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Channel On Leakage, ID (On), IS (On)
+25°C
−40°C to
+85°C
VDD to VSS
10
11.2
9.5
10.7
0.05
0.5
0.05
0.35
0.6
0.9
0.1
0.4
0.7
±0.3
±1.5
14
16.5
13.5
16
0.6
0.7
0.5
0.5
1.1
1.1
0.5
0.5
±2.0
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
±78
µA typ
±40
µA typ
nA typ
±8.0
±10
±15
Power Supplies Floating
±30
±10
±50
±10
±49
nA max
nA typ
±100
±10
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
V max
±0.7
±1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
Unit
±4.5
±2.0
Power Supplies Grounded
DIGITAL INPUTS/OUTPUTS (DR/FF)
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
5.0
2.0
0.8
Rev. B | Page 3 of 29
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V, see Figure 35
VS = ±10 V, IS = −10 mA
VS = ±9 V, IS = −10 mA
VS = ±10 V, IS = −10 mA
VS = ±9 V, IS = −10 mA
VS = ±10 V, IS = −10 mA
VS = ±9 V, IS = −10 mA
See Figure 23
VDD = +16.5 V, VSS = −16.5 V
VS = VD = ±10 V, see Figure 36
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V,
VS = ±55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, VS = ±55 V, see Figure 38
DR = floating or VDD
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V,
VS = ±55 V, see Figure 37
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±55 V, see Figure 38
VDD = floating, VSS = floating, GND = 0 V,
VS = ±55 V, see Figure 38
VIN = VGND or VDD
ADG5462F
Parameter
DYNAMIC CHARACTERISTICS 1
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Drain Pull-Up/Pull-Down Time Following
Overvoltage, tRESPONSE (DR)
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
Data Sheet
+25°C
460
585
720
930
4
85
60
600
−90
0.0015
−40°C to
+85°C
−40°C to
+125°C
615
630
1050
1100
115
85
Unit
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
µs typ
RL = 1 kΩ, CL = 2 pF, see Figure 42
ns typ
µs typ
ns typ
dB typ
% typ
CL = 12 pF, see Figure 44
CL = 12 pF, see Figure 45
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 46
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
RL = 10 kΩ, VS = 15 V p-p,
f = 20 Hz to 20 kHz, see Figure 41
RL = 50 Ω, CL = 5 pF, see Figure 40
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
VS = 0 V, f = 1 MHz
VDD = POSFV = +16.5 V, VSS = NEGFV = −16.5 V,
GND = 0 V
318
–0.8
24
MHz typ
dB typ
pF typ
0.9
0.1
1.2
0.4
0.55
0.5
0.1
0.65
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
1.3
0.6
0.7
RL = 1 kΩ, CL = 2 pF, see Figure 43
CL = 12 pF, see Figure 47
VS = ±55 V
1.2
0.1
1.6
0.8
1.0
0.5
0.1
1.0
1.8
1.1
1.8
±5
±22
Guaranteed by design; not subject to production test.
Rev. B | Page 4 of 29
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Data Sheet
ADG5462F
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Channel On Leakage, ID (On), IS (On)
+25°C
−40°C to
+85°C
VDD to VSS
10
11.5
9.5
11
0.05
0.35
0.05
0.35
1.0
1.4
0.1
0.4
0.7
±0.3
±1.5
14.5
16.5
14
16.5
0.5
0.5
0.5
0.5
1.5
1.5
0.5
0.5
±2.0
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
±78
µA typ
±40
µA typ
nA typ
±1.0
±10
±1.0
Power Supplies Floating
±30
±10
±50
±10
±1.0
µA max
nA typ
±100
±10
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
V max
0.7
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
Unit
±4.5
±5.0
Power Supplies Grounded
DIGITAL INPUTS/OUTPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
5.0
2.0
0.8
Rev. B | Page 5 of 29
Test Conditions/Comments
VDD = +18 V, VSS = −18 V, see Figure 35
VS = ±15 V, IS = −10 mA
VS = ±13.5 V, IS = −10 mA
VS = ±15 V, IS = −10 mA
VS = ±13.5 V, IS = −10 mA
VS = ±15 V, IS = −10 mA
VS = ±13.5 V, IS = −10 mA
See Figure 23
VDD = +22 V, VSS = −22 V
VS = VD = ±15 V, see Figure 36
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = ±55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, VS = ±55 V,
see Figure 38
DR = floating or VDD
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = ±55 V, see Figure 37
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±55 V, see Figure 38
VDD = floating, VSS = floating, GND = 0 V,
VS = ±55 V, see Figure 38
VIN = VGND or VDD
ADG5462F
Parameter
DYNAMIC CHARACTERISTICS 1
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Drain Pull-Up/Pull-Down Time Following
Overvoltage, tRESPONSE (DR)
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
Data Sheet
+25°C
370
480
840
1200
4
85
60
600
−90
0.001
−40°C to
+85°C
−40°C to
+125°C
500
515
1400
1700
115
85
Unit
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
µs typ
RL = 1 kΩ, CL = 2 pF, see Figure 42
ns typ
µs typ
ns typ
dB typ
% typ
CL = 12 pF, see Figure 44
CL = 12 pF, see Figure 45
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 46
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
RL = 10 kΩ, VS = 20 V p-p,
f = 20 Hz to 20 kHz, see Figure 41
RL = 50 Ω, CL = 5 pF, see Figure 40
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
VS = 0 V, f = 1 MHz
VDD = POSFV = +22 V, VSS = NEGFV = −22 V
310
–0.8
23
MHz typ
dB typ
pF typ
0.9
0.1
1.2
0.4
0.55
0.5
0.1
0.65
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
1.3
0.6
0.7
RL = 1 kΩ, CL = 2 pF, see Figure 43
CL = 12 pF, see Figure 47
VS = ±55 V
1.2
0.1
1.6
0.8
1.0
0.5
0.1
1.0
1.8
1.1
1.8
±5
±22
Guaranteed by design; not subject to production test.
Rev. B | Page 6 of 29
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Data Sheet
ADG5462F
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Channel On Leakage, ID (On), IS (On)
+25°C
−40°C to
+85°C
0 V to VDD
22
24.5
10
11.2
0.05
0.5
0.05
0.5
12.5
14.5
0.6
0.9
0.7
±0.3
±1.5
31
37
14
16.5
0.6
0.7
0.6
0.7
19
23
1.1
1.3
±2.0
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
±78
µA typ
±40
µA typ
nA typ
±8.0
±10
±15
Power Supplies Floating
±30
±10
±50
±10
±49
nA max
nA typ
±100
±10
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
V max
0.7
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
Unit
±4.5
±2.0
Power Supplies Grounded
DIGITAL INPUTS/OUTPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
5.0
2.0
0.8
Rev. B | Page 7 of 29
Test Conditions/Comments
VDD = +10.8 V, VSS = 0 V, see Figure 35
VS = 0 V to +10 V, IS = −10 mA
VS = +3.5 V to +8.5 V, IS = −10 mA
VS = 0 V to +10 V, IS = −10 mA
VS = +3.5 V to +8.5 V, IS = −10 mA
VS = 0 V to +10 V, IS = −10 mA
VS = +3.5 V to +8.5 V, IS = −10 mA
See Figure 23
VDD = +13.2 V, VSS = 0 V
VS = VD = 1 V/10 V, see Figure 36
VDD = +13.2 V, VSS = 0 V, GND = 0 V,
VS = ±55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, VS = ±55 V, see Figure 38
DR = floating or VDD
VDD = +13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
see Figure 37
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±55 V, see Figure 38
VDD = floating, VSS = floating,
GND = 0 V, VS = ±55 V, see Figure 38
VIN = VGND or VDD
ADG5462F
Parameter
DYNAMIC CHARACTERISTICS 1
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Drain Pull-Up/Pull-Down Time Following
Overvoltage, tRESPONSE (DR)
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD
1
Data Sheet
+25°C
560
660
640
800
4
85
60
600
−90
0.007
−40°C to
+85°C
−40°C to
+125°C
700
720
865
960
115
85
Unit
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
µs typ
RL = 1 kΩ, CL = 2 pF, see Figure 42
ns typ
µs typ
ns typ
dB typ
% typ
CL = 12 pF, see Figure 44
CL = 12 pF, see Figure 45
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 46
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
RL = 10 kΩ, VS = 6 V p-p,
f = 20 Hz to 20 kHz, see Figure 41
RL = 50 Ω, CL = 5 pF, see Figure 40
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
VS = 6 V, f = 1 MHz
VDD = +13.2 V, VSS = 0 V,
digital inputs = 0 V, 5 V, or VDD
284
–0.9
25
MHz typ
dB typ
pF typ
0.9
0.1
1.2
0.4
0.55
0.5
0.1
0.65
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
1.3
0.6
0.7
RL = 1 kΩ, CL = 2 pF, see Figure 43
CL = 12 pF, see Figure 47
VS = ±55 V
1.2
0.1
1.6
0.8
1.0
0.5
0.1
1.0
1.8
1.1
1.8
8
44
Guaranteed by design; not subject to production test.
Rev. B | Page 8 of 29
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
Digital inputs = 5 V
VS = ±55 V, VD = 0 V
GND = 0 V
GND = 0 V
Data Sheet
ADG5462F
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Channel On Leakage, ID (On), IS (On)
+25°C
−40°C to
+85°C
0 V to VDD
22
24.5
10
11
0.05
0.5
0.05
0.35
12.5
14.5
0.1
0.4
0.7
±0.3
±1.5
31
37
14
16.5
0.6
0.7
0.5
0.5
19
23
0.5
0.5
±2.0
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
±78
µA typ
±40
µA typ
nA typ
±8.0
±10
±15
Power Supplies Floating
±30
±10
±50
±10
±49
nA max
nA typ
±100
±10
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
V max
0.7
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
Unit
±4.5
±2.0
Power Supplies Grounded
DIGITAL INPUTS/OUTPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
5.0
2.0
0.8
Rev. B | Page 9 of 29
Test Conditions/Comments
VDD = +32.4 V, VSS = 0 V, see Figure 35
VS = 0 V to +30 V, IS = −10 mA
VS = +4.5 V to +28 V, IS = −10 mA
VS = 0 V to +30 V, IS = −10 mA
VS = +4.5 V to +28 V, IS = −10 mA
VS = 0 V to +30 V, IS = −10 mA
VS = +4.5 V to +28 V, IS = −10 mA
See Figure 23
VDD = +39.6 V, VSS = 0 V
VS = VD = 1 V/30 V, see Figure 36
VDD = +39.6 V, VSS = 0 V, GND = 0 V,
VS = −40 V to +55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, VS = +55 V, −40 V,
see Figure 38
DR = floating or VDD
VDD = +39.6 V, VSS = 0 V, GND = 0 V,
VS = −40 V to +55 V, see Figure 37
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = −40 V to +55 V, see Figure 38
VDD = floating, VSS = floating, GND = 0 V,
VS = −40 V to +55 V, see Figure 38
VIN = VGND or VDD
ADG5462F
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS 1
Overvoltage Response Time, tRESPONSE
+25°C
250
350
1500
2000
4
Overvoltage Recovery Time, tRECOVERY
Drain Pull-Up/Pull-Down Time Following
Overvoltage, tRESPONSE (DR)
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
−40°C to
+85°C
−40°C to
+125°C
360
375
2300
85
60
600
−90
0.001
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
115
85
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
µs typ
RL = 1 kΩ, CL = 2 pF, see Figure 42
ns typ
µs typ
ns typ
dB typ
% typ
CL = 12 pF, see Figure 44
CL = 12 pF, see Figure 45
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 46
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
RL = 10 kΩ, VS = 18 V p-p,
f = 20 Hz to 20 kHz, see Figure 41
RL = 50 Ω, CL = 5 pF, see Figure 40
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
VS = 18 V, f = 1 MHz
VDD = 39.6 V, VSS = 0 V,
digital inputs = 0 V, 5 V, or VDD
RL = 1 kΩ, CL = 2 pF, see Figure 43
CL = 12 pF, see Figure 47
321
–0.8
23
MHz typ
dB typ
pF typ
0.9
0.1
1.2
0.4
0.55
0.5
0.1
0.65
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
1.3
0.6
0.7
VS = −40 V to +55 V
1.2
0.1
1.6
0.8
1.0
0.5
0.1
1.0
ISS
INEGFV
ISS + INEGFV
1.8
1.1
1.8
8
44
VDD
1
2700
Unit
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter
16-Lead TSSOP
θJA = 112.6°C/W
16-Lead LFCSP
θJA = 30.4°C/W
25°C
85°C
125°C
Unit
Test Conditions/Comments
83
64
59
48
39
29
mA max
mA max
VS = VSS + 4.5 V to VDD − 4.5 V
VS = VSS to VDD
152
118
99
81
61
53
mA max
mA max
VS = VSS + 4.5 V to VDD − 4.5 V
VS = VSS to VDD
Rev. B | Page 10 of 29
Data Sheet
ADG5462F
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
POSFV to GND
NEGFV to GND
Sx Pins to GND
Sx to VDD or VSS
VS to VD
Dx Pins1, 2 to GND
Digital Input (DR pin) to GND
Peak Current, Sx or Dx Pins
Continuous Current, Sx or Dx Pins
Digital Output (FF pin)
Dx Pins, Overvoltage State,
DR = GND, Load Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer Board)
16-Lead LFCSP (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb-Free
ESD (HBM: ESDA/JEDEC JS-001-2011)
Input/Output Port to Supplies
Input/Output Port to
Input/Output Port
All Other Pins
Rating
48 V
−0.3 V to +48 V
−48 V to +0.3 V
−0.3 V to VDD + 0.3 V
VSS − 0.3V to +0.3 V
−55 V to +55 V
80 V
80 V
NEGFV − 0.7 V to POSFV +
0.7 V or 30 mA, whichever
occurs first
GND − 0.7 V to 48 V or 30 mA,
whichever occurs first
288 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data3 + 15%
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
1 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
30.4°C/W
As per JEDEC J-STD-020
4 kV
4 kV
4 kV
Overvoltages at the Dx pins are clamped by internal diodes. Limit current to
the maximum ratings given.
2
POSFV and NEGFV must not exceed VDD and VSS, respectively.
3
See Table 5.
1
Rev. B | Page 11 of 29
ADG5462F
Data Sheet
13 D2
14 POSFV
16 D1
15 NEGFV
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
12 S2
S1 1
15
D2
GND 3
S1 3
14
ADG5462F
S2
S4 4
13
TOP VIEW
(Not to Scale)
VDD
12
FF
S4 6
11
S3
D4 7
10
D3
DR 8
9
NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
TOP VIEW
(Not to Scale)
11 VDD
10 FF
9
D4 5
GND 5
S3
NOTES
1. NIC = NOT INTERNALLY CONNECTED. DO NOT
CONNECT TO THIS PIN.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE PAD BE SOLDERED
TO THE LOWEST SUPPLY VOLTAGE, VSS.
12698-002
VSS 4
ADG5462F
Figure 2. TSSOP Pin Configuration
12698-103
D1 2
VSS 2
D3 8
POSFV
NIC 7
16
DR 6
NEGFV 1
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP
1
15
Mnemonic
NEGFV
2
3
4
5
6
7
8
16
1
2
3
4
5
6
D1
S1
VSS
GND
S4
D4
DR
9
10
11
12
7
8
9
10
NIC
D3
S3
FF
13
14
15
16
11
12
13
14
VDD
S2
D2
POSFV
EP
Exposed Pad
Description
Negative Fault Voltage. This pin provides the negative supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VSS.
Drain Terminal 1. This pin can be an input or an output.
Overvoltage Protected Source Terminal 1. This pin can be an input or an output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Overvoltage Protected Source Terminal 4. This pin can be an input or an output.
Drain Terminal 4. This pin can be an input or an output.
Drain Response Digital Input. Tying this pin to GND enables the drain to pull to POSFV or NEGFV during an
overvoltage fault condition. The default condition of the drain is open-circuit when the pin is left
floating or if it is tied to VDD.
Not Internally Connected.
Drain Terminal 3. This pin can be an input or an output.
Overvoltage Protected Source Terminal 3. This pin can be an input or an output.
Fault Flag Digital Output. This pin has a high output (nominally 3 V) when the device is in normal
operation or a low output when a fault condition occurs on any of the Sx inputs. The FF pin has a weak
internal pull-up that allows the signals to be combined into a single interrupt for larger modules that
contain multiple devices.
Most Positive Power Supply Potential.
Overvoltage Protected Source Terminal 2. This pin can be an input or an output.
Drain Terminal 2. This pin can be an input or an output.
Positive Fault Voltage. This pin provides the positive supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VDD.
The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the lowest supply voltage, VSS.
Rev. B | Page 12 of 29
Data Sheet
ADG5462F
TYPICAL PERFORMANCE CHARACTERISTICS
25
VDD = +15V
VSS = –15V
TA = 25°C
35
VDD = +20V
VSS = –20V
VDD = +18V
VSS = –18V
15
VDD = +16.5V
VSS = –16.5V
30
ON RESISTANCE (Ω)
20
ON RESISTANCE (Ω)
40
VDD = +22V
VSS = –22V
VDD = +13.5V
VSS = –13.5V
10
20
+125°C
15
+85°C
10
VDD = +15V
VSS = –15V
5
25
+25°C
–40°C
–20
–15
–10
–5
0
5
10
15
20
25
VS, VD (V)
0
–15
12698-003
0
–25
–12
–9
–6
–3
0
3
6
9
12
15
VS, VD (V)
Figure 4. On Resistance (RON) as a Function of VS, VD (Dual Supply)
12698-006
5
Figure 7. On Resistance (RON) as a Function of VS,VD for Different
Temperatures, ±15 V Dual Supply
25
40
VDD = +20V
VSS = –20V
TA = 25°C
35
VDD = 12V
VSS = 0V
30
VDD = 10.8V
VSS = 0V
15
10
VDD = 13.2V
VSS = 0V
25
20
+125°C
15
+85°C
10
+25°C
5
5
0
2
4
6
8
10
12
14
VS, VD (V)
0
–20
12698-004
0
–40°C
–15
–10
–5
0
5
10
Figure 5. On Resistance (RON) as a Function of VS, VD (12 V Single Supply)
20
Figure 8. On Resistance (RON) as a Function of VS, VD for Different
Temperatures, ±20 V Dual Supply
25
40
VDD = 12V
VSS = 0V
TA = 25°C
35
20
VDD = 36V
VSS = 0V
30
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
15
VS, VD (V)
12698-007
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
20
VDD = 32.4V
VSS = 0V
15
10
20
+125°C
15
+85°C
10
VDD = 39.6V
VSS = 0V
5
25
+25°C
–40°C
0
5
10
15
20
VS, VD (V)
25
30
35
40
Figure 6. On Resistance (RON) as a Function of VS, VD (36 V Single Supply)
Rev. B | Page 13 of 29
0
0
2
4
6
8
10
12
VS, VD (V)
Figure 9. On Resistance (RON) as a Function of VS, VD for Different
Temperatures, 12 V Single Supply
12698-008
0
12698-005
5
ADG5462F
Data Sheet
40
1
VDD = 36V
VSS = 0V
35
0
LEAKAGE CURRENT (nA)
ON RESISTANCE (Ω)
30
25
20
+125°C
15
+85°C
10
+25°C
–40°C
VDD = 12V
VSS = 0V
VS = VD = 1V/10V
–1
–2
–3
–4
5
4
8
12
16
20
24
28
32
36
VS, VD (V)
0
20
40
60
80
100
120
TEMPERATURE (°C)
12698-012
0
IS, ID (ON) – –
IS, ID (ON) + +
–5
12698-009
0
Figure 13. Leakage Current vs. Temperature, 12 V Single Supply
Figure 10. On Resistance (RON) as a Function of VS, VD for Different
Temperatures, 36 V Single Supply
2
2
VDD = +15V
VSS = –15V
VS = VD = +10V/–10V
1
0
LEAKAGE CURRENT (nA)
LEAKAGE CURRENT (nA)
0
–1
–2
–3
–4
–5
–6
VDD = 36V
VSS = 0V
VS = VD = 1V/30V
–2
–4
–6
–8
–7
IS, ID (ON) – –
40
60
80
100
120
TEMPERATURE (°C)
0
DRAIN OVERVOLTAGE LEAKAGE CURRENT (nA)
VDD = +20V
VSS = –20V
VS = VD = +15V/–15V
–4
–6
–8
IS, ID (ON) + +
20
40
IS, ID (ON) – –
60
80
100
120
TEMPERATURE (°C)
12698-011
LEAKAGE CURRENT (nA)
0
0
IS, ID (ON) – –
40
60
80
100
120
Figure 14. Leakage Current vs. Temperature, 36 V Single Supply
2
–10
20
TEMPERATURE (°C)
Figure 11. Leakage Current vs. Temperature, ±15 V Dual Supply
–2
IS, ID (ON) + +
–10
12698-013
20
5
VDD = +15V
VSS = –15V
0
–5
–10
–15
VS = –30V
VS = –55V
VS = +30V
VS = +55V
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 12. Leakage Current vs. Temperature, ±20 V Dual Supply
Figure 15. Drain Overvoltage Leakage Current vs. Temperature,
±15 V Dual Supply
Rev. B | Page 14 of 29
12698-014
0
12698-010
IS, ID (ON) + +
–8
ADG5462F
0
5
VDD = +20V
VSS = –20V
TA = 25°C
VDD = +15V
VSS = –15V
–10
0
–20
–30
CROSSTALK (dB)
–5
–10
–15
–40
–50
–60
–70
VS = –30V
VS = –55V
VS = +30V
VS = +55V
–25
0
20
–80
–90
40
60
80
100
120
TEMPERATURE (°C)
–100
10k
10M
100M
1G
Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply
2
0
VDD = 12V
VSS = 0V
0
TA = 25°C
VDD = +15V
VSS = –15V
–20
–2
–4
ACPSRR (dB)
–40
–6
–8
–10
–60
–80
VS = –30V
VS = –55V
VS = +30V
VS = +55V
–14
–16
0
20
–100
40
60
80
100
120
TEMPERATURE (°C)
–120
10k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 17. Drain Overvoltage Leakage Current vs. Temperature,
12 V Single Supply
Figure 20. AC Power Supply Rejection Ratio (ACPSRR) vs. Frequency,
±15 V Dual Supply
2
0.020
VDD = 36V
VSS = 0V
0
100k
12698-019
–12
12698-016
–2
LOAD = 10kΩ
TA = 25°C
0.015
THD + N (%)
–4
–6
–8
–10
0
20
VDD = 20V, VSS = –20V, VS = 20V p-p
VDD = 36V, VSS = 0V, VS = 18V p-p
40
60
80
TEMPERATURE (°C)
100
120
0
12698-017
–14
VDD = 15V, VSS = –15V, VS = 15V p-p
0.005
VS = –38V
VS = –40V
VS = +38V
VS = +55V
–12
VDD = 12V, VSS = 0V, VS = 6V p-p
0.010
0
5000
10000
15000
FREQUENCY (Hz)
Figure 18. Overvoltage Leakage Current vs. Temperature, 36 V Single Supply
Rev. B | Page 15 of 29
Figure 21. THD + N vs. Frequency, ±15 V Dual Supply
20000
12698-020
DRAIN OVERVOLTAGE LEAKAGE CURRENT (nA)
1M
FREQUENCY (Hz)
Figure 16. Drain Overvoltage Leakage Current vs. Temperature,
±20 V Dual Supply
OVERVOLTAGE LEAKAGE CURRENT (nA)
100k
12698-018
–20
12698-015
DRAIN OVERVOLTAGE LEAKAGE CURRENT (nA)
Data Sheet
ADG5462F
Data Sheet
0
TA = 25°C
VDD = +15V
VSS = –15V
–0.5
T
–1.0
BANDWIDTH (dB)
–1.5
VDD
–2.0
POSFV
–2.5
–3.0
–3.5
DRAIN
SOURCE
4
–4.0
100k
1M
10M
100M
1G
FREQUENCY (Hz)
CH1 5.00V
CH3 5.00V
Figure 22. Bandwidth vs. Frequency
CH2 5.00V
CH4 5.00V
11.0V
T
SOURCE
0.8
VDD
POSFV
0.7
DRAIN
0.5
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
CH1 5.00V
CH3 5.00V
Figure 23. Threshold Voltage (VT) vs. Temperature
CH2 5.00V
CH4 5.00V
A CH1
11.0V
Figure 26. Drain Output Recovery from Positive Overvoltage
(DR = Floating or High)
24
T
TA = 25°C
VDD = +10V
VSS = –10V
20
M2.00µs
12698-025
4
0.6
12698-022
VDD
16
DRAIN
POSFV
12
DISTORTIONLESS
OPERATING
REGION
8
SOURCE
4
0
1
10
FREQUENCY (MHz)
Figure 24. Large Voltage Signal Tracking vs. Frequency
100
12698-023
4
CH1 5.00V
CH3 5.00V
CH2 5.00V
CH4 5.00V
M2.00µs
A CH1
11.7V
12698-026
THRESHOLD VOLTAGE, VT (V)
A CH1
Figure 25. Drain Output Response to Positive Overvoltage
(DR = Floating or High)
0.9
SIGNAL VOLTAGE (V p-p)
M2.00µs
12698-024
–5.0
10k
12698-021
–4.5
Figure 27. Drain Output Response to Positive Overvoltage (DR = GND)
Rev. B | Page 16 of 29
Data Sheet
ADG5462F
T
T
SOURCE
4
VDD
NEGFV
POSFV
DRAIN
DRAIN
VSS
4
CH2 5.00V
CH4 5.00V
M2.00µs
A CH1
16.0V
CH1 5.00V
CH3 5.00V
CH2 5.00V
CH4 5.00V
M2.00µs
A CH1
–10.4V
12698-030
CH1 5.00V
CH3 5.00V
12698-027
SOURCE
Figure 28. Drain Output Recovery from Positive Overvoltage (DR = GND)
Figure 31. Drain Output Response to Negative Overvoltage (DR = GND)
T
T
DRAIN
4
4
DRAIN
NEGFV
NEGFV
VSS
VSS
CH2 5.00V
CH4 5.00V
M2.00µs
A CH1
–10.4V
12698-028
CH1 5.00V
CH3 5.00V
Figure 29. Drain Output Response to Negative Overvoltage
(DR = Floating or High)
CH1 5.00V
CH3 5.00V
CH2 5.00V
CH4 5.00V
M2.00µs
A CH1
–10.4V
12698-031
SOURCE
SOURCE
Figure 32. Drain Output Recovery from Negative Overvoltage (DR = GND)
T
T
SOURCE
DRAIN
4
VDD = POSFV
NEGFV
DR INPUT
VSS
2
CH2 5.00V
CH4 5.00V
M2.00µs
A CH1
–10.4V
12698-029
CH1 5.00V
CH3 5.00V
Figure 30. Drain Output Recovery from Negative Overvoltage
(DR = Floating or High)
CH1 5.00V
CH3 2.00V
CH2 5.00V
CH4 5.00V
M1.00µs
A CH3
1.12V
12698-032
DRAIN
SOURCE
Figure 33. Drain Output Response to Positive Overvoltage (DR = High to Low)
Rev. B | Page 17 of 29
ADG5462F
Data Sheet
T
DRAIN
2
DR INPUT
3
VSS = NEGFV
CH2 5.00V
CH4 5.00V
M1.00µs
A CH3
1.12V
12698-033
CH1 5.00V
CH3 2.00V
SOURCE
Figure 34. Drain Output Response to Negative Overvoltage
(DR = High to Low)
Rev. B | Page 18 of 29
Data Sheet
ADG5462F
TEST CIRCUITS
V
Sx
A
IDS
RON = V/IDS
Dx
A
RL
|VS| > |POSFV| OR |NEGFV| 10kΩ
DR = FLOATING OR VDD
12698-037
VS
ID
IS
Dx
12698-034
Sx
Figure 37. Switch Overvoltage Leakage
Figure 35. On Resistance
VDD = VSS = POSFV = NEGFV = GND = 0V
VD
ID
Sx
Dx
A
RL
10kΩ
VS
Figure 38. Switch Unpowered Leakage
Figure 36. On Leakage
VDD
VSS
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
S1
D2
RL
50Ω
RL
50Ω
VOUT
S2
VS
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT
VS
Figure 39. Channel-to-Channel Crosstalk
VDD
VSS
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
Sx
50Ω
VS
Dx
RL
50Ω
GND
INSERTION LOSS = 20 log
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 40. Bandwidth
Rev. B | Page 19 of 29
12698-038
A
A
12698-036
NC = NO CONNECT
IS
12698-039
Dx
12698-035
NC
Sx
ID (ON)
ADG5462F
Data Sheet
VSS
VDD
0.1µF
0.1µF
VDD
AUDIO
PRECISION
VSS
RS
Sx
VS
V p-p
Dx
VOUT
RL
10kΩ
12698-040
GND
Figure 41. THD + N
VDD VSS
0.1µF
0.1µF
POSFV
0.1µF
NEGFV
0.1µF
SOURCE
VOLTAGE
(VS)
VDD VSS
S1
0V
VS
NEGFV
POSFV
POSFV + 0.5V
VD
D1
CL*
2pF
ADG5462F
tRESPONSE
POSFV × 0.9
RL
1kΩ
S2 TO S4
OUTPUT
(VD)
12698-041
GND
0V
*INCLUDES TRACK CAPACITANCE
Figure 42. Overvoltage Response Time, tRESPONSE
VDD VSS
0.1µF
0.1µF
POSFV
0.1µF
NEGFV
0.1µF
SOURCE
VOLTAGE
(VS)
S1
0V
VS
OUTPUT
(VD)
POSFV × 0.1
0V
VD
D1
ADG5462F
CL*
2pF
RL
1kΩ
S2 TO S4
GND
*INCLUDES TRACK CAPACITANCE
Figure 43. Overvoltage Recovery Time, tRECOVERY
Rev. B | Page 20 of 29
12698-042
tRECOVERY
VDD VSS
NEGFV
POSFV
POSFV + 0.5V
Data Sheet
ADG5462F
VDD VSS
0.1µF
POSFV
0.1µF
NEGFV
0.1µF
POSFV
POSFV + 0.5V
SOURCE
VOLTAGE
(VS)
VDD VSS
D1
S1
0V
NEGFV
0.1µF
VS
S2 TO S4
tDIGRESP
ADG5462F
OUTPUT
FF
CL*
12pF
GND
0.1VOUT
0V
*INCLUDES TRACK CAPACITANCE
12698-043
OUTPUT
(VFF)
Figure 44. Interrupt Flag Response Time, tDIGRESP
VDD VSS
0.1µF
POSFV
0.1µF
NEGFV
0.1µF
POSFV
POSFV + 0.5V
SOURCE
VOLTAGE
(VS)
VDD VSS
NEGFV
0.1µF
S1
0V
D
VS
S2 TO S4
ADG5462F
tDIGREC
OUTPUT
0.9VOUT
FF
CL*
12pF
GND
0V
*INCLUDES TRACK CAPACITANCE
12698-044
OUTPUT
(VFF)
Figure 45. Interrupt Flag Recovery Time, tDIGREC
VDD VSS
POSFV
0.1µF
NEGFV
0.1µF
VDD VSS
S1
0V
VS
tDIGREC
D1
S2 TO S4
5V
ADG5462F
RPULLUP
1kΩ
OUTPUT
5V
OUTPUT
(VFF)
FF
3V
GND
CL*
12pF
0V
*INCLUDES TRACK CAPACITANCE
Figure 46. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor
Rev. B | Page 21 of 29
12698-045
SOURCE
VOLTAGE
(VS)
NEGFV
0.1µF
POSFV
POSFV + 0.5V
0.1µF
ADG5462F
Data Sheet
VDD VSS
0.1µF
POSFV
0.1µF
NEGFV
0.1µF
POSFV
INPUT
VOLTAGE 50%
(VDR)
VDD VSS
NEGFV
3V
0.1µF
VS > POSFV + VT
OUTPUT
S1
0V
D
S2 TO S4
tRESPONSE (DR)
CL*
12pF
ADG5462F
POSFV × 0.9
DR
OUTPUT
(VD)
0V
*INCLUDES TRACK CAPACITANCE
Figure 47. Drain Enable Time with Overvoltage, tRESPONSE (DR)
Rev. B | Page 22 of 29
12698-046
GND
Data Sheet
ADG5462F
TERMINOLOGY
tDIGREC
tDIGREC is the time required for the FF pin to return high, measured
with respect to voltage on the Sx pin falling below the supply
voltage plus 0.5 V.
IDD
IDD represents the positive primary supply current.
ISS
ISS represents the negative primary supply current.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 90% of the supply voltage.
IPOSFV
IPOSFV represents the positive secondary supply current.
INEGFV
INEGFV represents the negative secondary supply current.
VD, VS
VD and VS represent the analog voltage on the Dx pins and the
Sx pins, respectively.
RON
RON represents the ohmic resistance between the Dx pins and
the Sx pins.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT(ON)
RFLAT(ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
tRECOVERY
tRECOVERY represents the delay between an overvoltage on the Sx
pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 10% of the supply voltage.
tRESPONSE (DR)
tRESPONSE (DR) represents the delay between the voltage at the DR
pin falling from a high to low signal and the output of the drain
pin reaching 90% of either POSFV or NEGFV
Channel-to-Channel Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
VINH
VINH is the minimum input voltage for Logic 1.
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. ACPSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
0.62 V p-p.
CD (On), CS (On)
CD (On) and CS (On) represent the on switch capacitances,
which are measured with reference to ground.
CIN
CIN is the digital input capacitance.
tDIGRESP
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to voltage on the source pin exceeding
the supply voltage by 0.5 V.
VT
VT is the voltage threshold at which the overvoltage protection
circuitry engages. See Figure 23
Rev. B | Page 23 of 29
ADG5462F
Data Sheet
THEORY OF OPERATION
VIN
SWITCH ARCHITECTURE
Each channel of the ADG5462F consists of a parallel pair of
NDMOS and PDMOS transistors. This construction provides
excellent performance across the signal range. The ADG5462F
channels present only as a typical impedance of 10 Ω when input
signals with a voltage between POSFV and NEGFV are applied.
The maximum voltage that can be applied to any source input
is −55 V or +55 V. When the device is powered using a single
supply of 25 V or greater, the maximum negative signal level is
reduced. It reduces from −55 V at VDD = +25 V to −40 V at VDD =
+40 V to remain within the 80 V maximum rating. Construction of
the silicon process allows the channel to withstand 80 V across
the switch when it is opened. These overvoltage limits apply
whether the power supplies are present or not.
POSFV
ESD
PROTECTION
ESD
DR
SWITCH
DRIVER
ESD
NEGFV
LOGIC
BLOCK
VPOSFV + VT
OUTPUT
DRAINS
THROUGH
LOAD
OUTPUT
CLAMPED
AT VPOSFV
OUTPUT SHOWN FOR
DR = GND
OUTPUT SHOWN FOR
DR = FLOATING/HIGH
Figure 49. Drain Output Response During Overvoltage Condition
During overvoltage conditions, the leakage current into and out
of the source pins (Sx) is limited to tens of microamperes. If the
DR pin is allowed to float or is driven high, only nanoamperes
of leakage are seen on the drain pins (Dx). If the DR pin is driven
low, the drain pin (Dx) is pulled to the rail. The device that pulls
the drain pin to the rail has an impedance of approximately 40 kΩ;
therefore, the Dx pin current is limited to about 1 mA during a
shorted load condition. This internal impedance also determines
the minimum external load resistance required to ensure that
the drain pin is pulled to the desired voltage level during a fault.
ESD Performance
12698-047
FAULT
DETECTOR
VPOSFV + VT
VOUT
When an overvoltage event occurs, the channels undisturbed by
the overvoltage input continue to operate normally without
additional crosstalk.
Dx
Sx
VOUT
The ADG5462F has an ESD rating of 4 kV for the human body
model.
Figure 48. Switch Channel and Control Function
When an overvoltage condition is detected on a source pin (Sx),
the switch automatically opens and the source pin (Sx) becomes
high impedance and ensures that no current flows through the
switch. If the DR pin is driven low, the drain pin (Dx) is pulled
to the supply that was exceeded. For example, if the source voltage
exceeds POSFV, the drain output pulls to POSFV. The same is
true for NEGFV. In Figure 27, the voltage on the drain pin (Dx)
clamps to the POSFV voltage when the source voltage exceeds
POSFV by VT. If the DR pin is allowed to float or is driven high,
the drain pin (Dx) also goes open circuit. In Figure 25, the voltage
on the drain pin (Dx) follows the voltage on the source pin
(Sx) until the switch turns off completely and the drain voltage
discharges through the load. The output response for each drain
pin configuration is shown in Figure 49. The maximum voltage
on the drain is limited by the internal ESD diodes and the rate
at which the output voltage discharges is dependent on the load at
the pin.
12698-148
Additional internal circuitry enables the switch to detect
overvoltage inputs by comparing the voltage on the source
pin (Sx) with POSFV and NEGFV. A signal is considered
overvoltage if it exceeds the secondary supply voltages by the
voltage threshold (VT). The threshold voltage is typically 0.7 V,
but it ranges from 0.8 V at −40°C down to 0.6 V at +125°C. See
Figure 23 to see the change in VT with operating temperature.
VPOSFV + VT
The drain pins (Dx) have ESD protection diodes to the secondary
supply rails, and the voltage at these pins must not exceed the
secondary supply voltage.
The source pins (Sx) have specialized ESD protection that allows
the signal voltage to reach ±55 V with a ±22 V dual supply, and
from −40 V to +55 V with a +40 V single supply. See Figure 48
for the switch channel overview. Exceeding ±55 V on any source
input may damage the ESD protection circuitry on the device.
Rev. B | Page 24 of 29
Data Sheet
ADG5462F
Trench Isolation
The channel responds to an analog input that exceeds POSFV
or NEGFV by a threshold voltage (VT) by turning off. The absolute
input voltage limits are −55 V and +55 V, while maintaining an
80 V limit between the source pin (Sx) and the supply rails. The
switch remains off until the voltage at the source pin (Sx) returns to
between POSFV and NEGFV.
In the ADG5462F, an insulating oxide layer (trench) is placed
between the NDMOS and the PDMOS transistors of each channel.
Parasitic junctions, which occur between the transistors in junction
isolated switches, are eliminated, and the result is a switch that
is latch-up immune under all circumstances. This device passes
a JESD78D latch-up test of ±500 mA for 1 sec, which is the
harshest test in the specification.
NDMOS
PDMOS
The fault response time (tRESPONSE) when powered by a ±15 V dual
supply is typically 460 ns, and the fault recovery time (tRECOVERY) is
720 ns. These values vary with supply voltage and output load
conditions.
The maximum stress across the channel and between the source
pin (Sx) and any supply pin is 80 V; therefore, pay close attention
to this limit if using the device in a single-supply configuration and
a negative overvoltage is applied to the device.
For example, consider the case where the device is set up in a
single supply configuration, as shown in Figure 51.
•
•
•
TRENCH
VDD = POSFV = 36 V, VSS = NEGFV = GND = 0 V
S1 = +36 V, S2 = +5 V, and S3 = −40 V
The voltage difference from S1 to VDD/POSFV = 0 V, and to
VSS/NEGFV = 36 V
The voltage difference from S2 to VDD/POSFV = 31 V, and
to VSS/NEGFV = 5 V
The voltage difference from S3 to VDD/POSFV = 76 V, and
to VSS/NEGFV = 40 V
BURIED OXIDE LAYER
•
12698-048
•
Figure 50. Trench Isolation
USER DEFINED FAULT PROTECTION
POSFV and NEGFV are required secondary power supplies
that set the level at which the overvoltage protection is engaged.
POSFV can be supplied from 4.5 V up to VDD, and NEGFV can
be supplied from VSS to 0 V. If a secondary supply is not available,
these pins (POSFV and NEGFV) must be connected to VDD
(POSFV) and VSS (NEGFV). The overvoltage protection then
engages at the primary supply voltages. When the voltages at
the source inputs exceed POSFV or NEGFV by VT, the channel
turns off or, if the device is unpowered, the channel remains off.
The source input remains high impedance, and if the DR pin is
driven low, the drain pulls to either POSFV or NEGFV. Signal
levels up to −55 V and +55 V are blocked in both the powered
and unpowered condition as long as the 80 V limitation between
the source and supply pins is met.
These calculations are all within device specifications: 55 V
maximum fault on source inputs and a maximum of 80 V
across the channel or to a supply pin. The voltage on a source
pin (Sx) cannot go below −44 V to stay within +80 V maximum.
+36V
POSFV
HANDLE WAFER
•
•
•
The primary supply must be VDD to VSS ≥ 8 V.
For POSFV, the secondary supply must be between 4.5 V
and VDD, and for NEGFV, the secondary supply must be
between VSS and 0 V.
The input signal must be between NEGFV − VT and
POSFV + VT.
VDD GND VSS
ADG5262F
+36V
+5V
–40V
Power-On Protection
For the channel to be in the on condition, the following three
conditions must be satisfied:
0V
S1
D1
S2
D2
S3
D3
S4
D4
FAULT
DETECTION
+ SWITCH
DRIVER
12698-049
N-WELL
NEGFV
P-WELL
Figure 51. ADG5462F in Single-Supply Configuration Under Overvoltage
Conditions
When the channel is on, signal levels up to the secondary
supply rails are passed.
Rev. B | Page 25 of 29
ADG5462F
Data Sheet
Power-Off Protection
Overvoltage Interrupt Flag
When no power supplies are present, the channel remains in the
off condition, and the switch inputs are high impedance. This
state ensures that no current flows and prevents damage to the
switch or downstream circuitry. The switch output is a virtual
open circuit.
The voltages on the source inputs of the ADG5462F are
continuously monitored, and an active low digital output pin
(FF) indicates the state of the switches.
The switch remains off regardless of whether the primary and
secondary supplies are 0 V or floating. A GND reference must
always be present to ensure proper operation. Signal levels of up
to ±55 V are blocked in the unpowered condition.
The voltage on the FF pin indicates if any of the source input pins
are experiencing a fault condition. The output of the FF pin is a
nominal 3 V when all source pins (Sx) are within normal operating
range. If any source pin (Sx) voltage exceeds the supply voltage
by VT, the FF output reduces to below 0.8 V.
Digital Input Protection
The ADG5462F can tolerate digital input signals being present
on the device without power. The digital input is protected against
positive faults up to 44 V. The digital input does not offer protection
against negative overvoltages. ESD protection diodes connected
to GND are present on the digital input.
Rev. B | Page 26 of 29
Data Sheet
ADG5462F
APPLICATIONS INFORMATION
The overvoltage protected family of switches and multiplexers
provide robust solutions for instrumentation, industrial,
automotive, aerospace, and other harsh environments where
overvoltage signals can be present, and the system must remain
operational both during and after the overvoltage has occurred.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 μF decoupling
capacitors are required on the primary and secondary supplies.
If they are driven from the same supply, then one set of 0.1 μF
decoupling capacitors is sufficient.
The secondary supplies (POSFV and NEGFV) provide the
current required to operate the fault protection and, therefore,
must be low impedance supplies. Therefore, they can be derived
from the primary supply by using a resistor divider and buffer.
The secondary supply rails (POSFV and NEGFV) must not exceed
the primary supply rails (VDD and VSS) because this can lead to a
signal passing through the switch unintentionally.
The ADG5462F can operate with bipolar supplies between ±5 V
and ±22 V. The supplies on VDD and VSS need not be symmetrical
but the VDD and VSS range must not exceed 44 V. The ADG5462F
can also operate with single supplies between 8 V and 44 V with
VSS connected to GND.
The ADG5462F is fully specified at ±15 V, ±20 V, +12 V, and
+36 V supply ranges.
POWER SUPPLY SEQUENCING PROTECTION
The channels remain open when the device is unpowered and
signals from −55 V to +55 V can be applied without damaging
the device. Only when the supplies are connected, and the signal
is within normal operating range, do the channels close. Placing
the ADG5462F between external connectors and sensitive
components offers protection in systems where a signal is
presented to the source pins (Sx) before the supply voltages
are available.
POWER SUPPLY RECOMMENDATIONS
Table 8. Recommended Power Management Devices
Product
ADP7118
ADP7142
ADP7182
USER DEFINED SIGNAL RANGE
The primary supplies define the on-resistance profile of the
channels, while the secondary supplies define the signal range.
Using voltages on POSFV and NEGFV that are lower than VDD
and VSS, the required signal can benefit from the flat on resistance
in the center of the full signal capabilities of the device.
LOW IMPEDANCE CHANNEL PROTECTION
The ADG5462F can be used as a protective element in signal
chains that are sensitive to both channel impedance and
overvoltage signals. Traditionally, series resistors are used to
limit the current during an overvoltage condition to protect
susceptible components.
These series resistors affect the performance of the signal chain
and reduce the precision that can be reached. A compromise
must be reached on the value of the series resistance that is high
enough to sufficiently protect sensitive components but low
enough that the precision performance of the signal chain is not
sacrificed.
The ADG5462F enables the designer to remove these resistors
and retain the precision performance without compromising
the protection of the circuit.
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5462F is not intended for use in very high voltage
applications. The maximum operating voltage of the transistor
is 80 V. In applications where the inputs are likely to be subject
to overvoltages exceeding the breakdown voltage, use transient
voltage suppressors (TVSs) or similar.
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
+16V
12V
INPUT
ADP7118
+15V
ADP7182
–15V
LDO
–16V
LDO
12698-050
An example of a bipolar power solution is shown in Figure 52.
The ADP7118 and ADP7182 can be used to generate clean
positive and negative rails from the dual switching regulator
output. These rails can power the ADG5462F, an amplifier,
and/or a precision converter in a typical signal chain.
DUAL
SWITCHING
REGULATOR
Description
20 V, 200 mA, low noise, CMOS low dropout
regulator (LDO)
40 V, 200 mA, low noise, CMOS LDO
−28 V, −200 mA, low noise, linear regulator
Figure 52. Bipolar Power Solution
Rev. B | Page 27 of 29
ADG5462F
Data Sheet
INTELLIGENT FAULT DETECTION
The ADG5462F digital output pin (FF) can interface with a
microprocessor or control system and be used as an interrupt
flag. This feature provides real-time diagnostic information on
the state of the device and the system to which it connects.
The control system can use the digital interrupt to start a
variety of actions, such as
•
•
•
Initiating investigation into the source of the overvoltage fault
Shutting down critical systems in response to the overvoltage
Signaling the data recorders to mark data during these
events as unreliable or out of specification
For systems that are sensitive during a start-up sequence, the
active low operation of the flag allows the system to ensure that
the ADG5462F is powered on and that all input voltages are
within normal operating range before initiating operation.
The interrupt flag recovery time, tDIGREC, can be decreased from
a typical 60 µs to 600 ns by using a 1 kΩ pull-up resistor.
The DR pin can also be used for diagnostic purposes. The FF
pin provides an interrupt that indicates one of the four channels
has a fault. The DR pin can then be pulled low to find which of
the channels has a fault as well as the polarity of the fault. For
example, if an ADC downstream is monitoring the channel, a
full-scale reading then indicates a positive fault, and a zero-scale
reading indicates a negative fault.
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 24 illustrates the voltage range and frequencies that the
ADG5462F can reliably convey. For signals that extend across
the full signal range from VSS to VDD, keep the frequency less
than 3 MHz. If the required frequency is greater than 3 MHz,
decrease the signal range appropriately to ensure signal integrity.
The FF pin is a weak pull-up, which allows the signals to be
combined into a single interrupt for larger modules that contain
multiple devices.
Rev. B | Page 28 of 29
Data Sheet
ADG5462F
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 53. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.35
0.30
0.25
0.65
BSC
16
13
PIN 1
INDICATOR
12
1
EXPOSED
PAD
4
2.70
2.60 SQ
2.50
9
0.80
0.75
0.70
0.45
0.40
0.35
8
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
08-16-2010-C
TOP VIEW
Figure 54. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG5462FBRUZ
ADG5462FBRUZ-RL7
ADG5462FBCPZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Z = RoHS Compliant Part.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12698-0-1/16(B)
Rev. B | Page 29 of 29
Package Option
RU-16
RU-16
CP-16-17