Wavescale Video Codec ADV212 FEATURES APPLICATIONS Implementation of a JPEG2000-compatible video CODEC for video and still images through the ADV212 Wavescale video compression/decompression engine Identical pinout and footprint to the ADV202; and support for all the functionality of the ADV202 Power reduction of at least 30% compared with ADV202 JTAG/boundary scan support Patented spatial ultraefficient recursive filtering (SURF) technology for low power, low cost wavelet-based compression Support for both 9/7 and 5/3 wavelet transforms with up to 5 levels of transform 9/7 wavelet support for tiles up to 1.048 million samples 5/3 wavelet support for tiles up to 262,144 samples Video interface direct support for ITU-R BT.656, SMPTE 125M PAL/NTSC, SMPTE 274M, SMPTE 293M (525p), and ITU-R BT.1358 (625p) or any video format with a maximum input rate of 65 MSPS for irreversible mode or 40 MSPS for reversible mode Programmable tile/image size with widths of up to 4096 pixels in single-component mode; maximum tile/image height of 4096 pixels Ability to combine 2 or more ADV212s to support full-frame SMPTE 274M HDTV (1080i) or SMPTE 296M (720p) Flexible, asynchronous SRAM-style host interface support for glueless connection to most 16-/32-bit microcontrollers and ASICs 2.5 V or 3.3 V input/output and 1.5 V core supply 2 package and speed grade options 12 mm × 12 mm, 121-ball CSP_BGA with a speed grade of 115 MHz 13 mm × 13 mm, 144-ball CSP_BGA with a speed grade of 150 MHz Networked video and image distribution systems Wireless video and image distribution Image archival/retrieval Digital CCTV and surveillance systems Digital cinema systems Professional video editing and recording Digital still cameras Digital camcorders GENERAL DESCRIPTION The ADV212 Wavescale® video compression/decompression (CODEC) is a single-chip JPEG2000 CODEC targeted for video and high bandwidth image compression applications that can benefit from the enhanced quality and features provided by the JPEG2000 (J2K) ISO/IEC15444-1 image compression standard. The part implements the computationally intensive operations of the JPEG2000 image compression standard and provides fully compliant code stream generation for most applications. The dedicated video port of the ADV212 provides glueless connection to common digital video standards such as ITU-R BT.656, SMPTE 125M, SMPTE 293M (525p), ITU-R BT.1358 (625p), SMPTE 274M (1080i), and SMPTE 296M (720p). A variety of other high speed, synchronous pixel and video formats can also be supported by using the programmable framing and validation signals. The ADV212 is an upgrade version of the ADV202, which is identical in pinout and footprint. It supports all of the functionality of the ADV202 and has the following additional options: JTAG/boundary scan support and power reduction of at least 30% compared with the ADV202. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved. ADV212 TABLE OF CONTENTS Features .............................................................................................. 1 Memory System .......................................................................... 25 Applications ....................................................................................... 1 Internal DMA Engine ................................................................ 25 General Description ......................................................................... 1 ADV212 Interfaces ......................................................................... 26 Revision History ............................................................................... 2 Video Interface (VDATA Bus).................................................. 26 JPEG2000 Feature Support .............................................................. 3 Host Interface (HDATA Bus) ................................................... 26 Functional Block Diagram .............................................................. 3 Direct and Indirect Registers .................................................... 26 Specifications..................................................................................... 4 Control Access Registers ........................................................... 27 Supply Voltages and Current ...................................................... 4 Pin Configuration and Bus Sizes/Modes ................................ 27 Input/Output Specifications........................................................ 4 Stage Register .............................................................................. 27 Clock and RESET Specifications ................................................ 5 JDATA Mode............................................................................... 27 Normal Host Mode—Write Operation ..................................... 6 Normal Host Mode—Read Operation ...................................... 7 DREQ/DACK DMA Mode—Single FIFO Write Operation .. 8 DREQ/DACK DMA Mode—Single FIFO Read Operation . 10 External DMA Mode—FIFO Write, Burst Mode .................. 12 External DMA Mode—FIFO Read, Burst Mode ................... 13 Streaming Mode (JDATA)—FIFO Read/Write ...................... 14 VDATA Mode Timing ............................................................... 15 Raw Pixel Mode Timing ............................................................ 17 JTAG Timing ............................................................................... 18 Absolute Maximum Ratings.......................................................... 19 Thermal Resistance .................................................................... 19 ESD Caution ................................................................................ 19 Pin Configurations and Function Descriptions ......................... 20 Theory of Operation ...................................................................... 25 Wavelet Engine ........................................................................... 25 Entropy CODECs ....................................................................... 25 External DMA Engine ............................................................... 27 Internal Registers ............................................................................ 28 Direct Registers........................................................................... 28 Indirect Registers ........................................................................ 29 PLL Registers .............................................................................. 30 Hardware Boot Modes and Power Considerations ............... 31 Video Input Formats ...................................................................... 32 Applications Information .............................................................. 34 Encode—Multichip Mode......................................................... 34 Decode—Multichip Master/Slave ............................................ 35 Digital Still Camera/Camcorder .............................................. 36 Encode/Decode SDTV Video Application ............................. 37 32-Bit Host Application ............................................................. 38 HIPI (Host Interface—Pixel Interface) ................................... 39 JDATA Interface ......................................................................... 40 Outline Dimensions ....................................................................... 41 Ordering Guide .......................................................................... 42 Embedded Processor System .................................................... 25 REVISION HISTORY 4/10—Rev. A to Rev. B Added Wavescale Information .................................... Throughout Changes to Features Section............................................................ 1 Changes to Table 16 ........................................................................ 20 Changes to Video Interface (VDATA Bus) Section, Changes to Table 17 ............................................................................................ 26 Changes to Hardware Boot Modes Section ................................ 31 Changes to Encode—Multichip Mode Section .......................... 34 4/08—Rev. 0 to Rev. A Change to Table 1, Static Current Parameter.................................4 10/06—Revision 0: Initial Version Rev. B | Page 2 of 44 ADV212 JPEG2000 FEATURE SUPPORT The ADV212 can process images at a rate of 40 MSPS in reversible mode and at higher rates when used in irreversible mode. The ADV212 contains a dedicated wavelet transform engine, three entropy CODECs, an on-board memory system, and an embedded reduced instruction set computer (RISC) processor that can provide a complete JPEG2000 compression/ decompression solution. The ADV212 supports a broad set of features that are included in Part 1 of the JPEG2000 standard (ISO/IEC 15444). Depending on the particular application requirements, the ADV212 can provide varying levels of JPEG2000 compression support. It can provide raw code block and attribute data output, which allows the host software to have complete control over generation of the JPEG2000 code stream and other aspects of the compression process such as bit-rate control. Additionally, the ADV212 can create a complete, fully compliant JPEG2000 code stream (J2C) and enhanced file formats such as JP2. The wavelet processor supports the 9/7 irreversible wavelet transform and the 5/3 wavelet transform in reversible and irreversible modes. The entropy CODECs support all features in the JPEG2000 Part 1 specification except maximum shift region of interest (ROI). The ADV212 operates on a rectangular array of pixel samples called a tile. A tile can contain a complete image, up to the maximum supported size, or some portion of an image. The maximum horizontal tile size supported depends on the wavelet transform selected and the number of samples in the tile. Images larger than the ADV212 maximum tile size can be broken into individual tiles and then sent sequentially to the chip while maintaining a single, fully compliant JPEG2000 code stream for the entire image. FUNCTIONAL BLOCK DIAGRAM PIXEL I/F PIXEL I/F WAVELET ENGINE EC1 EC2 EC3 EXTERNAL DMA CTRL PIXEL FIFO INTERNAL BUS AND DMA ENGINE CODE FIFO ATTR FIFO ADV212 EMBEDDED RISC PROCESSOR SYSTEM Figure 1. Rev. B | Page 3 of 44 RAM ROM 06389-001 HOST I/F ADV212 SPECIFICATIONS Specifications apply to IOVDD = 2.5 V or 3.3 V over the operating temperature range, unless otherwise specified. SUPPLY VOLTAGES AND CURRENT Table 1. Parameter DC Supply Voltage, Core DC Supply Voltage, Input/Output Mnemonic VDD IOVDD IOVDD VIN T IDD Input Range Operating Ambient Temperature Range in Free Air Static Current 1 Dynamic Current, Core (JCLK2 Frequency = 150 MHz)3 Dynamic Current, Core (JCLK2 Frequency = 108 MHz) Dynamic Current, Core (JCLK2 Frequency = 81 MHz) Dynamic Current, Input/Output Min 1.425 2.375 3.135 −0.3 −40 Typ 1.5 2.5 3.3 +25 60 380 280 210 40 Max 1.575 2.625 3.465 VDDI/O + 0.3 +85 440 320 290 50 No clock or input/output activity. For a definition of JCLK, see Figure 32. 3 ADV212-150 only. 1 2 INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current High Level Three-State Leakage Current Low Level Three-State Leakage Current Input Pin Capacitance Output Pin Capacitance Mnemonic VIH (3.3 V) VIH (2.5 V) VIL (3.3 V, 2.5 V) VOH (3.3 V) VOH (2.5 V) VOL (3.3 V, 2.5 V) IIH IIL IOZH IOZL CI CO Min 2.2 1.9 Typ Max 0.6 2.4 2.0 Rev. B | Page 4 of 44 0.4 1.0 1.0 1.0 1.0 8 8 Unit V V V V V V µA µA µA µA pF pF Test Conditions VDD = maximum VDD = maximum VDD = minimum VDD = minimum, IOH = −0.5 mA VDD = minimum, IOH = −0.5 mA VDD = minimum, IOL = +2 mA VDD = maximum, VIN = VDD VDD = maximum, VIN = 0 V VDD = maximum, VIN = VDD VDD = maximum, VIN = 0 V Unit V V V V °C mA mA mA mA mA ADV212 CLOCK AND RESET SPECIFICATIONS Table 3. Parameter MCLK Period MCLK Frequency MCLK Width Low MCLK Width High VCLK Period VCLK Frequency VCLK Width Low VCLK Width High RESET Width Low Min 13.3 10 6 6 13.4 20 5 5 5 Typ Max 100 75.18 50 74.60 Unit ns MHz ns ns ns MHz ns ns MCLK cycles1 For a definition of MCLK, see Figure 32. tMCLK tMCLKH tMCLKL MCLK tVCLK tVCLKL tVCLKH 06389-010 1 Mnemonic tMCLK fMCLK tMCLKL tMCLKH tVCLK fVCLK tVCLKL tVCLKH tRESET VCLK Figure 2. Input Clock Rev. B | Page 5 of 44 ADV212 NORMAL HOST MODE—WRITE OPERATION Table 4. Parameter WE to ACK, Direct Registers and FIFO Accesses Mnemonic tACK (direct) Min 5 WE to ACK, Indirect Registers tACK (indirect) 5 Data Setup Data Hold Address Setup Address Hold CS to WE Setup CS Hold Write Inactive Pulse Width (Minimum Time Until Next WE Pulse) Write Active Pulse Width Write Cycle Time tSD tHD tSA tHA tSC tHC tWH tWL tWCYC 3.0 1.5 2 2 0 0 2.5 JCLK1 2.5 JCLK1 5 JCLK1 Max 1.5 × JCLK + 7.01 2.5 × JCLK + 7.01 For a definition of JCLK, see Figure 32. tSA tHA ADDR tSC tHC CS tWCYC tWL tWH WE tACK ACK tHD tSD HDATA VALID Figure 3. Normal Host Mode—Write Operation Rev. B | Page 6 of 44 Unit ns ns ns ns ns ns ns ns ns ns ns 06389-012 1 Typ ADV212 NORMAL HOST MODE—READ OPERATION Table 5. Parameter RD to ACK, Direct Registers and FIFO Accesses Mnemonic tACK (direct)1 Min 5 Typ Max 1.5 × JCLK + 7.02 Unit ns RD to ACK, Indirect Registers tACK (indirect)1 10.5 JCLK2 15.5 × JCLK + 7.02 ns Read Access Time, Direct Registers Read Access Time, Indirect Registers Data Hold CS to RD Setup Address Setup CS Hold Address Hold Read Inactive Pulse Width Read Active Pulse Width Read Cycle Time, Direct Registers tDRD (direct) tDRD (indirect) tHZRD tSC tSA tHC tHA tRH tRL tRCYC 5 10.5 JCLK2 2 0 2 0 2 2.5 JCLK2 2.5 JCLK2 5.0 JCLK2 1.5 × JCLK + 7.02 15.5 × JCLK + 7.02 8.5 ns ns ns ns ns ns ns ns ns ns Timing relationship between ACK falling transition and HDATA valid is not guaranteed. HDATA valid hold time is guaranteed with respect to RD rising transition. A minimum of three JCLK cycles is recommended between ACK assert and RD deassert. 2 For a definition of JCLK, see Figure 32. 1 tHA tSA ADDR tHC tSC CS tRCYC tRH tRL RD tACK tDRD HDATA tHZRD VALID Figure 4. Normal Host Mode—Read Operation Rev. B | Page 7 of 44 06389-011 ACK ADV212 DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION Table 6. Parameter DREQ Pulse Width DACK Assert to Subsequent DREQ Delay Mnemonic DREQPULSE tDREQ Min 1 JCLK1 2.5 JCLK1 WE to DACK Setup tWESU 0 ns Data to DACK Deassert Setup Data to DACK Deassert Hold DACK Assert Pulse Width DACK Deassert Pulse Width WE Hold After DACK Deassert tSU tHD DACKLOW DACKHIGH tWEHD 2 2 2 JCLK1 2 JCLK1 0 ns ns ns ns ns WE Assert to FSRQ Deassert (FIFO Full) DACK to DREQ Deassert (DR × PULS = 0) WFSRQ tDREQRTN 1.5 JCLK1 2.5 JCLK1 Max 15 JCLK1 3.5 × JCLK + 8.51 Unit ns ns 2.5 × JCLK + 7.51 3.5 × JCLK + 9.01 ns ns For a definition of JCLK, see Figure 32. DREQPULSE tDREQ DREQ DACK HIGH DACK LOW DACK tWESU tWEHD WE 0 HDATA 1 2 3 06389-013 tHD tSU Figure 5. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1[14:1] Not Programmed to a Value of 0000) tDREQ RTN DREQ DACK HIGH DACK LOW DACK tWESU tWEHD WE tHD tSU HDATA 0 1 2 Figure 6. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000) Rev. B | Page 8 of 44 06389-014 1 Typ ADV212 DREQPULSE tDREQ DREQ DACK HIGH DACK LOW DACK tWESU tWEHD WEFB tHD 0 HDATA 1 06389-015 tSU 2 Figure 7. Single Write Cycle for Fly-By DMA Mode (DREQ Pulse Width Is Programmable) FCS0 RD WFSRQ FIFO NOT FULL FIFO FULL 0 HDATA tSU 1 tHD 2 NOT WRITTEN TO FIFO Figure 8. Single Write Access for DCS DMA Mode Rev. B | Page 9 of 44 06389-021 FSRQ0 ADV212 DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION Table 7. Parameter DREQ Pulse Width DACK Assert to Subsequent DREQ Delay Mnemonic DREQPULSE tDREQ Min 1 JCLK 1 2.5 JCLK1 RD to DACK Setup tRDSU 0 DACK to Data Valid tRD 2.5 Data Hold DACK Assert Pulse Width DACK Deassert Pulse Width RD Hold after DACK Deassert tHD DACKLOW DACKHIGH tRDHD 1.5 2 JCLK1 2 JCLK1 0 RD Assert to FSRQ Deassert (FIFO Empty) DACK to DREQ Deassert (DR × PULS = 0) RDFSRQ tDREQRTN 1.5 JCLK1 2.5 JCLK1 Max 15 JCLK1 3.5 × JCLK + 9.01 Unit ns ns ns 11 ns ns ns ns ns 2.5 × JCLK + 9.01 3.5 × JCLK + 9.01 ns ns For a definition of JCLK, see Figure 32. DREQPULSE tDREQ DREQ DACK HIGH DACK LOW DACK tRDHD tRDSU RD HDATA tHD 0 1 06389-018 tRD 2 Figure 9. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1[14:11] Not Programmed to a Value of 0000) tDREQ RTN DREQ DACK HIGH DACK LOW DACK tRDHD tRDSU RD tRD HDATA tHD 0 1 2 Figure 10. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000) Rev. B | Page 10 of 44 06389-019 1 Typ ADV212 DREQPULSE tDREQ DREQ DACK HIGH DACK LOW DACK tRDSU tRDHD tRD HDATA tHD 0 1 2 06389-020 RDFB Figure 11. Single Read Cycle for Fly-By DMA Mode (DREQ Pulse Width Is Programmable) FCS0 RD RDFSRQ FIFO NOT EMPTY FSRQ0 FIFO EMPTY HDATA 0 1 Figure 12. Single Read Access for DCS DMA Mode Rev. B | Page 11 of 44 06389-090 tHD tRD ADV212 EXTERNAL DMA MODE—FIFO WRITE, BURST MODE Table 8. Parameter DREQ Pulse Width1 WE to DREQ Deassert (DR × PULS = 0) Mnemonic DREQPULSE tDREQRTN Min 1 JCLK 2 2.5 JCLK2 DACK to WE Setup tDACKSU 0 ns Data Setup Data Hold WE Assert Pulse Width WE Deassert Pulse Width WE Deassert to Next DREQ tSU tHD WELOW WEHIGH tDREQWAIT 2.5 2 1.5 JCLK2 1.5 JCLK2 2.5 JCLK2 ns ns ns ns ns WE Deassert to DACK Deassert tWE_DACK 0 Unit ns ns 4.5 × JCLK + 9.02 ns Applies to assigned DMA channel, if EDMOD0/EDMOD1[14:11] is programmed to a nonzero value. For a definition of JCLK, see Figure 32. DREQPULSE tDREQ WAIT DREQ tWE_DACK DACK tDACK SU WEHIGH WELOW WE tHD HDATA 0 1 14 13 06389-022 tSU 15 Figure 13. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1[14:1] Not Programmed to a Value of 0000) tDREQ RTN tDREQ WAIT DREQ tWE_DACK DACK tDACK SU WELOW WEHIGH WE tHD tSU HDATA 0 1 13 14 06389-023 2 Max 15 JCLK2 3.5 × JCLK + 7.52 15 Figure 14. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000) tDREQ RTN tDREQ WAIT DREQ tWE_DACK DACK tDACK SU WEHIGH WELOW WEFB tHD tSU HDATA 0 1 13 14 Figure 15. Burst Write Cycle for Fly-By DMA Mode Rev. B | Page 12 of 44 15 06389-024 1 Typ ADV212 EXTERNAL DMA MODE—FIFO READ, BURST MODE Table 9. Parameter DREQ Pulse Width1 RD to DREQ Deassert (DR × PULS = 0) Mnemonic DREQPULSE tDREQRTN Min 1 JCLK 2 2.5 JCLK2 DACK to RD Setup tDACKSU 0 RD to Data Valid tRD 2.5 Data Hold RD Assert Pulse Width RD Deassert Pulse Width RD Deassert to Next DREQ tHD RDLOW RDHIGH tDREQWAIT 2.5 1.5 JCLK2 1.5 JCLK2 2.5 JCLK2 RD Deassert to DACK Deassert tRD_DACK 0 Unit ns ns ns 9.7 ns 3.5 × JCLK + 7.52 ns ns ns ns ns Applies to assigned DMA channel if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value. For a definition of JCLK, see Figure 32. tDREQ PULSE tDREQ WAIT DREQ tRD_DACK DACK tDACK SU RDLOW RDHIGH RD 0 HDATA 1 13 14 06389-025 tHD 15 tRD Figure 16. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel (EMOD0/EDMOD1[14:11] Not Programmed to a Value of 0 tDREQ WAIT DREQ tRD_DACK tDREQ RTN DACK tDACK SU RDHIGH RDLOW RD tHD 0 HDATA 1 13 14 15 06389-026 2 Max 15 JCLK2 3.5 × JCLK + 7.52 tRD Figure 17. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel (EMOD0/EDMOD1[14:11] Programmed to a Value of 0000) tDREQ RTN tDREQ WAIT DREQ tRD_DACK DACK tDACK SU RDFB tHD HDATA 0 1 13 14 tRD Figure 18. Burst Read Cycle for Fly-By DMA Mode Rev. B | Page 13 of 44 15 06389-027 1 Typ ADV212 STREAMING MODE (JDATA)—FIFO READ/WRITE Table 10. Parameter MCLK to JDATA Valid MCLK to VALID Assert/Deassert HOLD Setup to Rising MCLK HOLD Hold from Rising MCLK JDATA Setup to Rising MCLK JDATA Hold from Rising MCLK Min 1.5 JCLK1 1.5 JCLK1 3 3 3 3 Typ Max 2.5 × JCLK + 9.51 2.5 × JCLK + 8.01 Unit ns ns ns ns ns ns For a definition of JCLK, see Figure 32. MCLK JDATAHD JDATATD JDATA JDATASU VALIDTD HOLDHD HOLDSU HOLD 06389-028 VALID Figure 19. Streaming Mode Timing—Encode Mode JDATA Output MCLK JDATASU JDATAHD JDATA VALIDTD VALID HOLDHD HOLDSU 06389-029 1 Mnemonic JDATATD VALIDTD HOLDSU HOLDHD JDATASU JDATAHD HOLD Figure 20. Streaming Mode Timing—Decode Mode JDATA Input Rev. B | Page 14 of 44 ADV212 VDATA MODE TIMING Table 11. Parameter VCLK to VDATA Valid Delay (VDATA Output) VDATA Setup to Rising VCLK (VDATA Input) VDATA Hold from Rising VCLK (VDATA Input) HSYNC Setup to Rising VCLK HSYNC Hold from Rising VCLK VCLK to HSYNC Valid Delay VSYNC Setup to Rising VCLK VSYNC Hold from Rising VCLK VCLK to VSYNC Valid Delay FIELD Setup to Rising VCLK FIELD Hold from Rising VCLK VCLK to FIELD Valid Decode Slave Data Sync Delay (HSYNC Low to First 0xFF of EAV/SAV Code) Decode Slave Data Sync Delay (HSYNC Low to First Data for HVF Mode) Min Typ Max 12 Unit ns ns ns ns ns ns ns ns ns ns ns 4 4 3 4 12 3 4 12 4 3 12 81 VCLK cycles 101 VCLK cycles The sync delay value varies according to the application. VCLK VDATASU VDATA (IN) Cr Y Cb Y FF 00 00 EAV FF 00 SAV 00 Cb Y 06389-091 VDATAHD Cr Figure 21. Encode Video Mode Timing—CCIR 656 Mode VCLK HSYNCHD HSYNCSU VDATA (IN) Cb Y Cr Y Cb Y Cr 06389-092 HSYNC Y Figure 22. Encode Video Mode Timing—HVF Mode (HSYNC Timing) (HSYNC Programmed for Negative Polarity) VCLK VSYNCHD VSYNCSU VSYNC FIELDSU FIELDHD FIELD Figure 23. Encode Video Mode Timing—HVF Mode (VSYNC and FIELD Timing) (VSYNC and FIELD Programmed for Negative Polarity) Rev. B | Page 15 of 44 06389-093 1 Mnemonic VDATATD VDATASU VDATAHD HSYNCSU HSYNCHD HSYNCTD VSYNCSU VSYNCHD VSYNCTD FIELDSU FIELDHD FIELDTD SYNC DELAY ADV212 VCLK VDATATD FF VDATA (OUT) 00 00 HSYNCSU HSYNC (IN) EAV Cb Y HSYNCHD VSYNCHD VSYNCSU SYNC DELAY VSYNC (IN) 06389-094 FIELDSU FIELD (IN) Figure 24. Decode Video Mode Timing—CCIR 656 Mode, Decode Slave (HSYNC, VSYNC, and FIELD Programmed to Negative Polarity) VCLK VDATATD Cb VDATA (OUT) Y Cr HSYNCSU Y Cb Y HSYNCHD HSYNC (IN) VSYNCHD VSYNCSU SYNC DELAY VSYNC (IN) 06389-095 FIELDSU FIELD (IN) Figure 25. Decode Video Mode Timing—HVF Mode, Decode Slave (HSYNC, VSYNC, and FIELD Programmed to Negative Polarity) VCLK VDATATD VDATA (OUT) FF Cb 00 00 SAV Cb Y Cr Y Cb Y Cr HSYNCTD HSYNC (OUT) VSYNCTD VSYNC (OUT) 06389-096 FIELDTD FIELD (OUT) Figure 26. Decode Video Mode Timing—CCIR 656 Mode, Decode Master (HSYNC, VSYNC, and FIELD Programmed to Negative Polarity) VCLK VDATATD Cb VDATA (OUT) Y Cr Y Cb HSYNC (OUT) VSYNCTD VSYNC (OUT) 06389-097 FIELDTD FIELD (OUT) Figure 27. Decode Video Mode Timing—HVF Mode, Decode Master (HSYNC, VSYNC, and FIELD Programmed to Negative Polarity) Rev. B | Page 16 of 44 ADV212 RAW PIXEL MODE TIMING Table 12. Parameter VCLK to PIXELDATA Valid Delay (PIXELDATA Output)1 PIXELDATA Setup to Rising VCLK (PIXELDATA Input) PIXELDATA Hold from Rising VCLK (PIXELDATA Input) VCLK to VRDY Valid Delay VFRM Setup to Rising VCLK (VFRAME Input) VFRM Hold from Rising VCLK (VFRAME Input) VCLK to VFRM Valid Delay (VFRAME Output) VSTRB Setup to Rising VCLK VSTRB Hold from Rising VCLK Min Typ Max 12 Unit ns ns ns ns ns ns ns ns ns 4 4 12 3 4 12 4 3 PIXELDATA is the actual data on the VDATA bus; pins and bus width depend on it but timing does not. VCLK VDATASU PIXELDATA (IN) PIXEL 1 VFRMSU VDATAHD PIXEL 2 PIXEL 3 VFRMHD VFRM (IN) VRDYTD VRDY (OUT) VSTRBHD VSTRBSU VSTRB (IN) RAW PIXEL MODE—ENCODE VCLK VDATATD PIXELDATA (OUT) PIXEL 1 PIXEL 2 PIXEL 3 VFRMTD VFRM (OUT) VRDYTD VRDY (OUT) VSTRBHD VSTRBSU VSTRB (IN) RAW PIXEL MODE—DECODE Figure 28. Raw Pixel Modes Rev. B | Page 17 of 44 06389-031 1 Mnemonic VDATATD VDATASU VDATAHD VRDYTD VFRMSU VFRMHD VFRMTD VSTRBSU VSTRBHD ADV212 JTAG TIMING Table 13. Parameter TCK Period TDI or TMS Setup Time TDI or TMS Hold Time TDO Hold Time TDO Valid TRS Hold Time TRS Setup Time TRS Pulse Width Low Mnemonic TCK TDISU TDIHD TDOHD TDOVALID TRSHD TRSSU TRSLOW Min 134 4.0 4.0 0.0 Typ Max 10.0 4.0 4.0 4 Unit ns ns ns ns ns ns ns TCK cycles TCK TDOVALID TDOHD TDO TDISU TDIHD TDI TMS TRSHD 06389-032 TRSSU TRS Figure 29. JTAG Timing Rev. B | Page 18 of 44 ADV212 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 14. Parameter VDD − Supply Voltage, Core IOVDD − Supply Voltage, Input/Output Storage Temperature (TS) Reflow Soldering RoHS-Compliant, 121-Ball RoHS-Compliant, 144-Ball θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.3 V to +1.65 V −0.3 V to +3.63 V Table 15. Thermal Resistance Package Type 144-Ball ADV212BBCZ 121-Ball ADV212BBCZ −65°C to +150°C 260°C (20 sec to 40 sec) 260°C (20 sec to 40 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 19 of 44 θJA 22.5 32.8 θJC 3.8 7.92 Unit °C/W °C/W ADV212 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 11 10 9 8 7 6 5 4 3 1 A B C D E F G H J K L M 06389-035 A B C D E F G H J K L BOTTOM VIEW (Not to Scale) 2 BOTTOM VIEW (Not to Scale) Figure 30.121-Ball Pin Configuration 06389-036 12 11 10 9 8 7 6 5 4 3 2 1 Figure 31. 144-Ball Pin Configuration Table 16. Pin Function Descriptions 121-Ball Package 144-Ball Package Pin No. 119 Location L9 Pin No. 132 Location L12 Mnemonic MCLK Pins Used 1 Type I 117 L7 131 L11 RESET 1 I 37 to 34, 27 to 25, 16, 15, 24, 14 to 12, 2, 6, 5 D4 to D1, C5 to C3, B5, B4, C2, B3 to B1, A2, A6, A5 64, 49 to 51, 37 to 39, 25 to 27, 13 to 15, 2 to 4 F4, E1 to E3, D1 to D3, C1 to C3, B1 to B3, A2 to A4 HDATA[15:0] 16 I/O 88, 107, 87, 97 96 H11, K8, H10, J9 J8 108 to 106, 96 95 J12 to J10, H12 H11 ADDR[3:0] 4 I CS 1 I 95 J7 94 H10 WE1 RDFB2 1 I 86 H9 84 G12 RD1 WEFB3 1 I Rev. B | Page 20 of 44 Description System Input Clock. See the PLL Registers section. Reset. Causes the ADV212 to immediately reset. CS, RD, WE, DACK0, DACK1, DREQ0, and DREQ1 must be held high when a RESET is applied. Host Data Bus. With HDATA[23:16], HDATA[27:24], and HDATA[31:28], these pins make up the 32-bit wide host data bus. The async host interface is interfaced together with ADDR[3:0], CS, WE, RD, and ACK. Unused HDATA pins should be pulled down via a 10 kΩ resistor. Address Bus for the Host Interface. Chip Select. This signal is used to qualify addressed read and write access to the ADV212 using the host interface. Write Enable Used with the Host Interface. Read Enable When Fly-By DMA Is Enabled. Simultaneous assertion of WE and DACK low activates the HDATA bus, even if the DMA channels are disabled. Read Enable Used with the Host Interface. Write Enable When Fly-By DMA Is Enabled. Simultaneous assertion of RD and DACK low activates the HDATA bus, even if the DMA channels are disabled. ADV212 121-Ball Package 144-Ball Package Pin No. 85 Location H8 Pin No. 83 Location G11 Mnemonic ACK Pins Used 1 Type O 76 G10 82 G10 IRQ 1 O 63 F8 72 F12 DREQ0 1 O 64 F9 71 F11 FSRQ0 O VALID O CFG1 I DACK0 1 I HOLD I FCS0 I Rev. B | Page 21 of 44 Description Acknowledge. Used for direct register accesses. This signal indicates that the last register access was successful. Due to synchronization issues, control and status register accesses may incur an additional delay; therefore, the host software should wait for acknowledgment from the ADV212 before attempting another register access. Accesses to the FIFOs (external DMA modes), on the other hand, are guaranteed to occur immediately, provided that space is available; therefore, the host software does not need to wait for ACK before attempting another register access, provided that the timing constraints are observed. If ACK is shared with more than one device, ACK should be connected to a pull-up resistor (10 k Ω) and the PLL_HI register, Bit 4, must be set to 1. Interrupt. This pin indicates that the ADV212 requires the attention of the host processor. This pin can be programmed to indicate the status of the internal interrupt conditions within the ADV212. The interrupt sources are enabled via the bits in the EIRQIE register. Data Request for External DMA Interface. Indicates that the ADV212 is ready to send/receive data to/from the FIFO assigned to DMA Channel 0. FIFO Service Request. Used in DCS-DMA mode. Service request from the FIFO assigned to Channel 0 (asynchronous mode). Valid Indication for JDATA Input/Output Stream. Polarity of this pin is programmable in the EDMOD0 register. VALID is always an output. Boot Mode Configuration. This pin is read on reset to determine the boot configuration of the on-board processor. The pin should be tied to IOVDD through a 10 kΩ resistor. Data Acknowledge for External DMA Interface. Signal from the host CPU, which indicates that the data transfer request (DREQ0) has been acknowledged and that the data transfer can proceed. This pin must be held high at all times if the DMA interface is not used, even if the DMA channels are disabled. External Hold Indication for JDATA Input/Output Stream. Polarity is programmable in the EDMOD0 register. This pin is always an input. FIFO Chip Select. Used in DCS-DMA mode. Chip select for the FIFO assigned to Channel 0 (asynchronous mode). ADV212 121-Ball Package Pin No. 65 90 to 92, 78 J2 to J4, H1 111, 97 to 99 K3, J1 to J3 HDATA[31:28] 4 I/O 79 to 81, 70 H2 to H4, G4 100, 85 to 87 J4, H1 to H3 JDATA[7:4] HDATA[27:24] 4 I/O I/O JDATA Bus (JDATA Mode). Host Expansion Bus. 69, 68, 59, 58 57, 46 to 48 G3, G2, F4, F3 F2, E2, E3, E4 88, 73 to 75 H4, G1 to G3 JDATA[3:0] HDATA[23:20] 4 I/O I/O JDATA Bus (JDATA Mode). Host Expansion Bus. 76, 61 to 63 G4, F1 to F3 HDATA[19:16] 4 I/O Host Expansion Bus. I/O Video Data. Used only for raw pixel video mode. Unused pins should be pulled down via a 10 kΩ resistor. Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. Serial Communication. This pin must be used in multiple chip mode to align the outputs of two or more ADV212s. For details, see the Applications Information section. When not used, this pin should be tied low via a 10 kΩ resistor. LCODE Output in Encode Mode. When LCODE is enabled, the output on this pin indicates on a high transition that the last data-word for a field has been read from the FIFO. For an 8-bit interface, such as JDATA, LCODE is asserted for four consecutive bytes and is enabled by default. G9 Pin No. 70 69 Location F10 F9 Mnemonic DREQ1 Pins Used 1 Description Data Request for External DMA Interface. Indicates that the ADV212 is ready to send/receive data to/from the FIFO assigned to DMA Channel 1. FIFO Service Request. Used in DCS-DMA mode. Service request from the FIFO assigned to Channel 1 (asynchronous mode). Boot Mode Configuration. This pin is read on reset to determine the boot configuration of the on-board processor. The pin should be tied to DGND through a 10 kΩ resistor. Data Acknowledge for External DMA Interface. Signal from the host CPU, which indicates that the data transfer request (DREQ1) has been acknowledged and data transfer can proceed. This pin must be held high at all times unless a DMA or JDATA access is occurring. This pin must be held high at all times if the DMA interface is not used, even if the DMA channels are disabled. FIFO Chip Select. Used in DCS-DMA mode. Chip select for the FIFO assigned to Channel 1 (asynchronous mode). Host Expansion Bus. 75 Location F10 144-Ball Package Type O FSRQ1 O CFG2 I DACK1 1 I I FCS1 VDATA[15:12] 112 L2 134 M2 SCOMM7 8 113 L3 135 M3 SCOMM6 I/O 114 L4 136 M4 SCOMM5 I/O 100 K1 121 L1 SCOMM4 O Rev. B | Page 22 of 44 I/O ADV212 121-Ball Package 144-Ball Package Pins Used Pin No. 101 Location K2 Pin No. 122 Location L2 Mnemonic SCOMM3 115 L5 123 L3 SCOMM2 O 103 K4 109 K1 SCOMM1 I 102 K3 110 K2 SCOMM0 O 53 E9 60 E12 VCLK 1 I 44, 43, 29, 31, 32, 18 to 20, 22, 21, 7, 10 46 to 48, 34 to 36, 22 to 24, 9 to 11 D10 to D12, C10 to C12, B10 to B12, A9 to A11 VDATA[11:0] 12 I/O 41 D11, D10, C7, C9, C10, B7, B8, B9, B11, B10, A7, A10 D8 58 E10 VSYNC VFRM 1 I/O 42 D9 59 E11 1 54 E10 57 E9 94 J6 120 K12 HSYNC VRDY FIELD VSTRB TCK 1 I/O O I/O I I 108 K9 119 K11 TRS 1 I 98 J10 118 K10 TMS 1 I 116 L6 141 M9 TDI 1 I 109 K10 130 L10 TDO 1 O 3, 8, 40, 84, 120 A3, A8, D7, H7, L10 18, 19, 30, 31, 42, 43, 102, 103, 114, 115, 126, 127, 142 B6, B7, C6, C7, D6, D7, J6, J7, K6, K7, L6, L7, M10 VDD 5/13 V 1 Rev. B | Page 23 of 44 Type I Description Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. Serial Communication. This pin should be tied low via a10 kΩ resistor. Video Data Clock. This pin must be supplied if video data is input/output on the VDATA bus. Video Data. Unused pins should be pulled down via a 10 kΩ resistor. Vertical Sync for Video Mode. Raw Pixel Mode Framing Signal. When this pin is asserted high, it indicates the first sample of a tile. Horizontal Sync for Video Mode. Raw Pixel Mode Ready Signal. Field Sync for Video Mode. Raw Pixel Mode Transfer Strobe. JTAG Clock. If not used, this pin should be connected to ground via a pull-down resistor. JTAG Reset. If the JTAG is used, this pin must be toggled low to high. If JTAG is not used, this pin must be held low. JTAG Mode Select. If JTAG is used, connect a 10 kΩ pull-up resistor to this pin. If not used, this pin should be connected to ground via a pull-down resistor. JTAG Serial Data Input. If JTAG is used, connect a 10 kΩ pull-up resistor to this pin. If JTAG is not used, this pin should be connected to ground via a pull-down resistor. JTAG Serial Data Output. If this pin is not used, do not connect it. Positive Supply for Core. ADV212 121-Ball Package Pin No. 1, 4, 9,11, 23, 33, 39, 45, 49 to 51, 55, 56, 60 to 62, 66, 67, 71 to 73, 77, 83, 89, 99, 110, 111, 118, 121 Location A1, A4, A9, A11, C1, C11, D6, E1, E5 to E7, E11, F1, F5 to F7, F11, G1, G5 to G7, G11, H6, J1, J11, K11, L1, L8, L11 17, 28, 30, 38, 52, 74, 82, 93, 104 to 106 B6, C6, C8, D5, E8, G8, H5, J5, K5 to K7 144-Ball Package Pin No. 1, 5 to 8, 12, 17, 20, 29, 32, 41, 44, 52 to 56, 65 to 68, 77 to 81, 89 to 93, 101, 104, 105, 113, 116, 125, 128, 133, 137 to 140, 143, 144 16, 21, 28, 33, 40, 45, 112, 117, 124, 129 Location A1, A5 to A8, A12, B5, B8, C5, C8, D5, D8, E4 to E8, F5 to F8, G5 to G9, H5 to H9, J5, J8, J9, K5, K8, L5, L8, M1, M5 to M8, M11, M12 Mnemonic DGND Pins Used 29/45 Type GND Description Ground. B4, B9, C4, C9, D4, D9, K4, K9, L4, L9 IOVDD 11/10 V Positive Supply for Input/Output. In fly-by mode DMA, the functions of the RD and WE signals (for DMA only) are reversed. This allows a host to move data between an external device and the ADV212 with the use of a single strobe. 2 In encode mode with fly-by DMA, the host can use the RDFB signal (WE pin) to simultaneously read from the ADV212 and write to an external device such as memory. 3 In decode mode with fly-by DMA, the host can use the WEFB signal (RD pin) to simultaneously read from the external device and write to the ADV212. 1 Rev. B | Page 24 of 44 ADV212 THEORY OF OPERATION The input video or pixel data is passed to the ADV212 pixel interface, and samples are deinterleaved and passed to the wavelet engine, which decomposes each tile or frame into subbands using the 5/3 or 9/7 filters. The resultant wavelet coefficients are then written to the internal memory. The entropy CODECs code the image data so that it conforms to the JPEG2000 standard. An internal DMA provides high bandwidth memory-to-memory transfers, as well as high performance transfers between functional blocks and memory. ENTROPY CODECS WAVELET ENGINE EMBEDDED PROCESSOR SYSTEM The ADV212 provides a dedicated wavelet transform processor based on the Analog Devices, Inc., proven and patented SURF® technology. This processor can perform up to six wavelet decomposition levels on a tile. In encode mode, the wavelet transform processor takes in uncompressed samples, performs the wavelet transform and quantization, and writes the wavelet coefficients in all frequency subbands to the internal memory. Each of these subbands is further broken down into code blocks. The code-block dimensions can be user defined and are used by the wavelet transform processor to organize the wavelet coefficients into code blocks when writing to the internal memory. Each completed code block is then entropy coded by one of the entropy CODECs. In decode mode, wavelet coefficients are read from internal memory and recomposed into uncompressed samples. The entropy CODEC block performs context modeling and arithmetic coding on a code block of the wavelet coefficients. Additionally, this block also performs the distortion metric calculations during compression that are required for optimal rate and distortion performance. Because the entropy coding process is the most computationally intensive operation in the JPEG2000 compression process, three dedicated hardware entropy CODECs are provided on the ADV212. The ADV212 incorporates an embedded 32-bit RISC processor. This processor is used for configuration, control, and management of the dedicated hardware functions, as well as for parsing and generating the JPEG2000 code stream. The processor system includes memory for both the program and data memory, the interrupt controller, the standard bus interfaces, and other hardware functions such as timers and counters. MEMORY SYSTEM The main function of the memory system is to manage wavelet coefficient data, interim code-block attribute data, and temporary workspace for creating, parsing, and storing the JPEG2000 code stream. The memory system can also be used for the program and data memory for the embedded processor. INTERNAL DMA ENGINE The internal DMA engine provides high bandwidth memoryto-memory transfers, as well as high performance transfers between memory and functional blocks. This function is critical for high speed generation and parsing of the code stream. Rev. B | Page 25 of 44 ADV212 ADV212 INTERFACES There are several possible ways to interface to the ADV212 using the VDATA bus and the HDATA bus or the HDATA bus alone. The control and data channel bus widths can be specified independently, which allows the ADV212 to support applications that require control and data buses of different widths. VIDEO INTERFACE (VDATA BUS) The host interface is used for configuration, control, and status functions, as well as for transferring compressed data streams. It can be used for uncompressed data transfers in certain modes. The host interface can be shared by as many as three concurrent data streams in addition to control and status communications. The data streams are The video interface can be used in applications in which uncompressed pixel data is on a separate bus from compressed data. For example, it is possible to use the VDATA bus to input uncompressed video while using the HDATA bus to output the compressed data. This interface is ideal for applications requiring very high throughput, such as live video capture. Optionally, the ADV212 interlaces ITU-R BT.656 resolution video on the fly prior to wavelet processing, which yields significantly better compression performance for temporally coherent frame-based video sources. Additionally, high definition digital video such as SMPTE 274M (1080i) is supported using two or more ADV212 devices. The video interface can support video data or still image data input/output in 8-/10-/12-bit formats, in YCbCr format, or in single input mode. YCbCr data must be in 4:2:2 format. When operating in raw pixel mode, only one component can be processed by a single ADV212. Video data can be input/output in several different modes on the VDATA bus, as described in Table 17. In all these modes, the pixel clock must be input on the VCLK pin. Table 17. Video Input/Output Modes Mode EAV/SAV HVF Raw Video Description Accepts video with embedded EAV/SAV codes, where the YCbCr data is interleaved onto a single bus. Accepts video data accompanied by separate H, V, and F signals, where YCbCr data is interleaved onto a single bus. Used for still picture data and nonstandard video. VFRM, VSTRB, and VRDY are used to program the dimensions of the image. When operating in raw pixel mode, only one component can be processed by a single ADV212. HOST INTERFACE (HDATA BUS) The ADV212 can connect directly to a wide variety of host processors and ASICs using an asynchronous SRAM-style interface, DMA accesses, or streaming mode (JDATA) interface. The ADV212 supports 16- and 32-bit buses for control and 8-/16-/32-bit buses for data transfer. • • • Uncompressed tile data (for example, still image data) Fully encoded JPEG2000 code stream (or unpackaged code blocks) Code-block attributes The ADV212 uses big endian byte alignment for 16- and 32-bit transfers. All data is left-justified (MSB). Pixel Input on the Host Interface Pixel input on the host interface supports 8-/10-/12-/14-/16-bit raw pixel data formats. It can be used for pixel (still image) input/output or compressed video output. Because there are no timing codes or sync signals associated with the input data on the host interface, dimension registers and internal counters are used and must be programmed to indicate the start and end of the frame. Host Bus Configuration For maximum flexibility, the host interface provides several configurations to meet particular system requirements. The default bus mode uses the same pins to transfer control, status, and data to and from the ADV212. In this mode, the ADV212 can support 16- and 32-bit control transfers and 8-/16-/32-bit data transfers. The size of these buses can be selected independently, allowing, for example, a 16-bit microcontroller to configure and control the ADV212 while still providing 32-bit data transfers to an ASIC or external memory system. DIRECT AND INDIRECT REGISTERS To minimize pin count and cost, the number of address pins is limited to four, which yields a total direct address space of 16 locations. These locations are most commonly used by the external controller and are, therefore, accessible directly. All other registers in the ADV212 can be accessed indirectly through the IADDR and IDATA registers. Rev. B | Page 26 of 44 ADV212 CONTROL ACCESS REGISTERS With the exception of the indirect address and data registers (IADDR and IDATA), all control/status registers in the ADV212 are 16 bits wide and are half-word (16-bit) addressable only. When 32-bit host mode is enabled, the upper 16 bits of the HDATA bus are ignored on writes and return all zeros on reads of 16-bit registers. PIN CONFIGURATION AND BUS SIZES/MODES The ADV212 provides a wide variety of control and data configurations, which allows it to be used in many applications with little or no glue logic. The modes described in this section are configured using the BUSMODE register. In this section, host refers to normal addressed accesses (CS/RD/WE/ADDR) and data refers to external DMA accesses (DREQ/DACK). 32-Bit Host/32-Bit Data In this mode, the HDATA[31:0] pins provide full 32-bit wide data access to the pixel channel, code channel, and ATTR channel FIFOs. 16-Bit Host/32-Bit Data This mode allows a 16-bit host to configure and communicate with the ADV212 while allowing 32-bit accesses to the pixel, xode, and ATTR FIFOs using the external DMA capability. All addressed host accesses are 16 bits and, therefore, use only the HDATA[15:0] pins. The HDATA[31:16] pins provide the additional 16 bits necessary to support the 32-bit external DMA transfers to and from the FIFOs only. 16-Bit Host/16-Bit Data This mode uses 16-bit transfers if used for host or external DMA data transfers. has been provided to allow 16-bit hosts to access these registers and memory locations using the stage register, which is accessed as a 16-bit register using HDATA[15:0]. Before writing to the desired register, the stage register must be written with the upper (most significant) half-word. When the host subsequently writes the lower half-word to the desired control register, HDATA is combined with the previously staged value to create the required 32-bit value that is written. When a register is read, the upper (most significant) half-word is returned immediately on HDATA, and the lower half-word can be retrieved by reading the stage register on a subsequent access. Note that the stage register does not apply to the three data channels (pixel, code, and ATTR). These channels are always accessed at the specified data width and do not require the use of the stage register. JDATA MODE JDATA mode is typically used only when the dedicated video interface (VDATA) is also enabled. This mode allows code stream data (compressed data compliant with JPEG2000) to be input or output on a single dedicated 8-bit bus (JDATA[7:0]). The bus is always an output during compression operations and an input during decompression. A 2-pin handshake is used to transfer data over this synchronous interface. VALID is used to indicate that the ADV212 is ready to provide or accept data and is always an output. HOLD is always an input and is asserted by the host if it cannot accept/ provide data. For example, JDATA mode allows real-time applications, in which pixel data is input over the VDATA bus while the compressed data stream is output over the JDATA bus. EXTERNAL DMA ENGINE 16-Bit Host/8-Bit Data (JDATA Bus Mode) This mode provides separate data input/output and host control interface pins. Host control accesses are 16 bits and use HDATA[15:0], whereas the dedicated data bus uses JDATA[7:0]. JDATA uses a valid/hold synchronous transfer protocol. The direction of the JDATA bus is determined by the mode of the ADV212. If the ADV212 is encoding (compression), JDATA[7:0] is an output. If the ADV212 is decoding (decompression), JDATA[7:0] is an input. Host control accesses remain asynchronous. See also the JDATA Mode section. STAGE REGISTER The external DMA interface is provided to enable high bandwidth data input/output between an external DMA controller and the ADV212 data FIFOs. Two independent DMA channels can each be assigned to any one of the three data stream FIFOs (pixel, code, and ATTR). The controller supports asynchronous DMA using a datarequest/data-acknowledge (DREQ/DACK) protocol in either single or burst access mode. Additional functionality is provided for single address compatibility (fly-by) mode and dedicated chip select (DCS) mode. Because the ADV212 contains both 16-bit and 32-bit registers and its internal memory is mapped as 32-bit data, a mechanism Rev. B | Page 27 of 44 ADV212 INTERNAL REGISTERS This section describes the internal registers of the ADV212. DIRECT REGISTERS The ADV212 has 16 direct registers, as listed in Table 18. The direct registers are accessed over the ADDR[3:0], HDATA[31:0], CS, RD, WE, and ACK pins. The host must first initialize the direct registers before any application-specific operation can be implemented. Table 18. Direct Registers Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Name Pixel Code ATTR Reserved CMDSTA EIRQIE EIRQFLG SWFLAG BUSMODE MMODE Stage IADDR IDATA Boot PLL_HI PLL_LO Description Pixel FIFO access register Compressed code stream access register Attribute FIFO access register Reserved Command stack External interrupt enabled External interrupt flags Software flag register Bus mode configuration register Miscellaneous mode register Staging register Indirect address register Indirect data register Boot mode register PLL control register, high byte PLL control register, low byte Rev. B | Page 28 of 44 ADV212 INDIRECT REGISTERS In certain modes, such as custom-specific input format or HIPI mode, indirect registers must be accessed by the user through the IADDR and IDATA registers. The indirect register address space starts at Internal Address 0xFFFF0000. Both 32-bit and 16-bit hosts can access the indirect registers: 32-bit hosts use the IADDR and IDATA registers, and 16-bit hosts use the IADDR, IDATA, and stage registers. Table 19. Indirect Registers Address 0xFFFF0400 0xFFFF0404 0xFFFF0408 0xFFFF040C 0xFFFF0410 0xFFFF0414 0xFFFF0418 0xFFFF041C 0xFFFF0420 0xFFFF0424 0xFFFF0428 0xFFFF042C 0xFFFF0430 0xFFFF0440 0xFFFF0444 0xFFFF0448 0xFFFF044C 0xFFFF1408 0xFFFF140C 0xFFFF1410 0xFFFF1414 0xFFFF1418 0xFFFF141C 0xFFFF1420 0xFFFF1424 to 0xFFFF14FC Name PMODE1 COMP_CNT_STATUS LINE_CNT_STATUS XTOT YTOT F0_START F1_START V0_START V1_START V0_END V1_END PIXEL_START PIXEL_END MS_CNT_DEL Reserved PMODE2 VMODE EDMOD0 EDMOD1 FFTHRP Reserved Reserved FFTHRC FFTHRA Reserved Rev. B | Page 29 of 44 Description Pixel/video format Horizontal count Vertical count Total samples per line Total lines per frame Start line of Field 0 [F0] Start line of Field 1 [F1] Start of active video Field 0 [F0] Start of active video Field 1 [F1] End of active video Field 0 [F0] End of active video Field 1 [F1] Horizontal start of active video Horizontal end of active video Master/slave delay Reserved Pixel Mode 2 Video mode External DMA Mode Register 0 External DMA Mode Register 1 FIFO threshold for pixel FIFO Reserved Reserved FIFO threshold for code FIFO FIFO threshold for ATTR FIFO Reserved ADV212 PLL REGISTERS • The ADV212 uses the PLL_HI and PLL_LO direct registers to configure the PLL. Any time the PLL_LO register is modified, the host must wait at least 20 µs before reading from or writing to another register. If this delay is not implemented, erratic behavior may result. • • MCLK is the input clock to the ADV212 PLL and is used to generate the internal JCLK (JPEG2000 processor clock) and HCLK (embedded CPU clock). To achieve the lowest power consumption, an MCLK frequency of 27 MHz is recommended for a standard definition CCIR 656 input. The PLL circuit is recommended to have a multiplier of 3. This sets JCLK and HCLK to 81 MHz. The PLL can be programmed to have any possible final multiplier value as long as • • • • JCLK > 50 MHz and < 150 MHz (144-pin version). JCLK > 50 MHz and < 115 MHz (121-pin version). HCLK < 81 MHz (121-pin version) or HCLK < 108 MHz (144-pin version). JCLK ≥ 2 × VCLK for single-component input. JCLK ≥ 2 × VCLK for YCbCr [4:2:2] input. In JDATA mode (JDATA), JCLK must be 4 × MCLK or higher. The maximum burst frequency for external DMA modes is ≤ 0.36 JCLK. BYPASS IPD MCLK ÷2 PHASE DETECT VCO LPF JCLK ÷2 ÷2 ÷2 ÷PLLMULT HCLK ÷2 HCLKD LFB Figure 32. PLL Architecture and Control Functions Table 20. Recommended PLL Register Settings IPD 0 0 0 0 1 1 1 1 LFB 0 0 1 1 0 0 1 1 PLLMULT N N N N N N N N HCLKD 0 1 0 1 0 1 0 1 HCLK N × MCLK N × MCLK/2 2 × N × MCLK N × MCLK N × MCLK/2 N × MCLK/4 N × MCLK N × MCLK/2 JCLK N × MCLK N × MCLK 2 × N × MCLK 2 × N × MCLK N × MCLK/2 N × MCLK/2 N × MCLK N × MCLK Table 21. Recommended Values for PLL_HI and PLL_LO Registers Video Standard SMPTE 125M or ITU-R BT.656 (NTSC or PAL) SMPTE 293M (525p) ITU-R BT.1358 (625p) SMPTE 274M (1080i) CLKIN Frequency on MCLK 27 MHz 27 MHz 27 MHz 74.25 MHz Rev. B | Page 30 of 44 PLL_HI 0x0008 0x0008 0x0008 0x0008 PLL_LO 0x0004 0x0004 0x0004 0x0084 06389-009 • • • For MCLK frequencies greater than 50 MHz, the input clock divider must be enabled; that is, IPD must be set to 1. IPD cannot be enabled for MCLK frequencies below 20 MHz. Deinterlace modes require JCLK ≥ 4 × MCLK. It is not recommended to use an LLC output from a video decoder as a clock source for MCLK. ADV212 HARDWARE BOOT MODES AND POWER CONSIDERATIONS There is no special power sequencing requirement for VDD and IOVDD. The boot mode can be configured via hardware using the CFG pins or via software. The first boot mode after power-up is set by the CFG pins and should always be as described in the pin listing. CFG1 is tied to IOVDD through a 10 k resistor and CFG2 is tied to GND through a 10 k resistor. It is strongly recommended that the user place a small decoupling cap close to every power pin and at least one bulk cap on each supply. Rev. B | Page 31 of 44 ADV212 VIDEO INPUT FORMATS The ADV212 supports a wide variety of formats for uncompressed video and still image data. The actual interface and bus modes selected for transferring uncompressed data dictates the allowed size of the input data and the number of samples transferred with each access. The host interface can support 8-/10-/12-/14-/16-bit data formats. The video interface can support video data or still image data input/output. Supported formats are 8-/10-/12-bit YCbCr formats or single component format. All formats can support less precision than provided by specifying the actual data width/precision in the PMODE register. The maximum allowable data input rate is limited by using irreversible or reversible compression modes and the data width (or precision) of the input samples. See Table 22 and Table 24 to determine the maximum data input rate. Table 22. Maximum Pixel Data Input Rates (144-Ball Package) Interface HDATA VDATA 1 2 3 Compression Mode Irreversible Irreversible Irreversible Irreversible Reversible Reversible Reversible Reversible Irreversible Irreversible Irreversible Reversible Reversible Reversible Input Format 8-bit data 10-bit data 12-bit data 16-bit data 8-bit data 10-bit data 12-bit data 14-bit data 8-bit data 10-bit data 12-bit data 8-bit data 10-bit data 12-bit data Input Rate Limit Active Resolution (MSPS)1 45 45 45 45 40 32 27 23 65 65 65 40 32 27 Approximate Minimum Output Rate, Compressed Data2 (Mbps) 130 130 130 130 130 130 130 130 130 130 130 130 130 130 Approximate Maximum Output Rate, Compressed Data3 (Mbps) 200 200 200 200 200 200 200 200 200 200 200 200 200 200 Input rate limits for HDATA may be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings. Minimum guaranteed sustained output rate or minimum sustainable compression rate (input rate/minimum peak output rate). Maximum peak output rate; an output rate above this value is not possible. Table 23. Maximum Pixel Data Input Rates (121-Ball Package) Interface HDATA VDATA Compression Mode Irreversible Irreversible Irreversible Irreversible Reversible Reversible Reversible Reversible Irreversible Irreversible Irreversible Reversible Reversible Reversible Input Format 8-bit data 10-bit data 12-bit data 16-bit data 8-bit data 10-bit data 12-bit data 14-bit data 8-bit data 10-bit data 12-bit data 8-bit data 10-bit data 12-bit data Input Rate Limit Active Resolution (MSPS)1 34 34 34 34 30 24 20 17 48 48 48 30 24 20 Approx Min Output Rate, Compressed Data2 (Mbps) 98 98 98 98 98 98 98 98 98 98 98 98 98 98 Approx Max Output Rate, Compressed Data3 (Mbps) 150 150 150 150 150 150 150 150 150 150 150 150 150 150 Input rate limits for HDATA may be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings. Minimum guaranteed sustained output rate or minimum sustainable compression rate (input rate/minimum peak output rate). 3 Maximum peak output rate; an output rate above this value is not possible. 1 2 Rev. B | Page 32 of 44 ADV212 Table 24. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses Compression Mode 9/7i 9/7i 9/7i 5/3i 5/3i 5/3i 5/3r 5/3r 5/3r Input Format Single-component Two-component Three-component Single-component Two-component Three-component Single-component Two-component Three-component Tile/Precinct Maximum Width 2048 1024 each 1024 (Y) 4096 2048 (each) 2048 (Y) 4096 2048 1024 Rev. B | Page 33 of 44 ADV212 APPLICATIONS INFORMATION In decode mode, a master/slave configuration (as shown in Figure 34) or a slave/slave configuration can be used to synchronize the outputs of the two ADV212s. This section describes typical video applications for the ADV212 JPEG2000 video processor. ENCODE—MULTICHIP MODE Applications that have two separate VDATA outputs sent to an FPGA or buffer before they are sent to an encoder do not require synchronization at the ADV212 outputs. Due to the data input rate limitation (see Table 22), an 1080i application requires at least two ADV212s to encode or decode full-resolution 1080i video. In encode mode, the ADV212 accepts Y and CbCr data on separate buses. An encode example is shown in Figure 33. 32-BIT HOST CPU DATA[31:0] ADDR[3:0] CS ADV212_1_SLAVE 10-BIT SD/HD VIDEO DECODER ADDR[3:0] CS RD ACK RD ACK WR WE IRQ IRQ DREQ DREQ DACK DACK GPIO 74.25MHz OSC HDATA[31:0] LLC VCLK 1080i VIDEO IN MCLK Y VDATA[11:2] SCOMM[5] FIELD VSYNC HSYNC Y[9:0] CbCr C[9:0] ADV212_2_SLAVE HDATA[31:0] ADDR[3:0] CS RD WR WE ACK ACK IRQ IRQ DREQ DACK DREQ HSYNC VSYNC FIELD VDATA[11:2] CbCr DACK SCOMM[5] Figure 33. Encode—Multichip Application Rev. B | Page 34 of 44 06389-002 CS RD VCLK MCLK ADV212 DECODE—MULTICHIP MASTER/SLAVE In a slave/slave configuration, the common HVF for both ADV212s is generated by an external house sync, and each SCOMM5 is connected to the same GPIO output on the host. In a master/slave configuration, it is expected that the master HVF outputs are connected to the slave HVF inputs and that each SCOMM5 pin is connected to the same GPIO on the host. 32-BIT HOST CPU DATA[31:0] ADDR[3:0] 74.25MHz OSC ADV212_1_MASTER 10-BIT SD/HD VIDEO ENCODER HDATA[31:0] ADDR[3:0] CS CS RD RD WR WE ACK ACK IRQ IRQ DREQ DREQ DACK DACK GPIO SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be unmasked on both devices to enable multichip mode. CLKIN VCLK 1080i VIDEO OUT MCLK VDATA[11:2] Y Y FIELD VSYNC HSYNC SCOMM[5] Y[9:0] CbCr C[9:0] ADV212_2_SLAVE HDATA[31:0] ADDR[3:0] CS RD WR WE ACK ACK IRQ IRQ DREQ DREQ DACK DACK HSYNC VSYNC FIELD VDATA[11:2] CbCr 06389-003 CS RD VCLK MCLK SCOMM[5] Figure 34. Decode—Multichip Master/Slave Application Rev. B | Page 35 of 44 ADV212 DIGITAL STILL CAMERA/CAMCORDER Figure 35 is a typical configuration for a digital camera or camcorder. ADV212 D[9:0] SDATA SCK SL 10 DATA INPUTS[9:0] MCLK VCLK SERIAL DATA VFRM VRDY VSTRB SERIAL CLK SERIAL EN PIXEL OUT[9:0] HDATA[15:0] ADDR[3:0] CS RD WE VDATA[15:6] ACK IRQ 16-BIT HOST CPU DATA[15:0] ADDR[3:0] CS RD WE ACK IRQ Figure 35. Digital Still Camera/Camcorder Encode Application for 10-Bit Pixel Data Using Raw Pixel Mode Rev. B | Page 36 of 44 06389-004 FPGA AD9843A ADV212 ENCODE/DECODE SDTV VIDEO APPLICATION Figure 36 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode. ENCODE MODE ADV212 10-BIT VIDEO DECODER VIDEO IN VDATA[11:2] 32-BIT HOST CPU DATA[31:0] INTR ADDR[3:0] CS RD WE ACK DECODE MODE P[19:10] VCLK HDATA[31:0] IRQ ADDR[3:0] CS RD WE ACK MCLK LLC1 27MHz OSC ADV212 10-BIT VIDEO ENCODER VIDEO OUT VDATA[11:2] VCLK 32-BIT HOST CPU CLKIN MCLK HDATA[31:0] IRQ ADDR[3:0] CS RD WE ACK 27MHz OSC Figure 36. Encode/Decode—SDTV Video Application Rev. B | Page 37 of 44 06389-005 DATA[31:0] INTR ADDR[3:0] CS RD WE ACK P[9:0] ADV212 32-BIT HOST APPLICATION Figure 37 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode. FPGA ADV7189 ADV212 10-BIT VIDEO DECODER DREQ0 DREQ0 DACK0 DACK0 VDATA[11:2] DATA[31:0] HDATA[31:0] 32-BIT HOST CPU LLC1 VCLK MCLK VIDEO IN P[19:10] 27MHz OSC DATA[31:0] FPGA IRQ ADDR[3:0] CS RD WE ACK ENCODE MODE 10-BIT VIDEO ENCODER ADV212 VIDEO OUT DREQ0 DREQ0 DACK0 DACK0 VDATA[11:2] DATA[31:0] HDATA[31:0] 31-BIT HOST CPU CLKIN MCLK 27MHz OSC DATA[31:0] IRQ ADDR[3:0] CS RD WE ACK P[9:0] VCLK IRQ ADDR[3:0] CS RD WE ACK DECODE MODE Figure 37. Encode/Decode 32-Bit Host Application Rev. B | Page 38 of 44 06389-006 IRQ ADDR[3:0] CS RD WE ACK ADV212 HIPI (HOST INTERFACE—PIXEL INTERFACE) Figure 38 is a typical configuration using HIPI mode. ADV212 Y0/G0<MSB> Y0/G0<6> Y0/G0<5> Y0/G0<4> Y0/G0<3> Y0/G0<2> Y0/G0<1> Y0/G0<0> Cb0/G1<MSB> Cb0/G1<6> Cb0/G1<5> Cb0/G1<4> Cb0/G1<3> Cb0/G1<2> Cb0/G1<1> Cb0/G1<0> Y1/G2<MSB> Y1/G2<6> Y1/G2<5> Y1/G2<4> Y1/G2<3> Y1/G2<2> Y1/G2<1> Y1/G2<0> Cr0/G3<MSB> Cr0/G3<6> Cr0/G3<5> Cr0/G3<4> Cr0/G3<3> Cr0/G3<2> Cr0/G3<1> Cr0/G3<0> 32-BIT HOST HDATA<31> HDATA<30> HDATA<29> HDATA<28> HDATA<27> HDATA<26> HDATA<25> HDATA<24> HDATA<23> HDATA<22> HDATA<21> HDATA<20> HDATA<19> HDATA<18> HDATA<17> HDATA<16> HDATA<15> HDATA<14> HDATA<13> HDATA<12> HDATA<11> HDATA<10> HDATA<9> HDATA<8> HDATA<7> HDATA<6> HDATA<5> HDATA<4> HDATA<3> HDATA<2> HDATA<1> HDATA<0> DATA<31:0> CS CS RD RD WR WE ACK ACK IRQ DREQ0 DACK0 COMPRESSED DATA PATH DREQ DACK DREQ1 DACK1 RAW PIXEL DATA PATH 74.25MHz MCLK Figure 38. Host Interface—Pixel Interface Mode Rev. B | Page 39 of 44 06389-007 IRQ DREQ DACK ADV212 JDATA INTERFACE Figure 39 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR 656. ADV212 JDATA[7:0] VDATA[11:2] HOLD FIELD VALID VSYNC HSYNC 16-BIT HOST CPU DATA[15:0] IRQ ADDR[3:0] CS RD WE ACK YCrCb FIELD VS HS VCLK HDATA[15:0] IRQ ADDR[3:0] CS RD WE ACK MCLK VIDEO IN LLC1 27MHz OSC Figure 39. JDATA Application Rev. B | Page 40 of 44 ADV7189 P[19:10] 06389-008 FPGA ADV212 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 12.20 12.00 SQ 11.80 BALL A1 CORNER 11 10 9 8 7 6 5 4 3 2 1 A B C D 10.00 BSC SQ E F G H J K L 1.00 BSC BOTTOM VIEW TOP VIEW *1.85 1.71 1.40 DETAIL A *1.31 1.21 1.11 DETAIL A 0.50 NOM 0.30 MIN 0.70 0.60 0.50 BALL DIAMETER 0.20 COPLANARITY 082406-A SEATING PLANE *COMPLIANT WITH JEDEC STANDARDS MO-192-ABD-1 WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. Figure 40. 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-121-1) Dimensions shown in millimeters A1 CORNER INDEX AREA 13 .00 BSC SQ 12 11 10 9 8 7 6 5 4 3 2 A B C D E F G H J K L M BALL A1 INDICATOR TOP VIEW DETAIL A 11.00 BCS SQ 1.00 BSC *1.85 MAX 1 BOTTOM VIEW *1.32 1.21 1.11 DETAIL A 0.53 0.43 SEATING PLANE *COMPLIANT WITH JEDEC STANDARDS MO-192-AAD-1 WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. Figure 41. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-144-3) Dimensions shown in millimeters Rev. B | Page 41 of 44 COPLANARITY 0.20 MAX 021506-A 0.70 0.60 0.50 BALL DIAMETER ADV212 ORDERING GUIDE Model1 ADV212BBCZ-115 Temperature Range −40°C to +85°C Speed Grade 115 MHz ADV212BBCZRL-115 −40°C to +85°C 115 MHz ADV212BBCZ-150 −40°C to +85°C 150 MHz ADV212BBCZRL-150 −40°C to +85°C 150 MHz Operating Voltage 1.5 V Internal, 2.5 V or 3.3 V I/O 1.5 V Internal, 2.5 V or 3.3 V I/O 1.5 V Internal, 2.5 V or 3.3 V I/O 1.5 V Internal, 2.5 V or 3.3 V I/O Package Description 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Package Option BC-121-1 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-121-1 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-3 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-3 Z = RoHS Compliant Part. 1 Rev. B | Page 42 of 44 ADV212 NOTES Rev. B | Page 43 of 44 ADV212 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06389-0-4/10(B) Rev. B | Page 44 of 44