STMicroelectronics MM24256-AWDL5T 256 kbit serial i c bus eeprom with two chip enable line Datasheet

M24256-A
256 Kbit Serial I²C Bus EEPROM
With Two Chip Enable Lines
NOT FOR NEW DESIGN
This device is now designated as “Not for New Design”. Please use the M24256-B in all future designs (as described in application note AN1470).
2
■ Compatible with I C Extended Addressing
■
Two Wire I2C Serial Interface
Supports 400 kHz Protocol
■
Single Supply Voltage:
8
1
– 4.5V to 5.5V for M24256-A
PDIP8 (BN)
0.25 mm frame
– 2.5V to 5.5V for M24256-AW
■
2 Chip Enable Inputs: up to four memories can
be connected to the same I2C bus
■
Hardware Write Control
■
BYTE and PAGE WRITE (up to 64 Bytes)
■
RANDOM and SEQUENTIAL READ Modes
■
Self-Timed Programming Cycle
■
Automatic Address Incrementing
■
Enhanced ESD/Latch-Up Behavior
■
More than 100,000 Erase/Write Cycles
■
More than 40 Year Data Retention
DESCRIPTION
These I 2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32Kx8 bits, and operate down to 2.5 V
(for the M24256-AW).
The M24256-A is available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small Out-
TSSOP14 (DL)
169 mil width
SBGA
SBGA7 (EA)
140 x 90 mil
8
8
1
1
SO8 (MN)
150 mil width
SO8 (MW)
200 mil width
Figure 1. Logic Diagram
VCC
2
E0-E1
Table 1. Signal Names
E0, E1
Chip Enable
SCL
SDA
Serial Data
WC
SCL
Serial Clock
WC
Write Control
VCC
Supply Voltage
VSS
Ground
November 2001
This is information on a product still in production but not recommended for new designs.
SDA
M24256-A
VSS
AI02271C
1/20
M24256-A
Figure 2C. TSSOP Connections
Figure 2A. DIP Connections
M24256-A
M24256-A
E0
E1
NC
VSS
1
2
3
4
8
7
6
5
E0
E1
NC
NC
NC
NC
VSS
VCC
WC
SCL
SDA
AI02273C
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
WC
NC
NC
NC
SCL
SDA
AI02388C
Note: 1. NC = Not Connected
Note: 1. NC = Not Connected
Figure 2B. SO Connections
Figure 2D. SBGA Connections (top view)
M24256-A
S1
WC
M24256-A
E0
E1
NC
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
S0
VCC
SDA
AI02272C
SCL
VSS
AI03760
Note: 1. NC = Not Connected
Table 2. Absolute Maximum Ratings 1
Symbol
Value
Unit
Ambient Operating Temperature
–40 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
TLEAD
PDIP: 10 seconds
Lead Temperature during Soldering SO: 20 seconds (max) 2
TSSOP: 20 seconds (max) 2
260
235
235
°C
TA
Parameter
VIO
Input or Output range
–0.6 to 6.5
V
VCC
Supply Voltage
–0.3 to 6.5
V
Electrostatic Discharge Voltage (Human Body model) 3
4000
V
Electrostatic Discharge Voltage (Machine model) 4
200
V
VESD
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
4. EIAJ IC-121 (Condition C) (200 pF, 0 Ω)
2/20
M24256-A
line packages. The M24256-A is also available in
a chip-scale (SBGA) package.
These memory devices are compatible with the
I2C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and after a NoAck for READ.
Power On Reset: V CC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is
held active until the V CC voltage has reached the
POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when VCC drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid V CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from
the SCL line to V CC. (Figure 3 indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to VCC. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Chip Enable (E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the two least significant
bits (b2, b1) of the 7-bit device select code. These
inputs must be tied to VCC or VSS to establish the
device select code. When unconnected, the E1
and E0 inputs are internally read as VIL (see Table
7 and Table 8)
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=VIL) or disable (WC=V IH)
write instructions to the entire memory area. When
Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC
Maximum RP value (kΩ)
20
16
RL
12
RL
SDA
MASTER
8
fc = 100kHz
4
fc = 400kHz
CBUS
SCL
CBUS
0
10
100
1000
CBUS (pF)
AI01665
3/20
M24256-A
Figure 4. I2C Bus Protocol
SCL
SDA
SDA
Input
START
Condition
SCL
1
SDA
MSB
2
SDA
Change
STOP
Condition
3
7
8
9
ACK
START
Condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
Condition
AI00792B
unconnected, the WC input is internally read as
VIL, and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowledged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I2C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
4/20
device is always a slave device in all communication.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device continuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
M24256-A
Table 3. Device Select Code 1
Device Type Identifier
Device Select Code
Chip Enable
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
0
E1
E0
RW
Note: 1. The most significant bit, b7, is sent first.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9th clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transition, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is further subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (0, E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
Up to four memory devices can be connected on a
single I 2C bus. Each one is given a unique 2-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the memory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.
Table 4. Most Significant Byte
b15
b14
b13
b12
b11
b10
b9
b8
Note: 1. b15 is treated as Don’t Care on the M24256-A series.
Table 5. Least Significant Byte
b7
b6
b5
b4
b3
b2
b1
b0
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding memory gives an acknowledgment on the SDA bus during the 9th bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Table 4) is sent first, followed by the Least significant
Byte (Table 5). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as Don’t
Care bits on the M24256-A memory.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory re-
Table 6. Operating Modes
Mode
Current Address Read
RW bit
WC 1
Data Bytes
1
X
1
0
X
Random Address Read
Initial Sequence
START, Device Select, RW = 1
START, Device Select, RW = 0, Address
1
reSTART, Device Select, RW = 1
1
X
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
START, Device Select, RW = 0
Page Write
0
VIL
≤ 64
START, Device Select, RW = 0
Similar to Current or Random Address Read
Note: 1. X = VIH or VIL.
5/20
M24256-A
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
BYTE ADDR
ACK
BYTE ADDR
NO ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
BYTE ADDR
NO ACK
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
NO ACK
DATA IN N
STOP
PAGE WRITE
(cont'd)
NO ACK
AI01120C
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the accompanying data bytes will not be acknowledged,
as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, instead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
6/20
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b14-b6 for the M24256-A) are the same. If more
bytes are sent than will fit up to the end of the row,
a condition known as ‘roll-over’ occurs. Data starts
to become overwritten (in a way not formally specified in this data sheet).
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the contents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition immediately after the Ack bit (in the “10th bit” time
M24256-A
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
BYTE ADDR
ACK
BYTE ADDR
ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
BYTE ADDR
ACK
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
DATA IN N
STOP
PAGE WRITE
(cont'd)
ACK
AI01106B
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trigger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not respond to any requests.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory disconnects itself from the bus, and copies the data from
its internal latches to the memory cells. The maximum write time (tw) is shown in Table 9, but the
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
Read Operations
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the master sends another START condition, and repeats
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must
not acknowledge the byte output, and terminates
the transfer with a STOP condition.
7/20
M24256-A
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
Operation is
Addressing the
Memory
YES
Send Address
and Receive ACK
ReSTART
NO
STOP
YES
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
WRITE Operation
Continue the
Random READ Operation
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory acknowledges this, and outputs the byte addressed by the
internal address counter. The counter is then incremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, without acknowledging the byte output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
8/20
START
Condition
AI01847C
The output data comes from consecutive addresses, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
M24256-A
Figure 8. Read Mode Sequences
ACK
DATA OUT
STOP
START
DEV SEL
NO ACK
R/W
ACK
START
DEV SEL *
ACK
BYTE ADDR
ACK
DEV SEL *
ACK
NO ACK
DATA OUT N
R/W
ACK
ACK
BYTE ADDR
R/W
ACK
ACK
BYTE ADDR
ACK
DEV SEL *
START
START
DEV SEL *
DATA OUT
R/W
ACK
DATA OUT 1
NO ACK
STOP
START
DEV SEL
SEQUENTIAL
RANDOM
READ
BYTE ADDR
R/W
ACK
SEQUENTIAL
CURRENT
READ
ACK
START
RANDOM
ADDRESS
READ
STOP
CURRENT
ADDRESS
READ
ACK
DATA OUT 1
R/W
NO ACK
STOP
DATA OUT N
AI01105C
st
th
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
9/20
M24256-A
Table 7. DC Characteristics
(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)
Symbol
Parameter
ILI
Input Leakage Current
(SCL, SDA)
ILO
Output Leakage Current
ICC
Supply Current
-W series:
Test Condition
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
VCC=5V, fc=400kHz (rise/fall time < 30ns)
2
mA
VCC =2.5V, fc=400kHz (rise/fall time < 30ns)
1
mA
VIN = VSS or VCC , VCC = 5 V
10
µA
VIN = VSS or VCC , VCC = 2.5 V
2
µA
ICC1
Supply Current
(Stand-by)
VIL
Input Low Voltage (SCL, SDA)
–0.3
0.3VCC
V
VIH
Input High Voltage (SCL, SDA)
0.7VCC
VCC+1
V
VIL
Input Low Voltage
(E0, E1, WC)
–0.3
0.5
V
VIH
Input High Voltage
(E0, E1, WC)
0.7VCC
VCC+1
V
Output Low
Voltage
IOL = 3 mA, VCC = 5 V
0.4
V
VOL
IOL = 2.1 mA, VCC = 2.5 V
0.4
V
-W series:
-W series:
Table 8. Input Parameters 1 (TA = 25 °C, f = 400 kHz)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
CIN
Input Capacitance (SDA)
8
pF
CIN
Input Capacitance (other pins)
6
pF
ZL
Input Impedance (E1, E0, WC)
VIN ≤ 0.5 V
50
kΩ
ZH
Input Impedance (E1, E0, WC)
VIN ≥ 0.7VCC
500
kΩ
tNS
Pulse width ignored
(Input Filter on SCL and SDA)
Single glitch
Note: 1. Sampled only, not 100% tested.
10/20
100
ns
M24256-A
Table 9. AC Characteristics
M24256-A
Symbol
Alt.
Parameter
VCC=4.5 to 5.5 V
TA=–40 to 85°C
Min
Max
VCC=2.5 to 5.5 V
TA=–40 to 85°C
Min
Unit
Max
tCH1CH2
tR
Clock Rise Time
300
300
ns
tCL1CL2
tF
Clock Fall Time
300
300
ns
tDH1DH2 2
tR
SDA Rise Time
20
300
20
300
ns
tDL1DL2 2
tF
SDA Fall Time
20
300
20
300
ns
tCHDX 1
tSU:STA
Clock High to Input Transition
600
600
ns
tCHCL
tHIGH
Clock Pulse Width High
600
600
ns
tDLCL
tHD:STA
Input Low to Clock Low (START)
600
600
ns
tCLDX
tHD:DAT
Clock Low to Input Transition
0
0
µs
tCLCH
tLOW
Clock Pulse Width Low
1.3
1.3
µs
tDXCX
tSU:DAT
Input Transition to Clock Transition
100
100
ns
tCHDH
tSU:STO
Clock High to Input High (STOP)
600
600
ns
tDHDL
tBUF
Input High to Input Low (Bus Free)
1.3
1.3
µs
tCLQV 3
tAA
Clock Low to Data Out Valid
200
tCLQX
tDH
Data Out Hold Time After Clock Low
200
fC
fSCL
Clock Frequency
400
400
kHz
tW
tWR
Write Time
10
10
ms
900
200
900
200
ns
ns
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Table 10. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing
Reference Voltages
≤ 50 ns
Figure 9. AC Testing Input Output Waveforms
0.8VCC
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
11/20
M24256-A
Figure 10. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
START
Condition
SDA
Input
SDA tDXCX
Change
tCHDH tDHDL
START
STOP
Condition Condition
SCL
SDA In
tCHDH
tW
STOP
Condition
Write Cycle
tCHDX
START
Condition
SCL
tCLQV
SDA Out
tCLQX
Data Valid
AI00795C
12/20
M24256-A
Table 11. Ordering Information Scheme
Example:
M24256
–A
W
MN
6
T
Memory Capacity
256
256 Kbit (32K x 8)
Option
T
Tape and Reel Packing
Temperature Range
6
Operating Voltage
–40 °C to 85 °C
Package
blank 4.5 V to 5.5 V
BN
PDIP8 (0.25 mm frame)
W
MN
SO8 (150 mil width)
MW
SO8 (200 mil width)
DL
TSSOP14 (169 mil width)
EA
SBGA71
2.5 V to 5.5 V
Note: 1. SBGA7 package available only for the “M24256-A W EA 6 T”
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all 1s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
13/20
M24256-A
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
E
b2
A2
A1
b
A
L
c
e
eA
eB
D
8
E1
1
PDIP-B
Note: 1. Drawing is not to scale.
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame
mm
inches
Symb.
Typ.
Min.
A
Typ.
Min.
5.33
A1
Max.
0.210
0.38
0.015
A2
3.30
2.92
4.95
0.130
0.115
0.195
b
0.46
0.36
0.56
0.018
0.014
0.022
b2
1.52
1.14
1.78
0.060
0.045
0.070
c
0.25
0.20
0.36
0.010
0.008
0.014
D
9.27
9.02
10.16
0.365
0.355
0.400
E
7.87
7.62
8.26
0.310
0.300
0.325
E1
6.35
6.10
7.11
0.250
0.240
0.280
e
2.54
–
–
0.100
–
–
eA
7.62
–
–
0.300
–
–
eB
L
14/20
Max.
10.92
3.30
2.92
3.81
0.430
0.130
0.115
0.150
M24256-A
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
h x 45˚
A
C
B
CP
e
D
N
E
H
1
α
A1
L
SO-a
Note: Drawing is not to scale.
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
mm
inches
Symb.
Typ.
Min.
Max.
A
1.35
A1
Min.
Max.
1.75
0.053
0.069
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
CP
1.27
Typ.
0.050
8
0.10
0.004
15/20
M24256-A
SO8 wide – 8 lead Plastic Small Outline, 200 mils body width
A
A2
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-b
Note: Drawing is not to scale.
SO8 wide – 8 lead Plastic Small Outline, 200 mils body width
mm
inches
Symb.
Typ.
Min.
A
Typ.
Min.
2.03
A1
0.10
A2
0.25
0.35
0.45
–
–
D
5.15
E
Max.
0.080
0.004
1.78
B
0.010
0.070
0.014
0.018
–
–
5.35
0.203
0.211
5.20
5.40
0.205
0.213
–
–
–
–
H
7.70
8.10
0.303
0.319
L
0.50
0.80
0.020
0.031
α
0°
10°
0°
10°
N
8
C
e
CP
16/20
Max.
0.20
1.27
0.008
0.050
8
0.10
0.004
M24256-A
TSSOP14 - 14 lead Thin Shrink Small Outline
D
14
8
c
E1
1
E
7
α
A1
A
L
A2
L1
CP
b
e
TSSOP14-M
Note: 1. Drawing is not to scale.
TSSOP14 - 14 lead Thin Shrink Small Outline
mm
inches
Symbol
Typ.
Min.
A
Max.
Min.
1.200
A1
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ.
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
5.000
4.900
5.100
0.1969
0.1929
0.2008
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.500
0.750
0.0236
0.0197
0.0295
L1
1.000
0°
8°
α
0.0394
0°
8°
17/20
M24256-A
SBGA7 – 7 ball Shell Ball Grid Array – Underside view (ball side)
D3
D2
FD
D1
b
E3
E
FE
E2
BALL "1"
E1
D
A
A1
SBGA-01
Note: 1. Drawing is not to scale.
SBGA7 – 7 ball Shell Ball Grid Array
mm
inches
Symb.
Typ.
Min.
Max.
Typ.
Min.
Max.
A
0.430
0.380
0.480
0.017
0.015
0.019
A1
0.180
0.150
0.210
0.007
0.006
0.008
b
0.350
0.320
0.380
0.014
0.013
0.015
D
3.555
3.525
3.585
0.140
0.138
0.142
D2 1
1.000
0.970
1.030
0.039
0.038
0.041
E
2.275
2.245
2.305
0.090
0.088
0.091
FD
1.278
—
—
0.050
—
—
FE
0.388
—
—
0.015
—
—
N
7
7
Note: 1. No ball is closer than D2 to any other ball, thus giving an arrangement of equilateral triangles in which:
E1 = D2/2 ; E2 = D2 ; E3 = 3xD2/2
D3 = √3xD2/2 ; D1 = D2 + √3xD2/2
18/20
M24256-A
Table 12. Revision History
Date
Rev
Description of Revision
17-Apr-2000
1.2
SBGA7(EA) package added on pp 1, 2, OrderInfo, PackageData
E1 and E0 are specified as having to be tied either to VCC or VSS
22-May-2001
1.3
-R voltage range removed
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Depiction of Start and Stop condition on timing illustrations revised
Write Mode Sequences with WC=1 (data write inhibited) illustration updated
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP8 changed to PDIP8, and Package Mechanical data updated
Document promoted from Preliminary Data to Full Data Sheet
09-Oct-2001
1.4
Document moved from Full Data Sheet to Not for New Design
(please see the M24256-B data sheet for a suitable replacement device)
09-Nov-2001
1.5
Reference made to AN1470, on replacing the M24256-A by the M24256-B
Specification of Test Condition for Leakage Currents in the DC Characteristics table improved
19/20
M24256-A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© November 2001 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies Austalia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
www.st.com
20/20