INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4042B MSI Quadruple D-latch Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4042B MSI Quadruple D-latch DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the same state, either HIGH or LOW. O0 to O3 follow D0 to D3 as long as both E0 and E1 remain in the same state. When E0 and E1 are different, D0 to D3 do not affect O0 to O3 and the information in the latch is stored. O0 to O3 are always the complement of O0 to O3. The exclusive-OR input structure allows the choice of either polarity for E0 and E1. With one enable input HIGH, the other enable input is active HIGH; with one enable input LOW, the other enable input is active LOW. Fig.2 Pinning diagram. HEF4042BP(N): 16-lead DIL; plastic HEF4042BD(F): 16-lead DIL; ceramic (cerdip) (SOT38-1) (SOT74) HEF4042BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING D0 to D3 data inputs E0 and E1 enable inputs O0 to O3 parallel latch outputs O0 to O3 complementary parallel latch outputs APPLICATION INFORMATION Some examples of applications for the HEF4042B are: • Buffer storage • Holding register FAMILY DATA, IDD LIMITS category MSI See Family Specifications Fig.1 Functional diagram. January 1995 2 Philips Semiconductors Product specification HEF4042B MSI Quadruple D-latch FUNCTION TABLE E0 E1 OUTPUT On L L Dn L H latched H L latched H H Dn Note 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage). Fig.3 Logic diagram. Fig.4 Logic diagram (one latch). January 1995 3 Philips Semiconductors Product specification HEF4042B MSI Quadruple D-latch AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYPICAL EXTRAPOLATION FORMULA MIN. TYP. MAX. Propagation delays D → O, O HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 E → O, O HIGH to LOW 190 ns 67 ns + (0,55 ns/pF) CL 40 80 ns 28 ns + (0,23 ns/pF) CL 30 55 ns 22 ns + (0,16 ns/pF) CL 85 175 ns 57 ns + (0,55 ns/pF) CL 40 75 ns 28 ns + (0,23 ns/pF) CL 30 60 ns 22 ns + (0,16 ns/pF) CL 130 260 ns 102 ns + (0,55 ns/pF) CL 50 105 ns 38 ns + (0,23 ns/pF) CL 35 75 ns 27 ns + (0,16 ns/pF) CL 120 245 ns 92 ns + (0,55 ns/pF) CL 50 105 ns 38 ns + (0,23 ns/pF) CL 15 35 75 ns 27 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 30 60 ns 5 10 tPHL 15 5 LOW to HIGH 95 10 tPLH Output transition times HIGH to LOW LOW to HIGH 10 tTHL 6 ns + (0,28 ns/pF) CL 15 20 40 ns 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 tTLH 15 Set-up time 5 D→E 10 tsu 15 Hold time 5 D→E 10 thold 15 Minimum enable 5 pulse width 10 15 VDD V Dynamic power 9 ns + (0,42 ns/pF) CL 5 tWE 30 10 ns 20 5 ns 20 5 ns 15 −5 ns 15 0 ns 15 0 ns 90 45 ns 40 20 ns 30 15 ns 10 ns + (1,0 ns/pF) CL see also waveforms Figs 5 and 6 TYPICAL FORMULA FOR P (W) 3800 fi + ∑ (foCL) × VDD2 dissipation per 10 15 700 fi + ∑ (foCL) × package (P) 15 41 100 fi + ∑ (foCL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification HEF4042B MSI Quadruple D-latch Either E0 or E1 is held HIGH or LOW while the other enable input is pulsed as the function table shows. Fig.5 Waveforms showing propagation delays for D to O, with latch enabled. January 1995 5 Philips Semiconductors Product specification HEF4042B MSI Quadruple D-latch Fig.6 Waveforms showing minimum enable pulse width, set-up time and hold time for E and D. Set-up and hold-times are shown as positive values but may be specified as negative values. January 1995 6