Cypress CY14E104L-ZSP25XCT 4 mbit (512k x 8/256k x 16) nvsram Datasheet

PRELIMINARY
CY14E104L/CY14E104N
4 Mbit (512K x 8/256K x 16) nvSRAM
Features
Functional Description
■
15 ns, 20 ns, 25 ns, and 45 ns access times
■
Internally organized as 512K x 8 (CY14E104L) or 256K x 16
(CY14E104N)
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap® nonvolatile elements is initiated by
software, device pin, or AutoStore® on power down
■
RECALL to SRAM initiated by software or power up
■
Infinite read, write, and recall cycles
■
200,000 STORE cycles to QuantumTrap
The Cypress CY14E104L/CY14E104N is a fast static RAM with
a nonvolatile element in each memory cell. The memory is
organized as 512K words of 8 bits each or 256K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the reliable
QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
■
20 year data retention
■
Single 5V +10% operation
■
Commercial and industrial temperatures
■
48-pin FBGA and 44/54-pin TSOP II packages
■
Pb-free and RoHS compliance
Logic Block Diagram
VCC
VCAP
[1]
Address A0 - A18
[1]
CE
OE
DQ0 - DQ7
CY14E104L
CY14E104N
WE
HSB
BHE
BLE
VSS
Note
1. Address A0 - A18 and Data DQ0 - DQ7 for x8 configuration, Address A0 - A17 and Data DQ0 - DQ15 for x16 configuration.
Cypress Semiconductor Corporation
Document Number: 001-09603 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 20, 2008
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CY14E104L/CY14E104N
PRELIMINARY
Pinouts
Figure 1. Pin Diagram - 48 FBGA
48-FBGA
48-FBGA
Top View
(not to scale)
Top View
(not to scale)
(x8)
(x16)
2
3
4
5
6
NC
OE
A0
A1
A2
NC
NC
NC
A3
A4
CE
DQ0
NC
A5
A6
VSS
DQ1
A17
1
VCC
DQ2 VCAP
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
NC
A
NC
B
DQ8
BHE
A3
A4
CE
DQ0
B
NC
DQ4
C
DQ9 DQ10
A5
A6
DQ1
DQ2
C
A7
DQ5
VCC
D
VSS
DQ11 A17
A7
DQ3
VCC
D
A16
DQ6
VSS
E
VCC
DQ12 VCAP
A16
DQ4
VSS
E
DQ3
NC
A14
A15
NC
DQ7
F
DQ14 DQ13
A14
A15
DQ5 DQ6
F
[3]
NC
HSB
A12
A13
WE
NC
G
DQ15 HSB
A12
A13
WE
DQ7
G
A18
A8
A9
A10
A11
[2]
NC
H
NC
A9
A10
A11
[3]
NC
H
[2]
A8
Figure 2. Pin Diagram - 44 TSOP II
NC
[3]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 - TSOP II
(x8)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
HSB
NC
[2]
NC
A18
A17
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
30
29
28
27
26
25
24
23
VCAP
A14
A13
A12
A11
A10
NC
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 - TSOP II
(x16)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
Notes
2. Address expansion for 8 Mbit. NC pin is not connected to the die.
3. Address expansion for 16 Mbit. NC pin is not connected to the die.
Document Number: 001-09603 Rev. *H
Page 2 of 22
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CY14E104L/CY14E104N
PRELIMINARY
Pinouts
(continued)
Figure 3. Pin Diagram - 54 TSOP II (x16)
NC
[3]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
54 - TSOP II
(x16)
Top View
(not to scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
NC [2]
A17
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
NC
NC
NC
Pin Definitions
Pin Name
IO Type
A0 – A18
Input
A0 – A17
Description
Address Inputs Used to Select one of the 524, 288 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x16 Configuration.
DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
operation.
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
NC
No Connect No Connects. This pin is not connected to the die.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Input
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Input
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address
location latched by the falling edge of CE.
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE HIGH.
WE
CE
OE
VSS
VCC
Ground
Ground for the Device. Must be connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
HSB
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Document Number: 001-09603 Rev. *H
Page 3 of 22
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CY14E104L/CY14E104N
PRELIMINARY
The CY14E104L/CY14E104N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
the SRAM read and write operations are inhibited. The
CY14E104L/CY14E104N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations.
SRAM Read
The CY14E104L/CY14E104N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0-18 or A0-17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. When
the read is initiated by an address transition, the outputs are valid
after a delay of tAA (read cycle #1). If the read is initiated by CE
or OE, the outputs are valid at tACE or at tDOE, whichever is later
(read cycle #2). The data output repeatedly responds to address
changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common IO pins DQ0-15 are
written into the memory if the data is valid tSD before the end of
a WE controlled write or before the end of an CE controlled write.
It is recommended that OE be kept HIGH during the entire write
cycle to avoid data bus contention on common IO lines. If OE is
left LOW, internal circuitry turns off the output buffers tHZWE after
WE goes LOW.
AutoStore Operation
The CY14E104L/CY14E104N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB; Software Store activated by an address
sequence; AutoStore activated on device power down. The
AutoStore operation is a unique feature of QuantumTrap
technology
and
is
enabled
by
default
on
the
CY14E104L/CY14E104N.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, which is
below the minimum specified operating voltage, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Document Number: 001-09603 Rev. *H
Figure 4. AutoStore Mode
Vcc
0.1uF
10kOhm
Device Operation
Vcc
WE
VCAP
VSS
VCAP
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 7 for the size of VCAP.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Hardware STORE (HSB) Operation
The CY14E104L/CY14E104N provides the HSB pin to control
and acknowledge the STORE operations. The HSB pin is used
to request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14E104L/CY14E104N conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle begins
only if a write to the SRAM has taken place since the last STORE
or RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition when
the STORE (initiated by any means) is in progress.
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14E104L/CY14E104N continues SRAM operations for
tDELAY. During tDELAY, multiple SRAM read operations may take
place. If a write is in progress when HSB is pulled LOW it is
allowed a time, tDELAY, to complete. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH.
During any STORE operation, regardless of how it is initiated,
the CY14E104L/CY14E104N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation,
the
CY14E104L/CY14E104N remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Page 4 of 22
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CY14E104L/CY14E104N
PRELIMINARY
Hardware RECALL (Power Up)
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important to use read cycles and not write cycles
in the sequence, although it is not necessary that OE be LOW
for a valid sequence. After the tSTORE cycle time is fulfilled, the
SRAM is activated again for a read and write operation.
During power up or after any low power condition (VCC <
VSWITCH), an internal RECALL request is latched. When VCC
exceeds the sense voltage of VSWITCH, a RECALL cycle is
automatically initiated and takes tHRECALL to complete.
Software STORE
Software RECALL
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14E104L/CY14E104N
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Table 1. Mode Selection
OE
X
A15 - A0
Mode
IO
Power
X
Not Selected
Output High Z
Standby
H
L
X
Read SRAM
Output Data
Active
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[4,5,6]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[4,5,6]
CE
H
WE
X
L
L
Notes
4. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
5. While there are 19 address lines on the CY14E104L/CY14E104N, only the lower 16 lines are used to control software modes.
6. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
Document Number: 001-09603 Rev. *H
Page 5 of 22
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CY14E104L/CY14E104N
PRELIMINARY
Table 1. Mode Selection (continued)
CE
L
WE
H
OE
L
A15 - A0
Mode
IO
Power
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[4,5,6]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[4,5,6]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
Document Number: 001-09603 Rev. *H
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Data Protection
The CY14E104L/CY14E104N protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14E104L/ CY14E104N
is in a write mode (both CE and WE are LOW) at power up, after
a RECALL or STORE, the write is inhibited until a negative
transition on CE or WE is detected. This protects against
inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer CY application note AN1064.
Page 6 of 22
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PRELIMINARY
CY14E104L/CY14E104N
Maximum Ratings
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Surface Mount Pb Soldering
Temperature (3 Seconds) .......................................... +260°C
Storage Temperature ................................. –65°C to +150°C
Output Short Circuit Current [7] .................................... 15 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +150°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V
Latch Up Current ................................................... > 200 mA
Voltage Applied to Outputs
in High-Z State....................................... –0.5V to VCC + 0.5V
Operating Range
Input Voltage.............................................–0.5V to Vcc+0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
Range
Commercial
Industrial
Ambient Temperature
VCC
0°C to +70°C
4.5V to 5.5V
–40°C to +85°C
4.5V to 5.5V
DC Electrical Characteristics
Over the Operating Range (VCC = 4.5V to 5.5V) [9]
Parameter
Description
ICC1
Average VCC Current
ICC2
ICC3[8]
ICC4
ISB
IIX
IOZ
VIH
VIL
VOH
VOL
VCAP
Average VCC Current
during STORE
Average VCC Current at
tRC= 200 ns, 5V, 25°C
typical
Test Conditions
tRC = 15 ns
Commercial
tRC = 20 ns
tRC = 25 ns
tRC = 45 ns
Dependent on output loading and cycle rate.Values Industrial
obtained without output loads. IOUT = 0 mA
Min
All Inputs Don’t Care, VCC = Max.
Average current for duration tSTORE
WE > (VCC – 0.2). All other I/P cycling.
Dependent on output loading and cycle rate. Values obtained
without output loads.
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Storage Capacitor
IOUT = –2 mA
IOUT = 4 mA
Between VCAP pin and VSS, 5V Rated
Unit
70
65
65
50
75
70
70
52
mA
mA
mA
mA
mA
mA
6
mA
35
mA
6
mA
3
mA
–1
+1
μA
–100
+1
μA
–1
+1
μA
Average VCAP Current All Inputs Don’t Care, VCC = Max.
during AutoStore Cycle Average current for duration tSTORE
VCC Standby Current CE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V). Standby
current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
Input Leakage Current VCC = Max, VSS < VIN < VCC
(except HSB)
Input Leakage Current VCC = Max, VSS < VIN < VCC
(for HSB)
Off-State Output
VCC = Max., VSS < VIN < VCC, CE or OE > VIH
Leakage Current
Max
2.2
VCC + 0.5
Vss – 0.5
0.8
2.4
0.4
61
82
V
V
V
V
μF
Notes
7. Outputs shorted for no more than one second. Only one output shorted at a time.
8. Typical conditions for the active current shown on the front page of the data sheet are average values at 25°C (room temperature), and VCC = 5V. Not 100% tested.
9. The HSB pin has IOUT=-10 uA for VOH of 2.4V.This parameter is characterized but not tested.
Document Number: 001-09603 Rev. *H
Page 7 of 22
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CY14E104L/CY14E104N
PRELIMINARY
Capacitance
In the following table, the capacitance parameters are listed.[10]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
Unit
7
pF
7
pF
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[10]
Parameter
ΘJA
ΘJC
Description
Test Conditions
48-FBGA 44-TSOP II 54-TSOP II Unit
Thermal Resistance Test conditions follow standard test methods and
(Junction to Ambient) procedures for measuring thermal impedance, in
Thermal Resistance accordance with EIA/JESD51.
28.82
31.11
30.73
°C/W
7.84
5.56
6.08
°C/W
(Junction to Case)
Figure 5. AC Test Loads
963Ω
5.0V
for tri-state specs
963Ω
5.0V
R1
R1
OUTPUT
OUTPUT
R2
512Ω
30 pF
R2
512Ω
5 pF
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% - 90%) ........................ <5 ns
Input and Output Timing Reference Levels .................... 1.5V
AC Switching Characteristics
Parameters
15 ns
Description
Cypress
Alt
Parameters Parameters
Min
20 ns
Max
Min
25 ns
Max
Min
Max
45 ns
Min
Max
Unit
SRAM Read Cycle
tACE
tACS
Chip Enable Access Time
[11]
tRC
Read Cycle Time
tAA [12]
tAA
Address Access Time
tDOE
tOE
Output Enable to Data Valid
tOHA
tOH
Output Hold After Address Change
3
tLZCE [13]
tLZ
Chip Enable to Output Active
3
tHZCE [13]
tHZ
Chip Disable to Output Inactive
tRC
15
15
20
20
15
25
20
10
12
3
3
ns
45
ns
ns
20
3
3
8
45
45
25
10
3
7
25
3
10
ns
ns
ns
15
ns
Notes
10. These parameters are guaranteed but not tested.
11. WE must be HIGH during SRAM read cycles.
12. Device is continuously selected with CE and OE both LOW.
13. Measured ±200 mV from steady state output voltage.
Document Number: 001-09603 Rev. *H
Page 8 of 22
[+] Feedback
CY14E104L/CY14E104N
PRELIMINARY
AC Switching Characteristics
(continued)
Parameters
15 ns
Description
Cypress
Alt
Parameters Parameters
tLZOE [13]
tOLZ
Output Enable to Output Active
[13]
tHZOE
Min
20 ns
Max
0
Min
25 ns
Max
0
Min
Max
45 ns
Min
0
7
15
Output Disable to Output Inactive
tPA
Chip Enable to Power Active
tPD [10]
tPS
Chip Disable to Power Standby
15
20
25
45
ns
tDBE
-
Byte Enable to Data Valid
10
10
12
20
ns
tLZBE
-
Byte Enable to Output Active
tHZBE
-
Byte Disable to Output Inactive
15
ns
0
0
0
0
0
7
8
15
ns
tOHZ
0
10
Unit
tPU [10]
0
8
Max
0
10
ns
ns
ns
SRAM Write Cycle
tWC
tWC
Write Cycle Time
tPWE
tWP
Write Pulse Width
10
15
20
30
ns
tSCE
tCW
Chip Enable To End of Write
15
15
20
30
ns
tSD
tDW
Data Setup to End of Write
5
8
10
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
0
ns
tAW
tAW
Address Setup to End of Write
10
15
20
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
15
20
25
0
45
0
ns
0
ns
tHZWE [13,14] tWZ
tLZWE [13]
tOW
Write Enable to Output Disable
Output Active after End of Write
3
3
3
3
ns
tBW
Byte Enable to End of Write
15
15
20
30
ns
-
7
8
10
15
ns
AutoStore/Power Up RECALL
Parameters
Description
CY14E104L/CY14E104N
Min
Max
Unit
tHRECALL [15]
Power Up RECALL Duration
20
ms
tSTORE [16]
STORE Cycle Duration
15
ms
VSWITCH
Low Voltage Trigger Level
tVCCRISE
VCC Rise Time
4.4
150
V
μs
Notes
14. If WE is low when CE goes low, the outputs remain in the high impedance state.
15. tHRECALL starts from the time VCC rises above VSWITCH.
16. If an SRAM write has not taken place since the last nonvolatile cycle, no STORE takes place.
Document Number: 001-09603 Rev. *H
Page 9 of 22
[+] Feedback
CY14E104L/CY14E104N
PRELIMINARY
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed. [17, 18]
Parameters
15 ns
Description
Min
Max
20 ns
Min
Max
25 ns
Min
Max
45 ns
Min
Max
Unit
tRC
STORE/RECALL Initiation Cycle Time
15
20
25
45
ns
tAS
Address Setup Time
0
0
0
0
ns
tCW
Clock Pulse Width
12
15
20
30
tGHAX
Address Hold Time
1
1
1
tRECALL
RECALL Duration
200
200
200
200
μs
tSS [19, 20]
Soft Sequence Processing Time
70
70
70
70
μs
ns
ns
Hardware STORE Cycle
Parameters
Description
CY14E104L/CY14E104N
Min
Max
70
tDELAY [21]
Time Allowed to Complete SRAM Cycle
1
tHLHX
Hardware STORE Pulse Width
15
Unit
μs
ns
Notes
17. The software sequence is clocked with CE controlled or OE controlled reads.
18. The six consecutive addresses must be read in the order listed in the Table 1 on page 5. WE must be HIGH during all six consecutive cycles.
19. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
20. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
21. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete.
Document Number: 001-09603 Rev. *H
Page 10 of 22
[+] Feedback
CY14E104L/CY14E104N
PRELIMINARY
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled [11, 12, 22]
tRC
ADDRESS
t AA
t OHA
DQ (DATA OUT)
DATA VALID
Figure 7. SRAM Read Cycle #2: CE and OE Controlled [11, 22, 23]
tRC
ADDRESS
tLZCE
CE
tACE
tPD
tHZCE
OE
tLZOE
t HZOE
tDOE
BHE , BLE
tLZBE
DQ (DATA OUT)
t PU
ICC
tHZCE
tHZBE
tDBE
DATA VALID
ACTIVE
STANDBY
Notes
22. HSB must remain HIGH during read and write cycles.
23. BHE and BLE are applicable for x16 configuration only.
Document Number: 001-09603 Rev. *H
Page 11 of 22
[+] Feedback
CY14E104L/CY14E104N
PRELIMINARY
Switching Waveforms
(continued)
Figure 8. SRAM Write Cycle #1: WE Controlled[14, 22, 23, 24]
tWC
ADDRESS
tHA
tSCE
CE
tAW
tSA
tPWE
WE
tBW
BHE , BLE
tSD
tHD
DATA VALID
DATA IN
tHZWE
DATA OUT
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
Figure 9. SRAM Write Cycle #2: CE Controlled[14, 22, 23, 24]
tWC
ADDRESS
tSA
tSCE
CE
tHA
tAW
WE
BHE , BLE
tPWE
tBW
tSD
DATA IN
DATA OUT
tHD
DATA VALID
HIGH IMPEDANCE
Note
24. CE or WE must be > VIH during address transitions.
Document Number: 001-09603 Rev. *H
Page 12 of 22
[+] Feedback
CY14E104L/CY14E104N
PRELIMINARY
Switching Waveforms
(continued)
Figure 10. AutoStore/Power Up RECALL[25]
No STORE occurs
without atleast one
SRAM write
STORE occurs only
if a SRAM write
has happened
VCC
VSWITCH
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
tHRECALL
Read & Write Inhibited
Figure 11. CE Controlled Software STORE/RECALL Cycle[18]
Note
25. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
Document Number: 001-09603 Rev. *H
Page 13 of 22
[+] Feedback
CY14E104L/CY14E104N
PRELIMINARY
Switching Waveforms
(continued)
Figure 12. OE Controlled Software STORE/RECALL Cycle[18]
tRC
ADDRESS # 1
ADDRESS
CE
tAS
ADDRESS # 6
tCW
OE
tGHAX
DATA VALID
a
a
DQ (DATA)
t STORE / t RECALL
DATA VALID
a
a
a
a
a
a
a
a
a
a
a a
tRC
HIGH IMPEDANCE
Figure 13. Hardware STORE Cycle[21]
Figure 14. Soft Sequence Processing[19, 20]
tSS
Document Number: 001-09603 Rev. *H
tSS
Page 14 of 22
[+] Feedback
PRELIMINARY
CY14E104L/CY14E104N
PART NUMBERING NOMENCLATURE
CY 14 E 104 L - ZS P 15 X C T
Option:
T - Tape & Reel
Blank - Std.
Pb-free
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
P - 54 Pin
Package:
Blank - 44 Pin BA - 48 FBGA
ZS - TSOP II
Data Bus:
L - x8
N - x16
Speed:
15 - 15 ns
20 - 20 ns
25 - 25 ns
45 - 45 ns
Density:
104 - 4 Mb
Voltage:
E - 5.0V
NVSRAM
14 - AutoStore + Software Store + Hardware Store
Cypress
Document Number: 001-09603 Rev. *H
Page 15 of 22
[+] Feedback
PRELIMINARY
CY14E104L/CY14E104N
Ordering Information
Speed
(ns)
15
20
Ordering Code
Package
Diagram
Package Type
Operating Range
CY14E104L-ZS15XCT
51-85087
44-pin TSOP II
Commercial
CY14E104L-ZS15XIT
51-85087
44-pin TSOP II
Industrial
CY14E104L-ZS15XI
51-85087
44-pin TSOP II
CY14E104L-BA15XCT
51-85128
48-ball FBGA
Commercial
Industrial
CY14E104L-BA15XIT
51-85128
48-ball FBGA
CY14E104L-BA15XI
51-85128
48-ball FBGA
CY14E104L-ZSP15XCT
51-85160
54-pin TSOP II
Commercial
CY14E104L-ZSP15XIT
51-85160
54-pin TSOP II
Industrial
CY14E104L-ZSP15XI
51-85160
54-pin TSOP II
CY14E104N-ZS15XCT
51-85087
44-pin TSOP II
Commercial
Industrial
CY14E104N-ZS15XIT
51-85087
44-pin TSOP II
CY14E104N-ZS15XI
51-85087
44-pin TSOP II
CY14E104N-BA15XCT
51-85128
48-ball FBGA
Commercial
CY14E104N-BA15XIT
51-85128
48-ball FBGA
Industrial
CY14E104N-BA15XI
51-85128
48-ball FBGA
CY14E104N-ZSP15XCT
51-85160
54-pin TSOP II
Commercial
Industrial
CY14E104N-ZSP15XIT
51-85160
54-pin TSOP II
CY14E104N-ZSP15XI
51-85160
54-pin TSOP II
CY14E104L-ZS20XCT
51-85087
44-pin TSOP II
Commercial
CY14E104L-ZS20XIT
51-85087
44-pin TSOP II
Industrial
CY14E104L-ZS20XI
51-85087
44-pin TSOP II
CY14E104L-BA20XCT
51-85128
48-ball FBGA
Commercial
Industrial
CY14E104L-BA20XIT
51-85128
48-ball FBGA
CY14E104L-BA20XI
51-85128
48-ball FBGA
CY14E104L-ZSP20XCT
51-85160
54-pin TSOP II
Commercial
CY14E104L-ZSP20XIT
51-85160
54-pin TSOP II
Industrial
CY14E104L-ZSP20XI
51-85160
54-pin TSOP II
CY14E104N-ZS20XCT
51-85087
44-pin TSOP II
Commercial
Industrial
CY14E104N-ZS20XIT
51-85087
44-pin TSOP II
CY14E104N-ZS20XI
51-85087
44-pin TSOP II
CY14E104N-BA20XCT
51-85128
48-ball FBGA
Commercial
CY14E104N-BA20XIT
51-85128
48-ball FBGA
Industrial
CY14E104N-BA20XI
51-85128
48-ball FBGA
CY14E104N-ZSP20XCT
51-85160
54-pin TSOP II
Commercial
Industrial
CY14E104N-ZSP20XIT
51-85160
54-pin TSOP II
CY14E104N-ZSP20XI
51-85160
54-pin TSOP II
Document Number: 001-09603 Rev. *H
Page 16 of 22
[+] Feedback
PRELIMINARY
CY14E104L/CY14E104N
Ordering Information (continued)
Speed
(ns)
25
45
Ordering Code
Package
Diagram
Package Type
Operating Range
CY14E104L-ZS25XCT
51-85087
44-pin TSOP II
Commercial
CY14E104L-ZS25XIT
51-85087
44-pin TSOP II
Industrial
CY14E104L-ZS25XI
51-85087
44-pin TSOP II
CY14E104L-BA25XCT
51-85128
48-ball FBGA
Commercial
Industrial
CY14E104L-BA25XIT
51-85128
48-ball FBGA
CY14E104L-BA25XI
51-85128
48-ball FBGA
CY14E104L-ZSP25XCT
51-85160
54-pin TSOP II
Commercial
CY14E104L-ZSP25XIT
51-85160
54-pin TSOP II
Industrial
CY14E104L-ZSP25XI
51-85160
54-pin TSOP II
CY14E104N-ZS25XCT
51-85087
44-pin TSOP II
Commercial
Industrial
CY14E104N-ZS25XIT
51-85087
44-pin TSOP II
CY14E104N-ZS25XI
51-85087
44-pin TSOP II
CY14E104N-BA25XCT
51-85128
48-ball FBGA
Commercial
CY14E104N-BA25XIT
51-85128
48-ball FBGA
Industrial
CY14E104N-BA25XI
51-85128
48-ball FBGA
CY14E104N-ZSP25XCT
51-85160
54-pin TSOP II
Commercial
Industrial
CY14E104N-ZSP25XIT
51-85160
54-pin TSOP II
CY14E104N-ZSP25XI
51-85160
54-pin TSOP II
CY14E104L-ZS45XCT
51-85087
44-pin TSOP II
Commercial
CY14E104L-ZS45XIT
51-85087
44-pin TSOP II
Industrial
CY14E104L-ZS45XI
51-85087
44-pin TSOP II
CY14E104L-BA45XCT
51-85128
48-ball FBGA
Commercial
Industrial
CY14E104L-BA45XIT
51-85128
48-ball FBGA
CY14E104L-BA45XI
51-85128
48-ball FBGA
CY14E104L-ZSP45XCT
51-85160
54-pin TSOP II
Commercial
CY14E104L-ZSP45XIT
51-85160
54-pin TSOP II
Industrial
CY14E104L-ZSP45XI
51-85160
54-pin TSOP II
CY14E104N-ZS45XCT
51-85087
44-pin TSOP II
Commercial
Industrial
CY14E104N-ZS45XIT
51-85087
44-pin TSOP II
CY14E104N-ZS45XI
51-85087
44-pin TSOP II
CY14E104N-BA45XCT
51-85128
48-ball FBGA
Commercial
CY14E104N-BA45XIT
51-85128
48-ball FBGA
Industrial
CY14E104N-BA45XI
51-85128
48-ball FBGA
CY14E104N-ZSP45XCT
51-85160
54-pin TSOP II
Commercial
Industrial
CY14E104N-ZSP45XIT
51-85160
54-pin TSOP II
CY14E104N-ZSP45XI
51-85160
54-pin TSOP II
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document Number: 001-09603 Rev. *H
Page 17 of 22
[+] Feedback
CY14E104L/CY14E104N
PRELIMINARY
Package Diagrams
Figure 15. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
1
23
10.262 (0.404)
10.058 (0.396)
11.938 (0.470)
11.735 (0.462)
22
EJECTOR PIN
44
TOP VIEW
0.800 BSC
(0.0315)
OR E
K X A
SG
BOTTOM VIEW
0.400(0.016)
0.300 (0.012)
10.262 (0.404)
10.058 (0.396)
BASE PLANE
0.210 (0.0083)
0.120 (0.0047)
0°-5°
0.10 (.004)
Document Number: 001-09603 Rev. *H
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
18.517 (0.729)
18.313 (0.721)
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
51-85087-*A
51-85160-**
Page 18 of 22
[+] Feedback
CY14E104L/CY14E104N
PRELIMINARY
Package Diagrams (continued)
Figure 16. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
10.00±0.10
10.00±0.10
1
F
G
H
H
1.875
A
A
B
0.75
6.00±0.10
0.53±0.05
B
0.15 C
0.21±0.05
0.25 C
3.75
6.00±0.10
0.15(4X)
Document Number: 001-09603 Rev. *H
1.20 MAX
0.36
SEATING PLANE
C
51-85128-*D
Page 19 of 22
[+] Feedback
PRELIMINARY
CY14E104L/CY14E104N
Package Diagrams (continued)
Figure 17. 54-pin TSOP II (51-85160)
51-85160-**
Document Number: 001-09603 Rev. *H
Page 20 of 22
[+] Feedback
PRELIMINARY
CY14E104L/CY14E104N
Document History Page
Document Title: CY14E104L/CY14E104N 4 Mbit (512K x 8/256K x 16) nvSRAM
Document Number: 001-09603
Orig. of
Rev. ECN No. Submission
Description of Change
Date
Change
**
493192
See ECN
TUP
New Data Sheet
*A
499597
See ECN
PCI
Removed 35 ns speed bin
Added 55 ns speed bin. Updated AC table for the same
Changed “Unlimited” read/write to “infinite” read/write
Features section: Changed typical ICC at 200-ns cycle time to 8 mA
Changed STORE cycles from 500K to 200K cycles
Shaded Commercial grade in operating range table
Modified Icc/Isb specs
Corrected Vcc from 3.0v to 5.5v in the Low Average Active Power description section
48 FBGA package nomenclature changed from BW to BV
Modified part nomenclature table. Changes reflected in the ordering information table
*B
517928
See ECN
TUP
Removed 55ns speed bin
Changed pinout for 44TSOPII and 54TSOPII Packages.
Changed ISB to 1mA
Changed ICC4 to 3mA
Changed VCAP min to 35μF
Changed tSTORE to 15ns
Changed tPWE to 10ns
Changed tSCE to 15ns
Changed tSD to 5ns
Changed tAW to 10ns
Removed tHLBL
Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW
Removed min. specification for Vswitch
Changed tGLAX to 1ns
Added tDELAY max. of 70us
Changed tSS specification from 70us min. to 70us max.
*C
774157
See ECN
UHA
Changed the data sheet from Advance information to Preliminary
48 FBGA package code changed from BV to BA
Removed 48 FBGA package in X8 configuration in ordering information.
Changed tDBE to 10ns in 15ns part
Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns
Changed tBW in 15ns part to 15ns and in 25ns part to 20ns
Changed tGLAX to tGHAX
Changed the value of ICC3 to 25mA
Changed the value of tAW in 15ns part to 15ns
Changed A18 and A19 Pins in FBGA Pin Configuration to NC
In AC test loads changed the value of R1 to 963Ω and R2 to 512Ω
*D
914280
See ECN
UHA
Included all the information for 45 ns part in this data sheet
*E
1890926
See ECN
vsutmp8/A Updated logic block diagram
ESA
Updated Pin definition table
Added Footnote 1, 2 and 3.
Added 48-FBGA (X8) Pin Diagram
Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8)
package.
Corrected typo in VIL min spec
Changed Vswitch value from 2.65V to 4.4V
Changed the value of ICC3 from 25mA to 13mA
Changed ISB value from 1mA to 2mA
Updated ordering information table
Rearranging of Footnotes.
Document Number: 001-09603 Rev. *H
Page 21 of 22
[+] Feedback
PRELIMINARY
CY14E104L/CY14E104N
Document Title: CY14E104L/CY14E104N 4 Mbit (512K x 8/256K x 16) nvSRAM
Document Number: 001-09603
Orig. of
Rev. ECN No. Submission
Description of Change
Date
Change
*F
2267286
See ECN
GVCH/PY Updated Figure 4 (Autostore mode)
RS
Changed ICC2 & ICC4 from 3mA to 6mA. Changed ICC3 from 13mA to 15mA
Changed ISB from 2mA to 3mA
Added input leakage current (IIX) for HSB in DC Electrical Characteristics table
Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max value
Corrected typo in tHZCE and tHZOE min spec and added max value15ns for 45ns part
Corrected typo in tPU max spec and added min value 0ns for 45ns part
Corrected typo in tAW value from 15ns to 10ns for 15ns part
Changed tRECALL from 100us to 200us
Added tRECALL and tSS max value for 45ns part in Software controlled STORE/ReCALL Cycle table
Reframed footnote 6, 14 and 21. Added footnote 9 and 25
Added footnote 14 to figure 7 and footnote 14, 22 and 24 to figure 8
*G 2483627
See ECN
GVCH/PY Removed 8 mA typical ICC at 200 ns cycle time in Feature section
RS
Referenced footnote 8 to ICC3 in DC Characteristics table
Changed ICC3 from 15 mA to 35 mA
Changed Vcap minimum value from 54uF to 61uF. Changed tAVAV to tRC
Figure 11:Changed tSA to tAS and tSCE to tCW
*H
2519319
06/20/08
GVCH/PY Added 20 ns access speed in “Features”
RS
Added ICC1 for tRC=20 ns for both industrial and Commecial temperature Grade
Updated thermal resistance values for 48-FBGA, 44-TSOP II and 54-TSOP II packages
Added AC Switching Characteristics specs for 20 ns access speed
Added Software controlled STORE/RECALL cycle specs for 20 ns access speed
Updated ordering information and Part numbering nomenclature
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© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-09603 Rev. *H
Revised June 20, 2008
Page 22 of 22
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