AD ADG3243BRJ-REEL7 2.5 v/3.3 v, 2-bit, individual control level translator bus switch Datasheet

2.5 V/3.3 V, 2-Bit, Individual Control
Level Translator Bus Switch
ADG3243
FEATURES
225 ps Propagation Delay through the Switch
4.5 ⍀ Switch Connection between Ports
Data Rate 1.5 Gbps
2.5 V/3.3 V Supply Operation
Level Translation
3.3 V to 2.5 V
2.5 V to 1.8 V
Small Signal Bandwidth 710 MHz
8-Lead SOT-23 Package
FUNCTIONAL BLOCK DIAGRAM
A0
B0
BE0
APPLICATIONS
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Switch Applications
A1
B1
BE1
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3243 is a 2.5 V or 3.3 V, 2-bit, 2-port digital switch
with individual channel control. It is designed on a low voltage
CMOS process, which provides low power dissipation yet gives
high switching speed and very low on resistance. This allows the
inputs to be connected to the outputs without additional propagation delay or generating additional ground bounce noise.
1.
2.
3.
4.
5.
3.3 V or 2.5 V supply operation.
Extremely low propagation delay through switch.
4.5 Ω switches connect inputs to outputs.
Level/voltage translation.
Tiny SOT-23 package.
The switches are enabled by means of the bus enable (BEx) input
signal. This digital switch allows a bidirectional signal to be
switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. This makes the device
suited to applications requiring level translation between different
supplies, such as converter to DSP/microcontroller interfacing.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADG3243–SPECIFICATIONS1
Parameter
Symbol
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
VINH
Input Low Voltage
VINL
VINL
Input Leakage Current
II
OFF State Leakage Current
IOZ
ON State Leakage Current
Maximum Pass Voltage
VP
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS 3
Propagation Delay A to B or B to A, t PD4
Propagation Delay Matching 5
Bus Enable Time BEx to A or B6
Bus Disable Time BEx to A or B6
Bus Enable Time BEx to A or B6
Bus Disable Time BEx to A or B6
Maximum Data Rate
Channel Jitter
DIGITAL SWITCH
On Resistance
On Resistance Matching
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
Increase in ICC per Input7
(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX,
unless otherwise noted.)
Conditions
Min
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VA/VB = VCC = 3.3 V, IO = –5 µA
VA/VB = VCC = 2.5 V, IO= –5 µA
CA OFF
CB OFF
CA, CB ON
CIN
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
tPHL, tPLH
CL = 50 pF, VCC = 3 V
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
VCC = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.3 V to 2.7 V
VCC = 3.3 V; VA/VB = 2 V
VCC = 3.3 V; VA/VB = 2 V
RON
⌬RON
VCC = 3 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, VA = 0 V, IA = 8 mA
ICC
⌬ICC
Digital Inputs = 0 V or V CC
VCC = 3.6 V, BE0 = 3.0 V, BE1 = VCC or GND
2.0
1.5
B Version
Typ2
Max
± 0.01
± 0.01
± 0.01
2.5
1.8
0.8
0.7
±1
±1
±1
2.9
2.1
3.5
3.5
7
4
1
1
1
1
Unit
V
V
V
V
µA
µA
µA
V
V
pF
pF
pF
pF
225
5
4.6
4
4
3.4
ps
ps
ns
ns
ns
ns
Gbps
ps p-p
4.5
12
5
9
0.1
8
28
9
18
0.5
Ω
Ω
Ω
Ω
Ω
0.01
0.15
3.6
1
8
V
µA
µA
3.2
3
3
2.5
1.5
45
2.3
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Typical values are at 25°C, unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6
See Timing Measurement Information section.
7
This current applies to the control pin BEx only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
–2–
REV. 0
ADG3243
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
8-Lead SOT-23
(TA = 25°C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/Ω
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
BE0 1
A0 2
ADG3243
8
VCC
7
BE1
TOP VIEW
6 B0
A1
(Not to Scale)
5 B1
GND 4
3
PIN FUNCTION DESCRIPTIONS
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
BE0
A0
A1
GND
B1
B0
BE1
VCC
Bus Enable (Active Low)
Port A0, Input or Output
Port A1, Input or Output
Ground Reference
Port B1, Input or Output
Port B0, Input or Output
Bus Enable (Active Low)
Positive Power Supply Voltage
Table I. Truth Table
BEx
L
H
Function
Ax = Bx, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
Disconnect
ORDERING GUIDE
Model
Temperature Range
Package Description
Package
Branding
ADG3243BRJ-R2
ADG3243BRJ-REEL
ADG3243BRJ-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
SOT-23 (Small Outline Transistor Package)
SOT-23 (Small Outline Transistor Package)
SOT-23 (Small Outline Transistor Package)
RJ-8
RJ-8
RJ-8
SFA
SFA
SFA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3243 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–3–
ADG3243
TERMINOLOGY
VCC
GND
VINH
VINL
II
IOZ
IOL
VP
RON
⌬RON
CX OFF
CX ON
CIN
ICC
⌬ICC
tPLH, tPHL
tPZH, tPZL
tPHZ, tPLZ
Max Data Rate
Channel Jitter
Positive Power Supply Voltage.
Ground (0 V) Reference.
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
ON Resistance Match between Any Two Channels, i.e., RON max – RON min.
OFF Switch Capacitance.
ON Switch Capacitance.
Control Input Capacitance. This consists of BEx.
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.
It is measured when all control inputs are at a logic high or low level and the switches are OFF.
Extra power supply current component for the EN control input when the input is not driven at the supplies.
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
RON × CL, where CL is the load capacitance.
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BEx.
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control
signal. It is measured as the time taken for the output voltage to change by V⌬ from the original quiescent level,
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Maximum Rate at which Data Can Be Passed through the Switch.
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
–4–
REV. 0
Typical Performance Characteristics–ADG3243
40
40
VCC = 3V
TA = 25ⴗC
35
TA = 25ⴗC
35
30
VCC = 3.3V
15
30
VCC = 3.3V
25
20
VCC = 2.5V
RON (⍀)
25
RON (⍀)
RON (⍀)
20
VCC = 2.3V
20
15
10
ⴙ85ⴗC
15
VCC = 2.7V
VCC = 3.6V
5
0
0
0
1.0
0.5
2.0
1.5
VA/VB (V)
3.0
2.5
5
10
5
3.5
0
TPC 1. On Resistance vs.
Input Voltage
0.5
1.0
1.5
2.0
VA/VB (V)
3.0
VOUT (V)
ⴙ85ⴗC
1.0
VA/VB (V)
0.5
TA = 25ⴗC
IO = –5␮A
VCC = 2.7V
2.0
2.0
VCC = 3.3V
VCC = 3V
1.5
1.5
VCC = 2.5V
VCC = 2.3V
1.0
5
1.0
ⴚ40ⴗC
0.5
ⴙ25ⴗC
0
0
0.5
VA/VB (V)
0.5
1.0
0
1.2
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
0
0
0.5
1.0
2.0
1.5
VA/VB (V)
2.5
3.0
3.5
TA = 25ⴗC
VA = 0V
BEx = 0
2.5
400
2.5
200
1.5
VOUT (V)
250
VCC = 3.3V
100
VCC = 2.5V
50
0
0
5
10 15 20 25 30 35 40 45 50
ENABLE FREQUENCY (MHz)
TPC 7. ICC vs. Enable Frequency
REV. 0
1.5
2.0
VA/VB (V)
2.5
3.0
TA = 25ⴗC
VA = VCC
BEx = 0
VCC = 3.3V
1.5
1.0
1.0
150
1.0
2.0
2.0
VCC = 3.3V
VOUT (V)
ICC (␮A)
350
300
0.5
3.0
3.0
TA = 25ⴗC
0
TPC 6. Pass Voltage vs. VCC
TPC 5. Pass Voltage vs. VCC
500
450
2.0
1.5
TPC 3. On Resistance vs. Input
Voltage for Different Temperatures
VCC = 3.6V
TA = 25ⴗC
IO = –5␮A
2.5
10
0
2.5
3.0
VCC = 2.5V
RON (⍀)
2.5
TPC 2. On Resistance vs.
Input Voltage
15
ⴙ25ⴗC
ⴚ40ⴗC
0
VOUT (V)
10
VCC = 2.5V
0.5
0.5
VCC = 2.5V
0
0
0.02
0.04
0.06
IO (A)
0.08
0.10
TPC 8. Output Low Characteristic
–5–
0
–0.10
–0.08
–0.06
–0.04
IO (A)
–0.02
0
TPC 9. Output High Characteristic
ADG3243
–0.6
VCC = 2.5V
–1.0
–1.2
–1.4
–8
–10
–1.6
–12
–2.0
0
1.0
0.5
1.5
2.0
VA/VB (V)
–40
–50
–60
–70
–80
VCC = 3.3V
–1.8
2.5
3.0
TPC 10. Charge Injection vs.
Source Voltage
–90
–14
0.03
0.1
1
10
100
FREQUENCY (MHz)
1000
TPC 11. Bandwidth vs. Frequency
0
TA = 25ⴗC
–10 VCC = 3.3V/2.5V
VIN = 0dBm
–20 N/W ANALYZER:
–30 RL = RS = 50⍀
4.0
–40
2.5
3.5
–100
0.03 0.1
–60
1000
100
VCC = 3.3V
90 V = 1.5V p-p
IN
80 20dB ATTENUATION
ENABLE
DISABLE
VCC = 3.3V
VCC = 2.5V
–50
1.0
10
100
FREQUENCY (MHz)
TPC 12. Crosstalk vs. Frequency
3.0
TIME (ns)
ATTENUATION (dB)
–6
–20
–30
2.0
JITTER (ps p-p)
QINJ (pC)
–0.8
–4
TA = 25ⴗC
VCC = 3.3V/2.5V
VIN = 0dBm
N/W ANALYZER
RL = RS = 50⍀
–10
TA = 25ⴗC
VCC = 3.3V/2.5V
VIN = 0dBm
N/W ANALYZER:
RL = RS = 50⍀
–2
ATTENUATION (dB)
–0.4
0
0
TA = 25ⴗC
ON OFF
CL = InF
ATTENUATION (dB)
0
–0.2
ENABLE
DISABLE
1.5
–70
70
60
50
40
30
1.0
–80
20
0.5
–90
–100
0.1
1
100
10
FREQUENCY (MHz)
1000
TPC 13. Off Isolation vs. Frequency
0
–40
10
–20
0
20
40
60
TEMPERATURE (ⴗC)
80
TPC 14. Enable/Disable Time
vs. Temperature
0
0.5
0.7
0.9 1.1 1.3 1.5 1.7
DATA RATE (Gbps)
1.9
TPC 15. Jitter vs. Data Rate;
PRBS 31
EYE WIDTH (%)
100
95
VCC = 3.3V
90 V = 1.5V p-p
IN
85 20dB ATTENUATION
80
75
70
65
60
55
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) ⴛ 100%
50
0.5
0.7
0.9 1.1 1.3 1.5 1.7
DATA RATE (Gbps)
50mV/DIV
200ps/DIV
VCC = 3.3V
VIN = 1.5V p-p
20dB
ATTENUATION
TA = 25ⴗC
20mV/DIV
200ps/DIV
VCC = 2.5V
VIN = 1.5V p-p
20dB
ATTENUATION
TA = 25ⴗC
1.9
TPC 16. Eye Width vs. Data Rate;
PRBS 31
TPC 17. Eye Pattern; 1.5 Gbps,
VCC = 3.3 V, PRBS 31
–6–
TPC 18. Eye Pattern; 1.244 Gbps,
VCC = 2.5 V, PRBS 31
REV. 0
ADG3243
TIMING MEASUREMENT INFORMATION
Test Conditions
For the following load circuit and waveforms, the notation that
is used is VIN and VOUT where
VIN = VA and VOUT = VB or VIN = VB and VOUT = VA
VCC
SW1
VOUT
VIN
PULSE
GENERATOR
2 ⴛ VCC
Symbol
VCC = 3.3 V ⴞ 0.3 V
VCC = 2.5 V ⴞ 0.2 V
Unit
RL
V⌬
CL
VT
500
300
50
1.5
500
150
30
0.9
Ω
mV
pF
V
GND
RL
Table II. Switch Position
DUT
RT
CL
RL
NOTES
PULSE GENERATOR FOR ALL PULSES: tR ⱕ 2.5ns, tF ⱕ 2.5ns,
FREQUENCY ⱕ 10MHz.
CL INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO ZOUT
OF THE PULSE GENERATOR.
Test
S1
tPLZ, tPZL
tPHZ, tPZH
2 × VCC
GND
0V
tPZL
VIN = 0V
VIH
VOUT
SW1 @ 2VCC
VT
tPLH
tPLH
tPLZ
VCC
VCC
VT
VL + V⌬
VL
tPZH
tPHZ
0V
VH
VIN = VCC
VT
VOUT
VINH
VT
CONTROL INPUT BEx
Figure 1. Load Circuit
CONTROL
INPUT BEx
DISABLE
ENABLE
VOUT
SW1 @ GND
VH
VT
0V
VL
Figure 3. Enable and Disable Times
Figure 2. Propagation Delay
REV. 0
–7–
VH – V⌬
0V
ADG3243
BUS SWITCH APPLICATIONS
Mixed Voltage Operation, Level Translation
2.5 V to 1.8 V Translation
When VCC is 2.5 V and the input signal range is 0 V to VCC, the
maximum output signal will, as before, be clamped to within a
voltage threshold below the VCC supply. In this case, the output
will be limited to approximately 1.8 V, as shown in Figure 8.
Bus switches can provide an ideal solution for interfacing between
mixed voltage systems. The ADG3243 is suitable for applications where voltage translation from 3.3 V technology to a lower
voltage technology is needed. This device can translate from
2.5 V to 1.8 V or bidirectionally from 3.3 V directly to 2.5 V.
2.5V
Figure 4 shows a block diagram of a typical application in which a
user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor may not have 3.3 V tolerant inputs,
therefore placing the ADG3243 between the two devices allows
the devices to communicate easily. The bus switch directly
connects the two blocks, thus introducing minimal propagation
delay, timing skew, or noise.
ADG3243
2.5V
1.8V
Figure 7. 2.5 V to 1.8 V Voltage Translation
2.5V
3.3V
ADG3243
VOUT
3.3V ADC
2.5V SUPPLY
2.5V
MICROPROCESSOR
1.8V
SWITCH
OUTPUT
3.3V
Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
3.3 V to 2.5 V Translation
0V
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to within a voltage
threshold below the VCC supply.
Figure 8. 2.5 V to 1.8 V Voltage Translation
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3243 is designed specifically for
applications that do not need drive yet require simple logic
functions, it solves this requirement. The device isolates access
to the bus, thus minimizing capacitance loading.
2.5V
ADG3243
2.5V
2.5V
VIN
2.5V
Bus Isolation
3.3V
3.3V
SWITCH
INPUT
LOAD A
LOAD C
Figure 5. 3.3 V to 2.5 V Voltage Translation
In this case, the output will be limited to 2.5 V, as shown in
Figure 6. This device can be used for translation from 2.5 V to
3.3 V devices and also between two 3.3 V devices.
BUS/
BACKPLANE
BUS SWITCH
LOCATION
VOUT
LOAD D
Figure 9. Location of Bus Switched in a Bus
Isolation Application
3.3V SUPPLY
2.5V
Hot Plug and Hot Swap Isolation
SWITCH
OUTPUT
0V
LOAD B
SWITCH
INPUT
The ADG3243 is suitable for hot swap and hot plug applications.
The output signal of the ADG3243 is limited to a voltage that is
below the VCC supply, as shown in Figures 6 and 8. Therefore
the switch acts like a buffer to take the impact from hot insertion,
protecting vital and expensive chipsets from damage.
VIN
3.3V
Figure 6. 3.3 V to 2.5 V Voltage Translation
In hot plug applications, the system cannot be shut down when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 10 shows a typical example of this type of application.
–8–
REV. 0
RAM
ADG3243
CPU
PLUG-IN
CARD (1)
CARD I/O
ADG3243
ADG3243
PLUG-IN
CARD (2)
CARD I/O
switches. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the backplane before any other signal or power pins.
Analog Switching
Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.
BUS
Figure 10. ADG3243 in a Hot Plug Application
There are many systems, such as docking stations, PCI boards
for servers, and line cards for telecommunications switches, that
require the ability to handle hot swapping. If the bus can be
isolated prior to insertion or removal, there is more control over
the hot swap event. This isolation can be achieved using bus
REV. 0
High Impedance during Power-Up/Power-Down
To ensure the high impedance state during power-up or powerdown, BEx should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the currentsinking capability of the driver.
–9–
ADG3243
OUTLINE DIMENSIONS
8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
2.90 BSC
8
7
6
5
1
2
3
4
2.80 BSC
1.60 BSC
PIN 1
0.65 BSC
1.30
1.15
0.90
1.95
BSC
1.45 MAX
0.15 MAX
0.38
0.22
SEATING
PLANE
0.22
0.08
8ⴗ
4ⴗ
0ⴗ
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178BA
–10–
REV. 0
–11–
–12–
C04310–0–8/03(0)