TI1 DS90LV049Q Ds90lv049q automotive lvds dual line driver and receiver pair Datasheet

DS90LV049Q
DS90LV049Q Automotive LVDS Dual Line Driver and Receiver Pair
Literature Number: SNLS300C
DS90LV049Q
Automotive LVDS Dual Line Driver and Receiver Pair
General Description
Features
The DS90LV049Q is a dual CMOS flow-through differential
line driver-receiver pair designed for applications requiring ultra low power dissipation, exceptional noise immunity, and
high data throughput. The device is designed to support data
rates in excess of 400 Mbps utilizing Low Voltage Differential
Signaling (LVDS) technology.
The DS90LV049Q drivers accept LVTTL/LVCMOS signals
and translate them to LVDS signals. The receivers accept
LVDS signals and translate them to 3 V CMOS signals. The
LVDS input buffers have internal failsafe biasing that places
the outputs to a known H (high) state for floating receiver inputs. In addition, the DS90LV049Q supports a TRI-STATE
function for a low idle power state when the device is not in
use.
The EN and EN inputs are ANDed together and control the
TRI-STATE outputs. The enables are common to all four
gates.
■
■
■
■
■
■
■
■
■
■
■
■
Connection Diagram
Functional Diagram
AECQ-100 Grade 1
Up to 400 Mbps switching rates
Flow-through pinout simplifies PCB layout
50 ps typical driver channel-to-channel skew
50 ps typical receiver channel-to-channel skew
3.3 V single power supply design
TRI-STATE output control
Internal fail-safe biasing of receiver inputs
Low power dissipation (70 mW at 3.3 V static)
High impedance on LVDS outputs on power down
Conforms to TIA/EIA-644-A LVDS Standard
Available in low profile 16 pin TSSOP package
Dual-In-Line
30064201
Order Number DS90LV049QMT
Order Number DS90LV049QMTX (Tape and Reel)
See NS Package Number MTC16
30064202
Truth Table
EN
EN
LVDS Out
LVCMOS Out
L or Open
L or Open
OFF
OFF
H
L or Open
ON
ON
L or Open
H
OFF
OFF
H
H
OFF
OFF
© 2008 National Semiconductor Corporation
300642
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DS90LV049Q Automotive LVDS Dual Line Driver and Receiver Pair
December 1, 2008
DS90LV049Q
Maximum Package Power Dissipation @ +25°C
MT Package
1146 mW
Derate MT Package
10.4 mW/°C above +25°C
Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
LVCMOS Input Voltage (DIN)
LVDS Input Voltage (RIN+, RIN-)
Enable Input Voltage (EN, EN)
LVCMOS Output Voltage (ROUT)
LVDS Output Voltage
(DOUT+, DOUT-)
LVCMOS Output Short Circuit
Current (ROUT)
LVDS Output Short Circuit
Current (DOUT+, DOUT−)
LVDS Output Short Circuit
Current Duration(DOUT+, DOUT−)
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
Maximum Junction Temperature
θJA
−0.3 V to +4 V
−0.3 V to (VDD + 0.3 V)
96.0°C/W
θJC
ESD Rating
HBM (Note 1)
−0.3 V to +3.9 V
−0.3 V to (VDD + 0.3 V)
−0.3 V to (VDD + 0.3 V)
30.0°C/W
≥ 8 kV
≥ 250 V
≥ 1250 V
MM (Note 2)
CDM (Note 3)
−0.3 V to +3.9 V
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
100 mA
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
24 mA
Recommended Operating
Conditions
Continuous
−65°C to +150°C
Supply Voltage (VDD)
Operating Free Air
Temperature (TA)
+260°C
+135°C
Min
+3.0
Typ
+3.3
Max
+3.6
Units
V
−40
+25
+125
°C
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 5, 7, 9)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
LVCMOS Input DC Specifications (Driver Inputs, ENABLE Pins)
VIH
Input High Voltage
2.0
VDD
V
VIL
Input Low Voltage
GND
0.8
V
IIH
Input High Current
VIN = VDD
IIL
Input Low Current
VIN = GND
VCL
Input Clamp Voltage
ICL = −18 mA
DIN
EN
EN
−10
1
+10
μA
−10
−0.1
+10
μA
−1.5
−0.6
250
350
450
mV
1
35
|mV|
1.23
1.375
V
1
25
|mV|
−5.8
−9.0
mA
−5.8
−9.0
mA
V
LVDS Output DC Specifications (Driver Outputs)
| VOD |
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for
Complementary Output States
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for
Complementary Output States
IOS
Output Short Circuit Current (Note
17)
IOSD
Differential Output Short Circuit
Current (Note 17)
IOFF
Power-off Leakage
VOUT = 0 V or 3.6 V
VDD = 0 V or Open
−20
±1
+20
μA
IOZ
Output TRI-STATE Current
EN = 0 V and EN = VDD
VOUT = 0 V or VDD
−10
±1
+10
μA
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RL = 100 Ω
(Figure 1)
1.125
ENABLED,
DIN = VDD, DOUT+ = 0 V or
DIN = GND, DOUT− = 0 V
DOUT−
DOUT+
ENABLED, VOD = 0 V
2
Parameter
Conditions
Pin
Min
Typ
Max
Units
−15
35
mV
LVDS Input DC Specifications (Receiver Inputs)
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VCMR
Common-Mode Voltage Range
VID = 100 mV, VDD=3.3 V
IIN
Input Current
VDD=3.6 V
VIN =0 V or 2.8 V
VCM = 1.2 V, 0.05 V, 2.35 V
-100
−15
0.05
RIN+
RIN-
VDD=0 V
VIN =0 V or 2.8 V or 3.6 V
mV
3
V
−12
±4
+12
μA
−10
±1
+10
μA
LVCMOS Output DC Specifications (Receiver Outputs)
VOH
Output High Voltage
IOH = -0.4 mA, VID= 200 mV
VOL
Output Low Voltage
IOL = 2 mA, VID = 200 mV
IOZ
Output TRI-STATE Current
Disabled, VOUT =0 V or VDD
2.7
ROUT
-10
3.3
V
0.05
0.25
V
±1
+10
μA
21
35
mA
15
25
mA
Typ
Max
Units
General DC Specifications
IDD
Power Supply Current (Note 6)
EN = 3.3 V
IDDZ
TRI-State Supply Current
EN = 0 V
VDD
Switching Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 7, 16)
Symbol
Parameter
Conditions
Min
LVDS Outputs (Driver Outputs)
tPHLD
Differential Propagation Delay High to Low
0.7
2
ns
tPLHD
Differential Propagation Delay Low to High
0.7
2
ns
tSKD1
Differential Pulse Skew |tPHLD − tPLHD|
(Notes 8, 10)
0
0.05
0.4
ns
0
0.05
0.5
ns
RL = 100 Ω
(Figure 2 and Figure 3)
tSKD2
Differential Channel-to-Channel Skew
(Notes 8, 11)
tSKD3
Differential Part-to-Part Skew (Notes 8, 12)
1.0
ns
tTLH
Rise Time (Note 8)
0.2
0.4
1
ns
tTHL
Fall Time (Note 8)
0.2
0.4
1
ns
tPHZ
Disable Time High to Z
1.5
3
ns
tPLZ
Disable Time Low to Z
1.5
3
ns
tPZH
Enable Time Z to High
3
6
ns
tPZL
Enable Time Z to Low
3
6
fMAX
Maximum Operating Frequency (Note 19)
0
RL = 100 Ω
(Figure 4 and Figure 5)
1
1
250
ns
MHz
LVCMOS Outputs (Receiver Outputs)
tPHL
Propagation Delay High to Low
0.5
tPLH
Propagation Delay Low to High
tSK1
Pulse Skew |tPHL − tPLH| (Note 13)
tSK2
Channel-to-Channel Skew (Note 14)
tSK3
Part-to-Part Skew (Note 15)
tTLH
Rise Time(Note 8)
0.3
tTHL
Fall Time(Note 8)
0.3
tPHZ
Disable Time High to Z
3
tPLZ
Disable Time Low to Z
3
tPZH
Enable Time Z to High
tPZL
Enable Time Z to Low
fMAX
Maximum Operating Frequency (Note 20)
(Figure 6 and Figure 7)
2
3.5
ns
0.5
2
3.5
ns
0
0.05
0.4
ns
0
0.05
0.5
ns
1.0
ns
0.9
1.4
ns
0.75
1.4
ns
5.6
8
ns
5.4
8
ns
2.5
4.6
7
ns
2.5
4.6
7
ns
0
(Figure 8 and Figure 9)
250
MHz
Note 4: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
3
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DS90LV049Q
Symbol
DS90LV049Q
Note 5: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VTH, VTL,
VOD and ΔVOD.
Note 6: Both, driver and receiver inputs are static. All LVDS outputs have 100 Ω load. All LVCMOS outputs are floating. None of the outputs have any lumped
capacitive load.
Note 7: All typical values are given for: VDD = +3.3 V, TA = +25°C.
Note 8: These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage,
temperature) ranges.
Note 9: The DS90LV049Q drivers are current mode devices and only function within datasheet specifications when a resistive load is applied to their outputs.
The typical range of the resistor values is 90 Ω to 110 Ω.
Note 10: tSKD1 or differential pulse skew is defined as |tPHLD − tPLHD|. It is the magnitude difference in the differential propagation delays between the positive
going edge and the negative going edge of the same driver channel.
Note 11: tSKD2 or differential channel-to-channel skew is defined as the magnitude difference in the differential propagation delays between two driver channels
on the same device.
Note 12: tSKD3 or differential part-to-part skew is defined as |tPLHD Max − tPLHD Min| or |tPHLD Max − tPHLD Min|. It is the difference between the minimum and maximum
specified differential propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature
range.
Note 13: tSK1 or pulse skew is defined as |tPHL − tPLH|. It is the magnitude difference in the propagation delays between the positive going edge and the negative
going edge of the same receiver channel.
Note 14: tSK2 or channel-to-channel skew is defined as the magnitude difference in the propagation delays between two receiver channels on the same device.
Note 15: tSK3 or part-to-part skew is defined as |tPLH Max − tPLH Min| or |tPHL Max − tPHL Min|. It is the difference between the minimum and maximum specified
propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
Note 16: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
Note 17: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Note 18: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
Note 19: fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45%/55%, VOD > 250 mV, all channels
switching.
Note 20: fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, VID = 200 mV, VCM = 1.2 V . Output Criteria: duty cycle = 45%/55%, VOH >
2.7 V, VOL < 0.25 V, all channels switching.
Parameter Measurement Information
30064203
FIGURE 1. Driver VOD and VOS Test Circuit
30064204
FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit
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4
DS90LV049Q
30064205
FIGURE 3. Driver Propagation Delay and Transition Time Waveforms
30064206
FIGURE 4. Driver TRI-STATE Delay Test Circuit
5
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DS90LV049Q
30064207
FIGURE 5. Driver TRI-STATE Delay Waveform
30064209
FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit
30064210
FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms
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6
DS90LV049Q
30064211
FIGURE 8. Receiver TRI-STATE Delay Test Circuit
30064214
FIGURE 9. Receiver TRI-STATE Delay Waveforms
Typical Application
30064208
FIGURE 10. Point-to-Point Application
7
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DS90LV049Q
field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more
likely to appear as common-mode which is rejected by the
receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase difference
between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note
the velocity of propagation, v = c/Er where c (the speed of
light) = 0.2997 mm/ps or 0.0118 in/ps). Do not rely solely on
the autoroute function for differential traces. Carefully review
dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias
and other discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use
arcs or 45° bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allowable.
Applications Information
General application guidelines and hints for LVDS drivers and
receivers may be found in the following application notes:
LVDS Owner's Manual (lit #550062-003), AN-805, AN-808,
AN-903, AN-916, AN-971, AN-977.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 10. This configuration provides a clean signaling
environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically, the characteristic differential
impedance of the media is in the range of 100 Ω. A termination
resistor of 100 Ω (selected to match the media), and is located
as close to the receiver input pins as possible. The termination
resistor converts the driver output current (current mode) into
a voltage that is detected by the receiver. Other configurations
are possible such as a multi-receiver configuration, but the
effects of a mid-stream connector(s), cable stub(s), and other
impedance discontinuities as well as ground shifting, noise
margin limits, and total termination loading must be taken into
account.
The TRI-STATE function allows the device outputs to be disabled, thus obtaining an even lower power state when the
transmission of data is not required.
The DS90LV049Q has a flow-through pinout that allows for
easy PCB layout. The LVDS signals on one side of the device
easily allows for matching electrical lengths of the differential
pair trace lines between the driver and the receiver as well as
allowing the trace lines to be close together to couple noise
as common-mode. Noise isolation is achieved with the LVDS
signals on one side of the device and the TTL signals on the
other side.
TERMINATION
Use a termination resistor which best matches the differential
impedance or your transmission line. The resistor should be
between 90 Ω and 130 Ω. Remember that the current mode
outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination.
Typically, connecting a single resistor across the pair at the
receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be < 10 mm
(12 mm MAX).
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1 μF and
0.001 μF capacitors in parallel at the power supply pin with
the smallest value capacitor closest to the device supply pin.
Additional scattered capacitors over the printed circuit board
will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10 μF
(35 V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground.
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100 kΩ), low capacitance
(< 2 pF) scope probes with a wide bandwidth (1 GHz) scope.
Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important
to remember:
Use controlled impedance media. The cables and connectors
you use should have a matched differential impedance of
about 100 Ω. They should not introduce major impedance
discontinuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate
less EMI due to field canceling effects and also tend to pick
up electromagnetic radiation a common-mode (not differential
mode) noise which is rejected by the receiver.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); LVDS signals,
ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
may couple onto the LVDS lines. It is best to put TTL and
LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
FAIL-SAFE FEATURE
An LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20 mV) to CMOS logic levels.
Due to the high gain and tight threshold of the receiver, care
should be taken to prevent noise from appearing as a valid
signal.
The receiver's internal fail-safe circuitry is designed to source/
sink a small amount of current, providing fail-safe protection
(a stable known state of HIGH output voltage) for floating receiver inputs.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential
impedance of your transmission medium (i.e. cable) and termination resistor. Run the differential pair trace lines as close
together as possible as soon as they leave the IC (stubs
should be < 10 mm long). This will help eliminate reflections
and ensure noise is coupled as common-mode. In fact, we
have seen that differential signals which are 1 mm apart radiate far less noise than traces 3 mm apart since magnetic
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8
of higher noise levels. The pull up and pull down resistors
should be in the 5 kΩ to 15 kΩ range to minimize loading and
waveform distortion to the driver. The common-mode bias
point should be set to approximately 1.2 V (less than 1.75 V)
to be compatible with the internal circuitry.
For more information on failsfe biasing of LVDS interfaces
please refer to AN-1194.
Pin Descriptions
Pin No.
Name
Description
10, 11
DIN
Driver input pins, LVCMOS levels. There is a pull-down current source
present.
6, 7
DOUT+
Non-inverting driver output pins, LVDS levels.
5, 8
DOUT−
Inverting driver output pins, LVDS levels.
2, 3
RIN+
Non-inverting receiver input pins, LVDS levels. There is a pull-up current
source present.
1, 4
RIN-
Inverting receiver input pins, LVDS levels. There is a pull-down current
source present.
14, 15
ROUT
Receiver output pins, LVCMOS levels.
9, 16
EN, EN
Enable and Disable pins. There are pull-down current sources present
at both pins.
12
VDD
Power supply pin.
13
GND
Ground pin.
Typical Performance Curves
Differential Output Voltage
vs Load Resistor
Power Supply Current
vs Frequency
30064221
30064219
9
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DS90LV049Q
The DS90LV049Q has two receivers, and if an application
requires a single receiver, the unused receiver inputs should
be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value
pull up and pull down current sources to set the output to a
HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs.
External lower value pull up and pull down resistors (for a
stronger bias) may be used to boost fail-safe in the presence
DS90LV049Q
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead (0.100″ Wide) Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90LV049QMT
Order Number DS90LV049QMTX (Tape and Reel)
NS Package Number MTC16
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10
DS90LV049Q
Notes
11
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DS90LV049Q Automotive LVDS Dual Line Driver and Receiver Pair
Notes
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