HUF76143P3, HUF76143S3S
Data Sheet
75A, 30V, 0.0055 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable
and battery-operated products.
January 2003
Features
• Logic Level Gate Drive
• 75A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.0055Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER© Mode
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA76143.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER
PACKAGE
D
BRAND
HUF76143P3
TO-220AB
76143P
HUF76143S3S
TO-263AB
76143S
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF76143S3ST.
S
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
©2003 Fairchild Semiconductor Corporation
GATE
DRAIN
(FLANGE)
SOURCE
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
30
V
Drain to Gate Voltage (R GS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
30
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
75
75
75
Figure 4
A
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Figure 6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
225
1.8
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-40 to 150
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, V GS = 0V (Figure 12)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 75A, VGS = 10V (Figures 9, 10)
-
0.0052
0.0055
Ω
ID = 75A, VGS = 5V (Figure 9)
-
0.0063
0.0075
Ω
ID = 75A, VGS = 4.5V (Figure 9)
-
0.0068
0.0085
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
(Figure 3)
-
-
0.55
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-220 and TO-263
-
-
62
oC/W
VDD = 15V, ID ≅ 75A,
RL = 0.2Ω, VGS = 4.5V,
RGS = 2.5Ω
-
-
250
ns
-
22
-
ns
tr
-
145
-
ns
td(OFF)
-
30
-
ns
tf
-
18
-
ns
tOFF
-
-
72
ns
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
©2003 Fairchild Semiconductor Corporation
tON
td(ON)
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
Electrical Specifications
TC = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
105
ns
-
14
-
ns
-
55
-
ns
td(OFF)
-
40
-
ns
tf
-
18
-
ns
tOFF
-
-
87
ns
-
95
114
nC
-
50
60
nC
-
3.8
4.6
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 15V, ID ≅ 75A,
RL = 0.2Ω, VGS = 10V,
RGS = 2.5Ω
(Figures 16, 21, 20)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 15V,
ID ≅ 75A,
RL = 0.2Ω
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
Gate to Source Gate Charge
Qgs
-
11.70
-
nC
Gate to Drain “Miller” Charge
Qgd
-
22.00
-
nC
-
3900
-
pF
-
1600
-
pF
-
270
-
pF
MIN
TYP
MAX
UNITS
ISD = 75A
-
-
1.25
V
trr
ISD = 75A, dISD/dt = 100A/µs
-
-
90
ns
QRR
ISD = 75A, dISD/dt = 100A/µs
-
-
170
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
TEST CONDITIONS
Typical Performance Curves
80
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
60
VGS = 10V
40
VGS = 4.5V
20
0.2
10
0
0
25
50
75
100
125
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
©2003 Fairchild Semiconductor Corporation
150
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
Typical Performance Curves
(Continued)
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10 -4
10-3
10-2
10 -1
t, RECTANGULAR PULSE DURATION (s)
10 0
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
2000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
1000
150 - TC
125
I = I25
VGS = 5V
VGS = 10V
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
500
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
100µs
100
1ms
10
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
BVDSS MAX = 30V
1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
©2003 Fairchild Semiconductor Corporation
100
IAS, AVALANCHE CURRENT (A)
1000
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
STARTING TJ = 25oC
STARTING TJ = 150oC
10
0.001
0.01
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
100
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
Typical Performance Curves
200
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
ID, DRAIN CURRENT (A)
I D, DRAIN CURRENT (A)
200
(Continued)
150
100
150oC
50
25oC
VGS = 10V
VGS = 5V
150
VGS = 4V
VGS = 3.5V
100
VGS = 3V
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
-40oC
0
0
0
1
2
3
4
5
0
1
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
1.6
15
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 75A
ID = 50A
2
9
6
ID = 25A
1.4
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 75A
1.2
1.0
0.8
0.7
3
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
-60
10
0
60
120
180
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. SOURCE TO DRAIN ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
VGS = VDS, I D = 250µA
1.0
0.8
0.6
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
NORMALIZED GATE
THRESHOLD VOLTAGE
5
ID = 250µA
1.1
1.0
0.9
0.5
-60
0
60
120
180
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2003 Fairchild Semiconductor Corporation
-60
0
60
120
180
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
Typical Performance Curves
(Continued)
10
4000
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
5000
CISS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + C GD
3000
2000
COSS
1000
CRSS
8
6
4
2
VDD = 15V
WAVEFORMS IN
DESCENDING ORDER:
ID = 75A
ID = 50A
ID = 25A
0
0
0
5
10
15
20
25
VDS , DRAIN TO SOURCE VOLTAGE (V)
0
30
20
40
60
Qg, GATE CHARGE (nC)
80
100
NOTE: Refer to Fairchild Application Notes 7254 and 7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
800
800
VGS = 10V, VDD = 15V, ID = 75A, R L = 0.2Ω
600
tr
td(OFF)
400
600
SWITCHING TIME (ns)
SWITCHING TIME (ns)
VGS = 4.5V, VDD = 15V, ID = 75A, RL = 0.2Ω
tf
200
td(OFF)
400
tf
tr
200
td(ON)
td(ON)
0
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
0
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
©2003 Fairchild Semiconductor Corporation
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
IgREF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
©2003 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
PSPICE Electrical Model
SUBCKT HUF76143 2 1 3 ;
REV March 1998
CA 12 8 5.2e-9
CB 15 14 5e-9
CIN 6 8 3.65e-9
LDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DPLCAP
10
RLDRAIN
RSLC1
51
DBREAK
+
EBREAK 11 7 17 18 39.38
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RSLC2
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
IT 8 17 1
LGATE
GATE
1
+
17
EBREAK 18
50
ESG
LDRAIN 2 5 1e-9
LGATE 1 9 2.6e-9
LSOURCE 3 7 1.1e-9
DRAIN
2
5
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.5e-3
RGATE 9 20 0.92
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
12
S2A
13
8
14
13
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
-
IT
14
+
+
EGS
19
VBAT
5
8
EDS
-
+
8
22
S1A
S1B
S2A
S2B
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*425),4))}
.MODEL DBODYMOD D (IS = 1.2e-11 RS = 2.65e-3 TRS1 = 2.3e-3 TRS2 = -4.2e-6 CJO = 5.45e-9 TT = 3.9e-8 XTI = 4.3 N = 1.03 M = 0.43)
.MODEL DBREAKMOD D (RS = 8.5e-2 TRS1 =0 TRS2 =0)
.MODEL DPLCAPMOD D (CJO = 2.6e-9 IS = 1e-30 N = 10 M = 0.7)
.MODEL MMEDMOD NMOS (VTO = 1.9 KP = 10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.92)
.MODEL MSTROMOD NMOS (VTO = 2.26KP = 215 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.62 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 9.2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.8e-4 TC2 = -4e-7)
.MODEL RDRAINMOD RES (TC1 = 1e-2 TC2 = 0)
.MODEL RSLCMOD RES (TC1 = 3e-3 TC2 = -2e-5)
.MODEL RSOURCEMOD RES (TC1 = 5e-4 TC2 = 1.1e-5)
.MODEL RVTHRESMOD RES (TC = -2.2e-3 TC2 = -6e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.45e-3 TC2 = -2e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -5 VOFF= -2)
VON = -2 VOFF= -5)
VON = -1.5 VOFF= 1)
VON = 1 VOFF= -1.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
SABER Electrical Model
REV March 1998
template huf76143 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 1.2e-11, xti = 4.3, cjo = 5.45e-9, tt = 3.9e-8, n = 1.03, m = 0.43)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.6e-9, is = 1e-30, n = 10, m = 0.70)
m..model mmedmod = (type=_n, vto = 1.9, kp = 10, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.26, kp = 215, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.62, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -2)
DPLCAP
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2, voff = -5)
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = 1)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 1, voff = -1.5)
c.ca n12 n8 = 5.2e-9
c.cb n15 n14 = 5e-9
c.cin n6 n8 = 3.65e-9
DRAIN
2
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
72
ISCL
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
EVTEMP
RGATE + 18 22
9
20
MWEAK
MSTRO
CIN
DBODY
EBREAK
+
17
18
MMED
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
71
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 9.8e-4, tc2 = -4e-7
res.rdbody n71 n5 = 2.65e-3, tc1 = 2.3e-3, tc2 = -4.2e-6
res.rdbreak n72 n5 = 8.5e-2, tc1 = 0, tc2 = 0
res.rdrain n50 n16 = 1.5e-3, tc1 = 1e-2, tc2 = 0
res.rgate n9 n20 = 0.92
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51 = 1e-6, tc1 = 3e-3, tc2 = -2e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3e-3, tc1 = 5e-4, tc2 = 1.1e-5
res.rvtemp n18 n19 = 1, tc1 = -1.45e-3, tc2 = -2e-6
res.rvthres n22 n8 = 1, tc1 = -2.2e-3, tc2 = -6e-6
21
RDBODY
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.6e-9
l.lsource n3 n7 = 1.1e-9
LDRAIN
5
-
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
13
8
S2A
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 39.38
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/425))** 4))
}
}
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
SPICE Thermal Model
th
JUNCTION
REV March 1998
HUF76143
CTHERM1 th 6 5.0e-3
CTHERM2 6 5 1.2e-2
CTHERM3 5 4 2.0e-2
CTHERM4 4 3 2.8e-2
CTHERM5 3 2 2e-1
CTHERM6 2 tl 3
RTHERM1
RTHERM1 th 6 2.0e-3
RTHERM2 6 5 2.0e-2
RTHERM3 5 4 6.9e-2
RTHERM4 4 3 1.3e-1
RTHERM5 3 2 7.5e-2
RTHERM6 2 tl 3.0e-2
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
Saber thermal model HUF76143
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 5.0e-3
ctherm.ctherm2 6 5 = 1.2e-2
ctherm.ctherm3 5 4 = 2.0e-2
ctherm.ctherm4 4 3 = 2.8e-2
ctherm.ctherm5 3 2 = 2.0e-1
ctherm.ctherm6 2 tl = 3
rtherm.rtherm1 th 6 = 2.0e-3
rtherm.rtherm2 6 5 = 2.0e-2
rtherm.rtherm3 5 4 = 6.9e-2
rtherm.rtherm4 4 3 = 1.3e-1
rtherm.rtherm5 3 2 = 7.5e-2
rtherm.rtherm6 2 tl = 3.0e-2
}
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2003 Fairchild Semiconductor Corporation
CASE
HUF76143P3, HUF76143S3S Rev. B1
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Rev. I2