NCP81063 Product Preview Synchronous Buck MOSFET Drivers The NCP81063 is a high−performance dual MOSFET gate driver in a small 3 mm x 3 mm package, optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. A zero−current detection feature allows for a high−efficiency solution even at light load conditions. VCC UVLO ensures the MOSFETs are off when supply voltages are low. A bi−directional Enable pin provides a fault signal to the controller when a UVLO fault is detected. • • • • • • • 1 DFN8 MN SUFFIX CASE 506BJ MARKING DIAGRAM Features • • • • • www.onsemi.com Space−efficient 3 mm x 3 mm DFN8 Thermally−enhanced Package VCC Range of 4.5 V to 13.2 V Integrated Bootstrap Diode 5 V 3−stage PWM input Zero Current Detect Function Provides Power Saving Operation During Light Load Conditions Bi−directional Enable Feature Pulls Enable Pin Low During a UVLO Fault Output Disable Control Turns Off Both MOSFETs VCC Undervoltage Lockout Adaptive Anti−cross Conduction Circuit Protects Against Cross−conduction During FET Turn−on and Turn−off Direct Interface to NCP6151 and Other Compatible PWM Controllers Thermally Enhanced Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • Power Solutions for Notebook and Desktop Systems 1 81063 ALYWG G 81063 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NCP81063MNTXG Package Shipping† DFN8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2016 June, 2016 − Rev. P1 1 Publication Order Number: NCP81063/D NCP81063 BST DRVH 1 PWM SW FLAG 9 EN GND VCC DRVL (Top View) Figure 1. Pin Diagram BST VCC DRVH PWM Logic SW Anti−Cross Conduction VCC DRVL EN Fault ZCD Detection UVLO Pre−OV Figure 2. Block Diagram Table 1. Pin Descriptions Pin No. Symbol Description 1 BST Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and the SW pin. 2 PWM Control input: PWM = High → DRVH is high, DRVL is low. PWM = Mid → Zero current detect enabled. Diode emulation mode. PWM = Low → DRVH is low, DRVL is high. 3 EN 4 VCC Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground. 5 DRVL Low side gate drive output. Connect to the gate of low side MOSFET. 6 GND Bias and reference ground. All signals are referenced to this node (QFN Flag). 3−state input: EN = High → Driver is enabled. EN = Low → Driver is disabled. 7 SW 8 DRVH Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET. High side gate drive output. Connect to the gate of high side MOSFET. 9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to ground plane. www.onsemi.com 2 NCP81063 12V_POWER TP1 R164 R1 1.02 C4 TP2 0.0 R143 NCP81063 TP3 0.0 TP4 PWM BST HG PWM SW DRON EN LG C1 4.7uF C2 4.7uF + CE9 390uF 0.0 VREG_SW1_HG TP5 VCCP L VREG_SW1_OUT 235nH TP6 TP7 Q9 NTMFS4851N VREG_SW1_LG Q10 NTMFS4851N R3 2.2 JP13_ETCH CSN11 PAD TP8 C5 1uF C3 4.7uF R142 GND VCC Q1 NTMFS4821N 0.027uF C6 2700pF JP14_ETCH CSP11 Figure 3. Application Circuit Table 2. ABSOLUTE MAXIMUM RATINGS Pin Symbol Pin Name VMAX VMIN VCC Main Supply Voltage Input 15 V −0.3 V BST Bootstrap Supply Voltage 35 V wrt/ GND 40 V ≤ 50 ns wrt/ GND 15 V wrt/ SW −0.3 V wrt/SW SW Switching Node (Bootstrap Supply Return) 35 V 40 V ≤ 50 ns −5 V −10 V (200 ns) DRVH High Side Driver Output BST+0.3 V −0.3 V wrt/SW −2 V (<200 ns) wrt/SW DRVL Low Side Driver Output VCC+0.3 V −0.3 V DC −5 V (<200 ns) PWM DRVH and DRVL Control Input 6.5 V −0.3 V EN Enable Pin 6.5 V −0.3 V GND Ground 0V 0V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 3. THERMAL INFORMATION (All signals referenced to AGND unless noted otherwise) Symbol RqJA Parameter Thermal Characteristic (Note 1) Value Unit 74 °C/W TJ Operating Junction Temperature Range −400 to 125 °C TA Operating Ambient Temperature Range −10 to +125 °C TSTG Maximum Storage Temperature Range −55 to +150 °C MSL Moisture Sensitivity Level 1 * The maximum package power dissipation must be observed. 1. I in2 Cu, 1 oz thickness. www.onsemi.com 3 NCP81063 Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −10°C < TA < +125°C; 4.5 V < VCC < 13.2 V, 4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V) Parameter Test Conditions Min. Typ. Max. Units 13.2 V SUPPLY VOLTAGE 4.5 VCC Operation Voltage UNDERVOLTAGE LOCKOUT VCC Start Threshold 3.8 4.35 4.5 V VCC UVLO Hysteresis 150 200 250 mV SUPPLY CURRENT Normal Mode Icc + Ibst, EN = 5 V, PWM = OSC, Fsw = 100 KHz, Cload = 3 nF for DRVH, 3 nF for DRVL 10 mA Standby Current Icc + Ibst, EN = GND 0.5 Standby Current ICC + IBST, EN = HIGH, PWM = LOW, No loading on DRVH & DRVL 2.0 mA Standby Current ICC + IBST, EN = HIGH, PWM = HIGH, No loading on DRVH & DRVL 2.0 mA 1.4 mA BOOTSTRAP DIODE Forward Voltage VCC = 12 V, forward bias current = 2 mA 0.1 0.4 0.6 V PWM INPUT PWM Input High 3.4 PWM Mid−State 1.3 V PWM Input Low ZCD Blanking Timer 2.7 V 0.7 V 250 ns HIGH SIDE DRIVER (VCC = 12 V) Output Impedance, Sourcing Current VBST − VSW = 12 V 1.9 3.0 W Output Impedance, Sinking Current VBST − VSW = 12 V 1.0 1.7 W DRVH Rise Time trDRVH VVCC = 12 V, 3 nF load, VBST−VSW = 12 V 16 30 ns DRVH Fall Time tfDRVH VVCC = 12 V, 3 nF load, VBST−VSW = 12 V 11 25 ns DRVH Turn−Off Propagation Delay tpdlDRVH CLOAD = 3 nF 30 ns DRVH Turn−On Propagation Delay tpdhDRVH CLOAD = 3 nF 30 ns SW Pull Down Resistance SW to PGND 37.5 kW DRVH Pull Down Resistance DRVH to SW, BST−SW = 0 V 37.55 kW W 8.0 HIGH SIDE DRIVER (VCC = 5 V) Output Impedance, Sourcing Current VBST − VSW = 5 V 2.5 Output Impedance, Sinking Current VBST − VSW = 5 V 1.6 W DRVH Rise Time trDRVH VVCC = 5 V, 3 nF load, VBST − VSW = 5 V 30 ns DRVH Fall Time tfDRVH VVCC = 5 V, 3 nF load, VBST − VSW = 5 V 27 ns DRVH Turn−Off Propagation Delay tpdlDRVH CLOAD = 3 nF 20 ns DRVH Turn−On Propagation Delay tpdhDRVH CLOAD = 3 nF 27 ns SW Pull Down Resistance SW to PGND 37.5 kW DRVH Pull Down Resistance DRVH to SW, BST−SW = 0 V 37.5 kW LOW SIDE DRIVER (VCC = 12 V) Output Impedance, Sourcing Current 2.0 www.onsemi.com 4 3.0 W NCP81063 Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −10°C < TA < +125°C; 4.5 V < VCC < 13.2 V, 4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V) Parameter Test Conditions Min. Typ. Max. Units 0.7 1.5 W LOW SIDE DRIVER (VCC = 12 V) Output Impedance, Sinking Current DRVL Rise Time trDRVL CLOAD = 3 nF 16 35 ns DRVL Fall Time tfDRVL CLOAD = 3 nF 11 20 ns DRVL Turn−Off Propagation Delay tpdlDRVL CLOAD = 3 nF 35 ns DRVL Turn−On Propagation Delay tpdhDRVL CLOAD = 3 nF 30 ns DRVL Pull Down Resistance DRVL to PGND, VCC = PGND 8.0 37.5 kW 2.5 W LOW SIDE DRIVER (VCC = 5 V) Output Impedance, Sourcing Current 1.0 W DRVL Rise Time trDRVL CLOAD = 3 nF 30 ns DRVL Fall Time tfDRVL CLOAD = 3 nF 22 ns DRVL Turn−Off Propagation Delay tpdlDRVL CLOAD = 3 nF 27 ns DRVL Turn−On Propagation Delay tpdhDRVL CLOAD = 3 nF 12 ns DRVL Pull Down Resistance DRVL to PGND, VCC = PGND 37.5 kW Output Impedance, Sinking Current EN INPUT Input Voltage High 2.0 V Input Voltage Low 1.0 Hysteresis V 500 Normal Mode Bias Current −1 Enable Pin Sink Current 4 Propagation Delay Time 20 mV 1 mA 30 mA 40 ns 20 mA SW Node SW Node Leakage Current Zero Cross Detection Threshold Voltage SW to −20 mV, ramp slowly until BG goes off (Start in DCM mode) (Note 2) −3 mV Table 5. DECODER TRUTH TABLE PWM INPUT ZCD DRVL DRVH PWM High ZCD Reset Low High PWM Mid Positive current through the inductor High Low PWM Mid Zero current through the inductor Low Low PWM Low ZCD Reset High Low 2. Guaranteed by design; not production tested. www.onsemi.com 5 NCP81063 1V 1V Figure 4. PWM DRVH−SW DRVL IL Figure 5. Timing Diagram www.onsemi.com 6 NCP81063 APPLICATIONS INFORMATION The NCP81063 gate driver is a single−phase MOSFET driver designed for driving N−channel MOSFETs in a synchronous buck converter topology. controller is alerted when the driver encounters a fault condition. Low−Side Driver Switching PWM between logic−high and logic−low states will allow the driver to operate in continuous conduction mode as long as VCC is greater than the UVLO threshold and EN is high. The threshold limits are specified in the electrical characteristics table in this datasheet. Refer to Figure 21 for the gate timing diagrams and Table 1 for the EN/PWM logic table. When PWM is set above PWMHI, DRVL will first turn off after a propagation delay of tpdlDRVL. To ensure non−overlap between DRVL and DRVH, there is a delay of tpdhDRVH from the time DRVL falls to 1 V, before DRVH is allowed to turn on. When PWM falls below PWMLO, DRVH will first turn off after a propagation delay of tpdlDRVH. To ensure non−overlap between DRVH and DRVL, there is a delay of tpdhDRVL from the time DRVH – SW falls to 1 V, before DRVL is allowed to turn on. When PWM enters the mid−state voltage range, PWMMID, DRVL goes high after the non−overlap delay, and stays high for the duration of the ZCD blanking timer and an 80 ns de−bounce timer. Once these timers expire, SW is monitored for zero current detection and pulls DRVL low once zero current is detected. Three−State PWM Input The low−side driver is designed to drive a ground−referenced low−RDS(on) N−channel MOSFET. The voltage supply for the low−side driver is internally connected to the VCC and GND pins. High−Side Driver The high−side driver is designed to drive a floating low−RDS(on) N−channel MOSFET. The gate voltage for the high−side driver is developed by a bootstrap circuit referenced to the SW pin. The bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor. When the NCP81063 is starting up, the SW pin is held at ground, allowing the bootstrap capacitor to charge up to VCC through the bootstrap diode. When the PWM input is driven high, the high−side driver will turn on the high−side MOSFET using the stored charge of the bootstrap capacitor. As the high−side MOSFET turns on, the SW pin rises. When the high−side MOSFET is fully turned on, SW will settle to VIN and BST will settle to VIN + VCC (excluding parasitic ringing). Bootstrap Circuit Thermal Considerations The bootstrap circuit relies on an external charge storage capacitor (CBST) and an integrated diode to provide current to the high−side driver. A multi−layer ceramic capacitor (MLCC) with a value greater than 100 nF should be used for CBST. As power in the NCP81063 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. When the NCP81063 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power applications. The maximum dissipation the NCP81063 can handle is given by: Power Supply Decoupling The NCP81063 can source and sink relatively large currents to the gate pins of the MOSFETs. In order to maintain a constant and stable supply voltage, a low−ESR capacitor should be placed near the VCC and GND pins. A MLCC between 1 mF and 4.7 mF is typically used. Undervoltage Lockout PD(MAX) + DRVH and DRVL are low until VCC reaches the VCC UVLO threshold, typically 4.35 V. Once VCC reaches this threshold, the PWM signal will control DRVH and DRVL. There is a 200 mV hysteresis on VCC UVLO. There are pull−down resistors on DRVH, DRVL and SW to prevent the gates of the MOSFETs from accumulating enough charge to turn on when the driver is powered off. ƪT J(MAX) * T Aƫ (eq. 1) R qJA Since TJ is not recommended to exceed 150°C, the NCP81063, soldered on to a 645 mm2 copper area, using 1 oz. copper and FR4, can dissipate up to 2.3 W when the ambient temperature (TA) is 25°C. The power dissipated by the NCP81063 can be calculated from the following equation: Bi−Directional EN Signal The Enable pin (EN) is used to disable the DRVH and DRVL outputs to prevent power transfer. When EN is above the ENHI threshold, DRVH and DRVL change their states according to the PWM input. A UVLO fault turns on the internal MOSFET that pulls the EN pin towards ground. By connecting EN to the DRON pin of a controller, the PD + VCC ƪǒnHS QgHS ) nLS QgLSǓ (eq. 2) f ) Istandby ƫ Where nHS and nLS are the number of high−side and low−side FETs, respectively, QgHS and QgLS are the gate charges of the high−side and low−side FETs, respectively and f is the switching frequency of the converter. www.onsemi.com 7 NCP81063 PACKAGE DIMENSIONS DFN8 3x3, 0.5P CASE 506BJ ISSUE O PIN 1 REFERENCE 2X 0.10 C 2X NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 ÇÇÇ ÇÇÇ ÇÇÇ 0.10 C EDGE OF PACKAGE A B D DETAIL A E OPTIONAL CONSTRUCTION DIM A A1 A3 b D D2 E E2 e K L L1 L TOP VIEW DETAIL A OPTIONAL CONSTRUCTION DETAIL B 0.05 C A 8X 0.05 C (A3) NOTE 4 SIDE VIEW A1 D2 8X L 1 C DETAIL A SEATING PLANE EXPOSED Cu 4 8 5 8X ÉÉ ÉÉ MOLD CMPD 1.85 8X 0.35 OPTIONAL CONSTRUCTION K e SOLDERMASK DEFINED MOUNTING FOOTPRINT DETAIL B E2 8X MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.64 1.84 3.00 BSC 1.35 1.55 0.50 BSC 0.20 −−− 0.30 0.50 0.00 0.03 3.30 1.55 0.63 0.50 PITCH b 0.10 C A B BOTTOM VIEW 0.05 C NOTE 3 8X DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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