Sanyo LC863G32A Cgrom16k-byte on-chip 768-byte ram and 352ã 9 bit osd ram 8-bit 1-chip microcontroller Datasheet

Ordering number : ENA0548
LC863G64A,LC863G56A
LC863G48A,LC863G40A
LC863G32A,LC863G28A
LC863G24A
CMOS IC
64K/56K/48K/40K/32K/28K/24K-byte ROM,
CGROM16K-byte
on-chip 768-byte RAM and 352×9 bit OSD RAM
8-bit 1-chip Microcontroller
Overview
The LC863G64A/56A/48A/40A/32A/28A/24A are 8-bit single chip microcontrollers with the following on-chip
functional blocks:
• CPU: Operable at a minimum bus cycle time of 0.424µs
• On-chip ROM capacity
Program ROM: 64K/56K/48K/40K/32K/28K/24K bytes
CGROM: 16K bytes
• On-chip RAM capacity: 768 bytes
• OSD RAM: 352 × 9 bits
• Closed-Caption TV controller and the on-screen display controller
• Closed-Caption data slicer
• Four channels × 8-bit AD Converter
• Three channels × 7-bit PWM
• Two 16-bit timer/counters, 14-bit base timer
• 8-bit synchronous serial interface circuit
• IIC-bus compliant serial interface circuit (Multi-master type)
• UART interface circuit (full duplex)
• ROM correction function
• 18-source 10-vectored interrupt system
• Integrated system clock generator and display clock generator
Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators
TV control and the closed caption function
All of the above functions are fabricated on a single chip.
Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in
advance of our receiving your program ROM code order.
Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in
an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips.
Trademarks
IIC is a trademark of Philips Corporation.
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
Ver.1.00
N1506HKIM 20060911-S00002 No.A0548-1/21
LC863G64A/56A/48A/40A/32A/28A/24A
Features
„Read-only Memory (ROM):
65536 × 8 bits/57344 × 8 bits/49152 × 8 bits/
40960 × 8 bits/32768 × 8 bits/28672 × 8 bits/24576 × 8 bits for program
16128 × 8 bits for CGROM
„Random Access Memory (RAM):
768 × 8 bits (including 128 bytes for ROM correction function)
352 × 9 bits (for CRT display)
„OSD Functions
• Screen display
: 36 characters × 16 lines (by software)
• RAM
: 352 words (9 bits per word)
Display area : 36 words × 8 lines
Control area : 8 words × 8 lines
• Characters
Up to 252 kinds of 16 × 32 dot character fonts (4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts: a 16 × 17 dot and 8 × 9 dot character font
At least 111 characters need to be divide to display the caption fonts.
• Various character attributes
Character colors
: 16 colors
Character background colors : 16 colors
Fringe/shadow colors
: 16 colors
Full screen colors
: 16 colors
Rounding
Underline
Italic character (slanting)
• Attribute can be changed without spacing
• Vertical display start line number can be set for each row independently (Rows can be overlapped)
• Horizontal display start position can be set for each row independently
• Horizontal pitch (9 to 16 dots)*1 and vertical pitch (1 to 32 dots) can be set for each row independently
• Different display modes can be set for each row independently
Caption • Text mode/OSD mode 1/OSD mode 2 (Quarter size) /Simplified graphic mode
• Ten character sizes*1
Horiz. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4), (0.5 × 0.5)
(1.5 × 1), (1.5 × 2), (3 × 2), (3 × 4), (0.75 × 0.5)
• Shuttering and scrolling on each row
• Simplified Graphic Display
• External OSD clock input enable
Note *1: range depends on display mode: refer to manual for details.
„Data Slicer (closed caption format)
• Closed caption data and XDS data extraction
• NTSC/PAL, and extracted line can be specified
„Bus Cycle Time / Instruction-cycle Time
Bus Cycle Time
0.424µs
Instruction Cycle Time
0.848µs
Clock Divider
1/2
System Clock Oscillation
Internal VCO
(Ref: X’tal 32.768kHz)
Oscillation Frequency
Voltage
14.156MHz
4.5V to 5.5V
7.5µs
15.0µs
1/2
Internal RC
800kHz
4.5V to 5.5V
91.55µs
183.1µs
1/1
Crystal
32.768kHz
4.5V to 5.5V
183.1µs
366.2µs
1/2
Crystal
32.768kHz
4.5V to 5.5V
No.A0548-2/21
LC863G64A/56A/48A/40A/32A/28A/24A
„Ports
• Input / Output Ports
: 5 ports (28 terminals)
Data direction programmable in nibble units
: 1 port (8 terminals)
(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
Data direction programmable for each bit individually
: 4 ports (20 terminals)
„AD Converter
• 4-channels × 8-bit AD converters
„Serial Interfaces
• IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected
internally.
• Synchronous 8-bit serial interface
„UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit
• Built-in baudrate generator
„PWM Output
• 3 channels × 7-bit PWM
„Timer
• Timer 0: 16-bit timer/counter
With 2-bit prescaler + 8-bit programmable prescaler
Mode 0: Two 8-bit timers with a programmable prescaler
Mode 1: 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2: 16-bit timer with a programmable prescaler
Mode 3: 16-bit counter
The resolution of timer is 1 tCYC.
• Timer 1: 16-bit timer/PWM
Mode 0: Two 8-bit timers
Mode 1: 8-bit timer + 8-bit PWM
Mode 2: 16-bit timer
Mode 3: Variable bit PWM (9 to 16 bits)
In mode 0/1, the resolution of Timer1/PWM is 1 tCYC
In mode 2/3, the resolution is selectable by program; tCYC or 1/2 tCYC
• Base timer
Generate every 500ms overflow for a clock application
(using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow
(using 32.768kHz crystal oscillation for the base timer clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0
„Remote Control Receiver Circuit (connected to the P73/INT3/T0IN terminal)
• Noise rejection function
• Polarity switching
„Watchdog Timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows
„ROM Correction Function
Max 128 bytes/2 addresses
No.A0548-3/21
LC863G64A/56A/48A/40A/32A/28A/24A
„Interrupts
• 18 source 10 vectored interrupts
1. External Interrupt INT0
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8 bits)
6. Timer T1H, T1L
7. SIO0, UART receive
8. Data slicer, UART transmit
9. Vertical synchronous signal interrupt (VS), horizontal line (HS), AD
10. IIC, Port 0
• Interrupt priority control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible.
Low or high priority can be assigned to the interrupts from 3 to 10 listed above.
For the external interrupt INT0 and INT1, low or highest priority can be set.
„Sub-routine Stack Level
• A maximum of 128 levels (stack is built in the internal RAM)
„Multiplication/Division Instruction
• 16 bits × 8 bits (7 instruction cycle times)
• 16 bits ÷ 8 bits (7 instruction cycle times)
„3 Oscillation Circuits
• Built-in RC oscillation circuit used for the system clock
• Built-in VCO circuit used for the system clock and OSD
• X’tal oscillation circuit used for base timer, system clock and PLL reference
„Standby Function
• HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This mode can be released by the interrupt request or the system reset.
• HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO and X’tal oscillations. This mode can be
released by the following conditions.
- Pull the reset terminal (RES) to low level.
- Feed the selected level to either P70/INT0 or P71/INT1.
- Input the interrupt condition to Port 0.
„Package
• DIP42S(600mil): Lead-free type
• QIP48E(14×14) : Lead-free type
„Development Tools
• Flash EEPROM: LC86F3G64A
• Emulator:
Special ROM monitor tool
(When debugging it, one terminal in the I/O port is used as a pin only for the tool)
No.A0548-4/21
LC863G64A/56A/48A/40A/32A/28A/24A
Package Dimensions
unit : mm (typ)
3025C
22
1
21
0.25
13.8
42
15.24
37.7
(4.25)
0.51min
3.8 5.1max
0.95
0.48
1.78
SANYO : DIP42S(600mil)
(1.05)
Package Dimensions
unit : mm (typ)
3156A
17.2
0.8
14.0
24
48
13
14.0
37
1
17.2
25
36
12
1.0
0.35
0.15
0.1
3.0max
(2.7)
(1.5)
SANYO : QIP48E(14X14)
No.A0548-5/21
LC863G64A/56A/48A/40A/32A/28A/24A
Pin Assignments
P10/SO0
1
42
P07
P11/SI0
2
41
P06
P12/SCK0
3
40
P05
P13/PWM1
4
39
P04
P14/PWM2/TX
5
38
P03
P15/PWM3/RX
6
37
P02
P16/OSDCK
7
36
P01
P17/PWM
8
35
P00
VSS
9
34
P73/INT3/T0IN
XT1
10
33
P72/INT2/T0IN
XT2
11
32
P71/INT1
VDD
12
31
P70/INT0
P84/AN4
13
30
P63/SCLK1
P85/AN5
14
29
P62/SDA1
P86/AN6
15
28
P61/SCLK0
P87/AN7
16
27
P60/SDA0
RES
17
26
I
LC863G64A
LC863G56A
LC863G48A
LC863G40A
LC863G32A
LC863G28A
LC863G24A
FILT
18
25
BL
CVIN
19
24
B
VS
20
23
G
HS
21
22
R
Top view
NC
P14/PWM2/TX
P13/PWM1
P12/SCK0
P11/SI0
P10/SO0
NC
P07
P06
P05
P04
P03
48
47
46
45
44
43
42
41
40
39
38
37
SANYO: DIP42S(600mil) “Lead-free Type”
P15/PWM3/RX
1
36
P02
P16/OSDCK
2
35
P01
P17/PWM
3
34
P00
VSS
4
33
NC
XT1
5
32
P73/INT3/T0IN
XT2
6
31
P72/INT2/T0IN
VDD
7
30
P71/INT1
NC
8
29
P70/INT0
P84/AN4
9
28
P63/SCLK1
P85/AN5
10
27
P62/SDA1
P86/AN6
11
26
P61/SCLK0
P87/AN7
12
25
P60/SDA0
23
24
I
22
BL
NC
21
18
HS
B
17
VS
20
16
NC
19
15
CVIN
R
14
FILT
G
13
RES
LC863G64A
LC863G56A
LC863G48A
LC863G40A
LC863G32A
LC863G28A
LC863G24A
Top view
SANYO: QIP48E(14×14) “Lead-free Type”
No.A0548-6/21
LC863G64A/56A/48A/40A/32A/28A/24A
System Block Diagram
Interrupt Control
IR
X’tal
RC
VCO
ROM
Clock
Generator
Standby Control
PLA
PC
PLL
IIC
ROM Correct Control
ACC
SIO0
XRAM
B Register
Timer 0
Bus Interface
C Register
Timer 1
Port 1
ALU
Base Timer
Port 6
ADC
Port 7
PSW
INT0-3
Noise Rejection Filter
Port 8
RAR
PWM
Data Slicer
UART
RAM
OSD
Control
Circuit
CGROM
Stack Pointer
VRAM
Port 0
Watch Dog Timer
No.A0548-7/21
LC863G64A/56A/48A/40A/32A/28A/24A
Pin Description
Pin Description Table
Terminal
I/O
Function Description
VSS
-
Negative power supply
XT1
I
Input terminal for crystal oscillator
XT2
O
Output terminal for crystal oscillator
VDD
-
Positive power supply
RES
I
Reset terminal
FILT
O
Filter terminal for PLL
CVIN
I
Video signal input terminal
VS
I
Vertical synchronization signal input terminal
HS
I
Horizontal synchronization signal input terminal
R
O
Red (R) output terminal of RGB image output
G
O
Green (G) output terminal of RGB image output
B
O
Blue (B) output terminal of RGB image output
I
O
Intensity ( I ) output terminal of RGB image output
BL
O
Option
Fast blanking control signal
Switch TV image signal and caption/OSD image signal
Port 0
I/O
P00 to P07
•8-bit input/output port,
Pull-up register
Input/output can be specified in nibble unit
provided/not provided
•Other functions
Output Format
HOLD release input
CMOS/Nch-OD
Interrupt input
Port 1
I/O
P10 to P17
•8-bit input/output port
Output Format
Input/output can be specified in a bit
CMOS/Nch-OD
•Other functions
Port 6
P60 to P63
I/O
P10
SIO0 data output
P11
SIO0 data input/bus input/output
P12
SIO0 clock input/output
P13
PWM1 output
P14
PWM2 output/UART transmit
P15
PWM3 output/UART receive
P16
External OSD clock input
P17
Timer1 (PWM) output
•4-bit input/output port
Input/output can be specified for each bit
•Other functions
P60
IIC0 data I/O
P61
IIC0 clock output
P62
IIC1 data I/O
P63
IIC1 clock output
Continued on next page.
No.A0548-8/21
LC863G64A/56A/48A/40A/32A/28A/24A
Continued from preceding page.
Terminal
Port 7
I/O
I/O
Function Description
Option
•4-bit input/output port
P70
Input or output can be specified for each bit
P71 to P73
•Other function
P70
INT0 input/HOLD release input/
Nch-Tr. output for watchdog timer
P71
INT1 input/HOLD release input
P72
INT2 input/Timer 0 event input
P73
INT3 input (noise rejection filter connected)/
Timer 0 event input
Interrupt receiver format, vector addresses
rising
Port 8
I/O
falling
rising/
falling
H level
L level
vector
INT0
enable
enable
disable
enable
enable
03H
INT1
enable
enable
disable
enable
enable
0BH
INT2
enable
enable
enable
disable
disable
13H
INT3
enable
enable
enable
disable
disable
1BH
•4-bit input/output port
Input or output can be specified for each bit
P84 to P87
•Other function
AD converter input port (4 lines)
NC
-
Unused terminal
Leave open
• Output form and existence of pull-up resistor for all ports can be specified for each bit.
• Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in
port 1.
• Port status in reset
Terminal
I/O
Port 0
I
Pull-up resistor OFF, ON after reset release
Pull-up resistor status at selecting pull-up option
Port 1
I
Programmable pull-up resistor OFF
No.A0548-9/21
LC863G64A/56A/48A/40A/32A/28A/24A
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter
Symbol
Pins
Specification
Conditions
VDD[V]
Maximum supply
VDD max
VDD
min
typ
-0.3
voltage
max
unit
+6.5
Input voltage
VI(1)
• RES, HS, VS, CVIN
-0.3
VDD+0.3
Output voltage
VO(1)
R, G, B, I, BL, FILT
-0.3
VDD+0.3
Input/output voltage
VIO
• Ports 0, 1, 6, 7, 8
-0.3
VDD+0.3
IOPH(1)
• Ports 0, 1, 7, 8
High level output current
Peak output
current
• CMOS output
• For each pin.
IOPH(2)
R, G, B, I, BL
• CMOS output
• For each pin.
Total output
ΣIOAH(1)
• Ports 0, 1
The total of all pins.
ΣIOAH(2)
Ports 7, 8
The total of all pins.
ΣIOAH(3)
R, G, B, I, BL
The total of all pins.
IOPL(1)
Ports 0, 1, 6, 8
For each pin.
IOPL(2)
Port 7
For each pin.
IOPL(3)
R, G, B, I, BL
For each pin.
ΣIOAL(1)
Ports 0, 1
The total of all pins.
ΣIOAL(2)
Ports 6, 7, 8
The total of all pins.
ΣIOAL(3)
R, G, B, I, BL
The total of all pins.
Pd max
DIP42S(600mil)
Ta=-10 to +70°C
current
Peak output
-4
-5
-20
-10
-15
15
Low level output current
current
Total output
dissipation
Operating
5
40
Storage
temperature range
35
15
520
QIP48E(14×14)
Topr
Temperature range
Tstg
mA
15
current
Maximum power
V
mW
280
-10
+70
-55
+125
°C
No.A0548-10/21
LC863G64A/56A/48A/40A/32A/28A/24A
Recommended Operating Range at Ta = -10°C to +70°C, VSS = 0V
Parameter
Symbol
Pins
Specification
Conditions
VDD[V]
Operating
VDD(1)
supply voltage
VDD(2)
VDD
0.844µs ≤ tCYC ≤ 0.852µs
VHD
max
unit
5.5
4.5
5.5
2.0
5.5
4.5 to 5.5
0.6VDD
VDD
4.5 to 5.5
0.75VDD
VDD
4.5 to 5.5
VDD-0.5
VDD
4.5 to 5.5
0.7VDD
VDD
4.5 to 5.5
0.45VDD
VDD
4.5 to 5.5
VSS
0.2VDD
4.5 to 5.5
VSS
0.25VDD
4.5 to 5.5
VSS
0.6VDD
4.5 to 5.5
VSS
0.3VDD
4.5 to 5.5
VSS
0.18VDD
4µs ≤ tCYC ≤ 400µs
VDD
typ
4.5
range
Hold voltage
min
RAMs and the registers
data are kept in HOLD
mode.
High level
VIH(1)
Port 0 (Schumitt)
Output disable
input voltage
VIH(2)
• Ports 1,6
Output disable
(Schumitt CMOS)
• Port 7 (Schumitt)
port input/interrupt
• HS, VS, RES
(Schumitt)
VIH(3)
Port 70
Output disable
Watchdog timer input
VIH(4)
• Port 8
Output disable
port input
VIH(5)
• Port 16 (TTL)
V
Output disable
• Port 6
(Schumitt TTL)
port input
Low level
VIL(1)
Port 0 (Schumitt)
Output disable
input voltage
VIL(2)
• Ports 1,6
Output disable
(Schumitt CMOS)
• Port 7 (Schumitt)
port input/interrupt
• HS, VS, RES
(Schumitt)
VIL(3)
Port 70
Output disable
Watchdog timer input
VIL(4)
Port 8
Output disable
port input
VIL(5)
• Port 16 (TTL)
Output disable
• Port 6 (Schumitt TTL)
port input
CVIN
VCVIN
CVIN
5.0
Operation
tCYC(1)
• All functions operating
cycle time
tCYC(2)
• AD converter operating
• OSD and Data slicer
1Vp-p
-3dB
4.5 to 5.5
0.844
4.5 to 5.5
0.844
1Vp-p
0.848
1Vp-p
+3dB
0.852
30
µs
are not operating
tCYC(3)
Vp-p*
• OSD, AD converter and
Data slicer are
4.5 to 5.5
0.844
400
4.5 to 5.5
0.4
0.8
3.0
4.5 to 5.5
13
14
15
not operating
Oscillation
FmRC
Internal RC oscillation
frequency range
External
FmICK
OSD clock
input frequency
P16/OSDCK
DUTY50±5% of external
OSD clock
MHz
range
* Vp-p: Peak-to-peak voltage
No.A0548-11/21
LC863G64A/56A/48A/40A/32A/28A/24A
Electrical Characteristics at Ta = -10°C to +70°C, VSS = 0V
Parameter
Symbol
Pins
Specification
Conditions
VDD[V]
High level
IIH(1)
Ports 0, 1, 6, 7, 8
input current
min
typ
max
unit
• Output disable
• Pull-up MOS Tr. OFF
• VIN=VDD
4.5 to 5.5
1
4.5 to 5.5
1
(including the off-leak
current of the output Tr.)
Low level
IIH(2)
• RES
• HS, VS
• VIN=VDD
IIL(1)
Ports 0, 1, 6, 7, 8
• Output disable
input current
µA
• Pull-up MOS Tr. OFF
• VIN=VSS
4.5 to 5.5
-1
4.5 to 5.5
-1
4.5 to 5.5
VDD-1
VDD-0.5
(including the off-leak
current of the output Tr.)
High level
IIL(2)
• RES
• HS, VS
VIN=VSS
VOH(1)
•CMOS output of
IOH=-1.0mA
output voltage
ports 0, 1, 71 to 73, 8
VOH(2)
R, G, B, I, BL
IOH=-0.1mA
4.5 to 5.5
Low level
VOL(1)
Ports 0, 1, 71 to 73, 8
IOL=10mA
4.5 to 5.5
1.5
output voltage
VOL(2)
Ports 0, 1, 71 to 73, 8
IOL=1.6mA
4.5 to 5.5
0.4
VOL(3)
• R, G, B, I, BL
IOL=3.0mA
4.5 to 5.5
0.4
• Port 6
Pull-up MOS
VOL(4)
Port 6
IOL=6.0mA
4.5 to 5.5
0.6
VOL(5)
Port 70
IOL=1mA
4.5 to 5.5
0.4
Rpu
• Ports 0, 1, 7, 8
VOH=0.9VDD
Tr. resistance
Bus terminal
RBS
short circuit
4.5 to 5.5
13
V
38
80
kΩ
4.5 to 5.5
130
300
Ω
4.5 to 5.5
0.1VDD
• P60 to P62
• P61 to P63
resistance
(SCL0 to SCL1,
SDA0 to SDA1)
Hysteresis
VHYS
Input clump
• Ports 0, 1, 6, 7
Output disable
• RES
• HS, VS
voltage
VCLMP
CVIN
CP
All pins
V
5.0
voltage
Pin capacitance
2.3
2.5
2.7
• f=1MHz
• Every other terminals are
connected to VSS.
4.5 to 5.5
10
pF
• Ta=25°C
No.A0548-12/21
LC863G64A/56A/48A/40A/32A/28A/24A
Serial Input/Output Characteristics at Ta = -10°C to +70°C, VSS = 0V
Parameter
Symbol
Pins
Specification
Conditions
VDD[V]
Input clock
tCKCY(1)
• SCK0
Refer to figure 4.
Low Level
tCKL(1)
4.5 to 5.5
pulse width
High Level
tCKCY(2)
Low Level
tCKL(2)
• SCK0
tCYC
• Use pull-up resistor (1kΩ)
2
when Nch open-drain output.
• Refer to figure 4.
4.5 to 5.5
pulse width
1/2tCKCY
tCKH(2)
1/2tCKCY
pulse width
Serial input
Data set up time
SI0
• Data set-up to SCK0.
0.1
• Data hold from SCK0.
• Refer to figure 4.
Data hold time
4.5 to 5.5
tCKI
0.1
Output delay time
Serial output
tICK
unit
1
• SCLK0
High Level
max
1
tCKH(1)
Cycle
typ
2
• SCLK0
pulse width
Output clock
Serial clock
Cycle
min
tCKO(1)
SO0
µs
• Data hold from SCK0.
4.5 to 5.5
• Use pull-up resistor (1kΩ)
(Using external
7/12tCYC
+0.2
when Nch open-drain output.
clock)
Output delay time
tCKO(2)
SO0
• Refer to figure 4.
(Using internal
1/3tCYC
4.5 to 5.5
+0.2
clock)
IIC Input/Output Conditions at Ta = -10°C to +70°C, VSS = 0V
Parameter
Standard
Symbol
min
High speed
max
min
unit
max
SCL Frequency
fSCL
0
BUS free time between stop to start
tBUF
4.7
1.3
µs
HOLD time of start, restart condition
tHD; STA
4.0
0.6
µs
L time of SCL
tLOW
4.7
1.3
µs
H time of SCL
tHIGH
4.0
0.6
µs
Set-up time of restart condition
tSU; STA
4.7
0.6
HOLD time of SDA
tHD; DAT
0
0
Set-up time of SDA
tSU; DAT
250
100
Rising time of SDA, SCL
tR
1000
20+0.1Cb
300
ns
Falling time of SDA, SCL
tF
300
20+0.1Cb
300
ns
Set-up time of stop condition
tSU; STO
4.0
100
0
0.6
400
kHz
µs
0.9
µs
ns
µs
Refer to figure 10
Note 1: Cb: Total capacitance of all BUS (unit: pF)
No.A0548-13/21
LC863G64A/56A/48A/40A/32A/28A/24A
UART (Full Duplex) Operating Conditions at Ta = -10°C to +70°C, VSS = 0V
Parameter
Symbol
Pin/Remarks
Specification
Condition
VDD[V]
Transfer rate*
UBR(1)
typ
max
unit
8192/6
tCYC
0.844µs ≤ tCYC ≤ 400µs
P14, 15
4.5 to 5.5
UBR(2)
* High speed mode: UBR= (n+1) × (8/6)tCYC
Low speed mode: UBR= (n+1) × (32/6)tCYC
Data length
Stop bits
Parity bits
min
16/6
n=1 to 255
:7/8/9 bits(LSB First)
:1 bit
:None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H)
Start bit
Start of transmission
Stop bit
Transmit data (LSB First)
End of transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H)
Start bit
Stop bit
Receive data (LSB First)
Start of reception
End of reception
UBR
No.A0548-14/21
LC863G64A/56A/48A/40A/32A/28A/24A
Pulse Input Conditions at Ta = -10°C to +70°C, VSS = 0V
Parameter
Symbol
Pins
Limits
Conditions
VDD[V]
High/low level
tPIH(1)
• INT0, INT1
• Interrupt acceptable
pulse width
tPIL(1)
• INT2/T0IN
• Timer0-countable
tPIH(2)
INT3/T0IN
• Interrupt acceptable
tPIL(2)
(1tCYC is selected for noise
• Timer0-countable
min
4.5 to 5.5
1
4.5 to 5.5
2
4.5 to 5.5
32
typ
max
unit
rejection clock.)
tCYC
tPIH(3)
INT3/T0IN
• Interrupt acceptable
tPIL(3)
(16tCYC is selected for
• Timer0-countable
tPIH(4)
INT3/T0IN
• Interrupt acceptable
tPIL(4)
(64tCYC is selected for
• Timer0-countable
4.5 to 5.5
128
4.5 to 5.5
200
4.5 to 5.5
3
noise rejection clock.)
noise rejection clock.)
tPIL(5)
RES
Reset acceptable
tPIH(6)
HS, VS
• Display position controllable
• The active edge of HS and
tPIL(6)
VS must be apart at least
µs
1 tCYC.
• Refer to figure 6.
Rising/falling
tTHL
time
tTLH
External
tOSCK
HS
Refer to figure 6.
OSDCK (P16)
Refer to figure 7.
4.5 to 5.5
4.5 to 5.5
OSD clock
500
10
ns
ns
input
AD Converter Characteristics at Ta = -10°C to +70°C, VSS = 0V
Parameter
Symbol
Pins
Limits
Conditions
VDD[V]
Resolution
N
Absolute
ET
(Note 2)
tCAD
ADCR2=0 (Note 3)
min
typ
max
8
Conversion time
ADCR2=1 (Note 3)
Analog input
VAIN
AN4 to AN7
16
4.5 to 5.5
Analog port
IAINH
VAIN=VDD
input current
IAINL
VAIN=VSS
LSB
tCYC
32
VSS
voltage range
bit
±1.5
precision
unit
VDD
1
V
µA
-1
Note 2: Absolute precision does not include quantizing error (1/2LSB).
Note 3: Conversion time is the time till the complete digital conversion value for analog input value is set to a register
after the instruction to start conversion is sent.
No.A0548-15/21
LC863G64A/56A/48A/40A/32A/28A/24A
Sample Current Dissipation Characteristics at Ta = -10°C to +70°C, VSS = 0V
The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the
recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally.
The currents through the output transistors and the pull-up MOS transistors are ignored.
Parameter
Symbol
Pins
Limits
Conditions
VDD[V]
Current dissipation
IDDOP(1)
VDD
typ
max
unit
•FmX’tal=32.768kHz X’tal oscillation
during basic
•System clock: VCO
operation
•VCO for OSD operating
(Note 4)
min
4.5 to 5.5
10
24
mA
4.5 to 5.5
55
300
µA
4.5 to 5.5
3
9
mA
4.5 to 5.5
300
1000
•Internal RC oscillation stops
IDDOP(2)
•FmX’tal=32.768kHz X’tal oscillation
•System clock: X'tal
(Instruction cycle time: 366.2µs)
•VCO for system, VCO for OSD,
Internal RC oscillation stop
•Data slicer, AD converters stop
Current dissipation
IDDHALT(1)
•HALT mode
in HALT mode
•FmX’tal=32.768kHz X’tal oscillation
(Note 4)
•System clock: VCO
•VCO for OSD stops
• Internal RC oscillation stops
IDDHALT(2)
•HALT mode
•FmX’tal=32.768kHz X’tal oscillation
•VCO for system stops
•VCO for OSD stops
•System clock: Internal RC
IDDHALT(3)
µA
•HALT mode
•FmX’tal=32.768kHz X’tal oscillation
•VCO for system stops
•VCO for OSD stops
4.5 to 5.5
45
200
4.5 to 5.5
0.05
20
•System clock: X’tal
(Instruction cycle time: 366.2µs)
Current dissipation
in HOLD mode
IDDHOLD
•HOLD mode
•All oscillation stops.
µA
(Note 4)
Note 4: The currents through the output transistors and the pull-up MOS transistors are ignored.
No.A0548-16/21
LC863G64A/56A/48A/40A/32A/28A/24A
Recommended Oscillation Circuit and Sample Characteristics
The sample oscillation circuit characteristics in the table below is based on the following conditions:
• Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation
evaluation board.
• Sample characteristics are the result of the evaluation with the recommended circuit parameters connected
externally.
Recommended oscillation circuit and sample characteristics (Ta = -10°C to +70°C)
Frequency
32.768kHz
Manufacturer
SEIKO EPSON
Recommended circuit parameters
Oscillator
C-002RX
Operating
Oscillation
supply
stabilizing time
C1
C2
Rf
Rd
voltage range
typ
max
18pF
18pF
OPEN
390kΩ
4.5 to 5.5V
1.0s
1.5s
Notes
Notes: The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes
stable after the following conditions. (Refer to Figure 2)
1. The VDD becomes higher than the minimum operating voltage after the power is supplied.
2. The HOLD mode is released.
The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with
oscillator manufacturer with the following notes in your mind.
• Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the
oscillation frequency on the production board.
• The above oscillation frequency and the operating supply voltage range are based on the operating temperature of
-10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high
reliability such as car products, please consult with oscillator manufacturer.
• When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with
Sanyo sales personnel.
Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed
with low gain in order to reduce the power dissipation, refer to the following notices.
• The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as
possible.
• The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND.
• The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit.
XT1
XT2
Rf
Rd
C1
C2
X’tal
Figure 1 Recommended Oscillation Circuit
No.A0548-17/21
LC863G64A/56A/48A/40A/32A/28A/24A
VDD
VDD limit
0V
Power supply
Reset time
RES
Internal RC
resonator
oscillation
XT1,XT2
tmsVCO
VCO for system
Operation mode
stable
Unfixed
Reset
Instruction execution mode
<Reset Time and Oscillation Stabilizing Time>
HOLD release
Valid
Internal RC
resonator
oscillation
XT1, XT2
tmsVCO
VCO for system
Operation mode
stable
HOLD
Instruction execution mode
<Hold Release Signal and Oscillation Stabilizing Time>
Figure 2 Oscillation Stabilizing Time
No.A0548-18/21
LC863G64A/56A/48A/40A/32A/28A/24A
VDD
RRES
(Note)
Determine the CRES, RRES value to generate more than
200µs reset time.
RES
CRES
Figure 3 Reset Circuit
0.5VDD
<AC Timing Measurement Point>
VDD
tCKCY
tCKL
tCKH
1kΩ
SCK0
tICK
tCKI
SI0
tCKO
50pF
SO0
SB0
<Timing>
<Test load>
Figure 4 Serial Input/Output Test Condition
TPIL (1) yo (5)
TPIH (1) to (4)
Figure 5 Pulse Input Timing Condition -1
No.A0548-19/21
LC863G64A/56A/48A/40A/32A/28A/24A
tPIL(6)
HS
0.75VDD
0.25VDD
tTLH
VS
tPIL(6)
more than ±1tCYC
Figure 6 Pulse Input Timing Condition - 2
HS
OSDCK
tOSCK
tOSCK
Note: tOSCK must be saving constant
Figure 7 Pulse Input Timing Condition - 3
LC863G64A
10kΩ
HS
C536
HS
Figure 8 Recommended Interface Circuit
Noise filter
1µF
C-Video
CVIN
200Ω
1000pF
Coupling capacitor
Output impedance of C-Video before Noise filter should be less then 100Ω.
Figure 9 CVIN Recommended Circuit
No.A0548-20/21
LC863G64A/56A/48A/40A/32A/28A/24A
100Ω
FILT
1MΩ
+
2.2µF
-
33000pF
Note: Place FILT parts on board as close to the microcontroller as possible.
Figure 10 FILT Recommended Circuit
P
S
P
Sr
SDA
tBUF
tHD;STA
tF
tR
tHD;STA
tsp
SCL
tHIGH
tLOW
tHD;DAT
S : start condition
P : stop condition
Sr : restart condition
tSU;DAT
tsp : spike suppression
tSU;STA
tSU;STO
Standard mode : not exist
High speed mode : less than 50ns
Figure 11 IIC Timing
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
products must not be exported without obtaining the export license from the authorities concerned in
accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or
otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and
reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
property rights or other rights of third parties.
This catalog provides information as of November, 2006. Specifications and information herein are subject
to change without notice.
PS No.A0548-21/21
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