Rohm BD9275F Silicon monolithic integrated circuit Datasheet

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STRUCTURE
Silicon Monolithic Integrated Circuit
NAME OF PRODUCT
DC-AC Inverter Control IC
TYPE
BD9275F
FUNCTION
・Using 20V process / 1ch control with Push-Pull
・Accuracy of drive output frequency:3.5%(IC Only/Built-in CT Capacitor)
・High accuracy timer latch current(±15%)
・Built-in FAIL function
・Adjustable latch timing
・Adjustable slow start time
・Lamp current and voltage sense feedback control
・Mode-selectable the operating or stand-by mode by STB pin (Typ.=0uA )
○Absolute Maximum Ratings(Ta = 25℃)
Parameter
Supply Voltage
OUTPUT PIN Voltage
Limits
Unit
VCC
20
V
N1, N2
20
V
Operating Temperature Range
Topr
-40~+85
℃
Storage Temperature Range
Tstg
-55~+150
℃
Maximum Junction Temperature
Tjmax
+150
℃
Pd
SOP18:562*
mW
Power Dissipation
*1
Symbol
Pd derate at -4.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇動作範囲
項目
Supply voltage
Input Frequency Ratio PWM_IN PIN
DRIVER frequency
記号
範囲
単位
VCC
8.0 ~ 18.0
V
F_PWM_IN
0.060~0.5
kHz
F_OUT
20 ~ 90
kHz
REV. B
2/4
○Electric Characteristics(Ta=25℃、VCC=12V、STB=3.0V)
LIMIT
Item
SYMBOL
MIN.
TYP.
MAX.
UNIT
CONDITION
Operating current
Icc1
-
2.0
4.0
mA
RT=100kΩ, FB=GND, IS=1.5V
Stand-by current
Icc2
-
0
20
μA
VSTB=0V
Stand-by voltage H
VSTBH
2
-
VCC
V
System ON
Stand-by voltage L
VSTBL
-0.3
-
0.8
V
STB PIN pull down resistor
RSTB
180
375
750
kΩ
Operating voltage
VCC_UVLO
7.2
7.5
7.8
V
VCC=6V→8V sweep
Hesteresis width
⊿UVLO_HYS
0.3
0.5
0.7
V
VCC=8V→6V sweep
RT pin Voltage
VRT
1.300
1.500
1.700
V
RT=100kΩ
SRT ON resistance
RSRT
-
75
150
Ω
VSRT=0.1V
((WHOLE DEVICE))
((STAND BY CONTROL))
System OFF
VSTB=2V
((VCC UVLO BLOCK)))
((OSC BLOCK)
)
((PWM Dimming Block))
PWM_IN PIN voltage H
VPWMIN_H
2.4
-
5
V
VPWM_IN=0V⇒3.0V
PWM_IN PIN voltage L
VPWMIN_L
-0.3
-
0.8
V
VPWM_IN=3.0V⇒0V
PWM_IN PIN pull down resistor
R_PWMIN
1000
2000
4000
kΩ
IS threshold voltage
VIS
1.225
1.250
1.275
V
VS threshold voltage
VVS
1.200
1.250
1.300
V
VPWM_I=5V
((FEED BACK BLOCK))
IS source current
IIS
16
20
24
μA
VISCOMP
0.565
0.625
0.685
V
SS term END Voltage
VSS
2.400
2.500
2.600
V
Soft start current
ISS
1.7
2.0
2.3
μA
IS COMP detect voltage
IS=1.0V
IS=1.3V→0.5V
((SLOW START BLOCK))
VSS=0V⇒3V
VSS=1.0V IS=1.5V
((COMP BLOCK))
COMP over voltage
detect voltage
VCOMPH
1.900
2.000
2.100
V
VSS>2.5V VCOMP=1.5V→2.5V
⊿VCOMPH
0.100
0.200
0.300
V
VSS<2.0V VCOMP=2.5V→1.5V
COMP PIN pull down resistor
RCOMP
1000
2000
4000
kΩ
COMP=5V
FAIL ON resistance
RFAIL
-
75
150
Ω
VFAIL=0.1V
3.0
6.0
Ω
IIN=100mA
IIN=-100mA
Hysterisis width (COMP)
((OUTPUT BLOCK))
N1,N2 PIN output
sink resistance
N1,N2 PIN output
source resistance
RsinkN
1.5
RsourceN
4.5
9
18
Ω
MAX DUTY
MAX DUTY
45
47.0
49.5
%
FOUT=50kHz
FOUT
48.25
50
51.75
kHz
RT=100kΩ
Timer Latch setting voltage
VCP
2.900
3.000
3.100
V
Timer Latch setting current
ICP
1.7
2.0
2.3
μA
Drive output frequency
((TIMER BLOCK))
(This product is not designed to be radiation-resistant.)
REV. B
VCP=0V⇒3.2V
CP=1.0V IS=1.5V COMP=3.0V
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〇Package Dimensions
Device Name
MAX11.55 (include. BURR)
MAX11.55 (include. BURR)
BD9275F
Lot No.
SOP-16 (Unit:mm)
〇PIN No.・PIN NAME・FUNCTION
BD9275F
No.
PIN
Function
No.
PIN
Function
1
VCC Supply voltage input
16
N1
NMOS FET driver
2
STB Stand-by switch
15
N2
NMOS FET driver
External resistor from SRT to RT for adjusting
3
SRT
4
RT
5
GND GROUND
12
SS
External capacitor from SS to GND for Soft Start Control
6
FB
Error amplifier output
11
CP
External capacitor from CP to GND for Timer Latch
7
IS
Error amplifier input
10
FAIL Error signal output pin
8
VS
Error amplifier input
9
COMP Over voltage detect pin
the triangle oscillator
14
PGND Ground for FET drivers
External resistor from SRT to RT for adjusting
the triangle oscillator
13
PWM_IN Dimming pulse signal input pin
REV. B
4/4
〇NOTE FOR USE
1. This product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum ratings.
Once IC is destroyed, failure mode will be difficult to determine, like short mode or open mode. Therefore, physical
protection countermeasure, like fuse is recommended in case operating conditions go beyond the expected absolute maximum
ratings.
2. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended
operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating
ranges, however the variation will be small.
3. Mounting failures, such as misdirection or miscounts, may harm the device.
4. A strong electromagnetic field may cause the IC to malfunction.
5. The GND pin should be the location within ±0.3V compared with the PGND pin. ALL voltage should be under VCC voltage
+0.3V
6. BD9275F incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is
designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee
its operation of the thermal shutdown circuit is assumed.
7. When modifying the external circuit components, make sure to leave an adequate margin for external components actual
value and tolerance as well as dispersion of the IC.
8. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching.
Make sure to leave adequate margin for this IC variation.
9. Under operating CP charge (under error mode) analog dimming and burst dimming are not operate.
10. Under operating Slow Start Control (SS is less than 2.5V), It does not operate Timer Latch.
11. By STB voltage is changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state
(0.8~2.0V).
12. The pin connected a connector need to connect to the resistor for electrical surge destruction.
13. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins. A P-N junction is
formed from this P layer of each pin. For example, the relation between each potential is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by
which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input
pin.
Transistor (NPN)
Resistance
(PinA)
(PinB)
B
E
C
C
GND
P
P+
N
P+
N
N
P substrate
GND
Parasitic diode
N
N
N
P substrate
GND
Parasitic diode
(PinB)
(PinA)
B
CC
B
EE
Parasitic diode
GND
GND
Parasitic diode
Other adjacent components
Fig-1 Simplified structure of a Bipolar IC
REV. B
Notice
Notes
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