CML FX802LG Dvsr codec Datasheet

FX802
DVSR CODEC
SERIAL
CLOCK
COMMAND
DATA
REPLY
DATA
XTAL/
CLOCK
IRQ
CS
XTAL
AUDIO
IN
AUDIO
OUT
AUDIO
BYPASS
CLOCK
C-BUS INTERFACE AND CONTROL LOGIC
GENERATOR
DECODER
OUTPUT
VBIAS
PLAY
STORE
COMMAND
COMMAND
BUFFER
BUFFER
SPEECH
SPEECH
CONTROL
STATUS
REGISTER
REGISTER
ENCODE
CLOCK
DATA
DATA
POWER
READ
WRITE
PLAY
STORE
COUNTER
COUNTER
COUNTERS
COUNTERS
DECODE
CLOCK
MOD
DEMOD
ASSESS
ENCODER
CLOCK
DECODER
CLOCK
IDLE
PATTERN
DRAM CONTROL AND TIMING
DIRECT ACCESS CLOCKS and DATA
WE
CAS
VDD
RAS 1 RAS 2 RAS 3 RAS 4
A9
A8
A7
A6
A5
A4
A3/ECK
A2/DCK
DRAM ADDRESS LINES
A0/ENO
(ENCODER
OUT)
VBIAS
VSS
A1/ DEI
(DECODER
IN)
Fig.1 FX802 DVSR Codec
Brief Description
A Continuously Variable Slope Delta Modulation (CVSD)
encoder and decoder.
The FX802 may also be used without DRAM (as a “standalone” CVSD Codec), in which case direct access is
provided to the CVSD Codec digital data and clock signals.
Control and timing circuitry for up to 4Mbits of external
Dynamic Random Access Memory (DRAM).
All functions are controlled by “C-BUS” commands from
the system µController.
“C-BUS” µProcessor interface and control logic.
The Storage, Recovery and Replay functions of the
FX802 can be used for:
The FX802 DVSR Codec contains:
When used with external DRAM, the FX802 has four primary
functions:
● Speech Storage
Speech signals present at the Audio Input may be digitized
by the CVSD encoder, and the resulting bit stream stored
in DRAM. This process also provides readings of input
power level for use by the system µController.
● Speech Playback
Previously digitized speech data may be read from DRAM
and converted back into analogue form by the CVSD
decoder.
● Data Storage
Digital data sent over the “C-BUS” from the system
µController may be stored in DRAM.
● Data Retrieval
Digital data may be read from DRAM and sent over
“C-BUS” to the system µController.
Speech storage and playback may be performed
concurrently with data storage or retrieval.
Publication D/802/4 December 1995
● Answering Machine applications, where an incoming
speech message is stored for later recall.
● Busy Buffering, an outgoing speech message is stored
temporarily until the transmit channel becomes free.
● Automatic transmission of pre-recorded ‘Alarm’ or
status announcements.
● Time Domain Scrambling of speech messages.
● VOX control of transmitter functions.
● Temporary Data Storage applications, such as
buffering of over-air data transmissions.
On-chip the Delta Codec is supported by input and output
analogue switched-capacitor filters and audio output
switching circuitry. The DRAM control and timing circuitry
provides all the necessary address, control and refresh
signals to interface to external DRAM.
The FX802 DVSR Codec is a low-power 5-volt CMOS LSI
device.
Pin Number Function
FX802
J
FX802
LG/LS
1
Row Address Strobe 2 (RAS2): Should be connected to the Row Address Strobe input of the second
1Mbit DRAM chip (if fitted).
2
1
Row Address Strobe 1 (RAS1): Should be connected to the Row Address Strobe input of the first
DRAM chip.
3
2
Write Enable (WE): The DRAM Read/Write control pin.
4
Xtal: The output of the on-chip clock oscillator. External components are required at this output when
a Xtal is employed. A Xtal cannot be used with the 24-pin version.
5
3
Xtal/Clock: The input to the on-chip clock oscillator inverter. A 4.0MHz Xtal or externally derived clock
should be connected here, see Figure 2. This clock provides timing for on-chip elements, filters etc. A
Xtal cannot be used with the 24-pin version. Various Xtal frequencies can be used with this device, see
Table 3 for the sampling clock rate variations.
6
4
Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the µController, by
going to a logic “0.” This is a “wire-or able” output, enabling the connection of up to 8 peripherals to 1
interrupt port on the µController. The pin has a low-impedance pulldown to logic “0” when active and a
high impedance when inactive.
Conditions indicated by this function are:
Power Reading Ready, Play Command Complete, Store Command Complete.
7
5
Serial Clock: The “C-BUS,” serial clock input. This clock, produced by the µController, is used for
transfer timing of commands and data to and from the DVSR Codec. See Timing Diagrams and
System Support Document, Document 2. The clock-rate requirements vary for differing FX802
functions.
8
6
Command Data: The “C-BUS,” serial data input from the µController. Data is loaded to this device in
8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. See Timing Diagrams
and System Support Document, Document 2.
9
7
Chip Select (CS): The “C-BUS”, data transfer control function, this input is provided by the
µController. Command Data transfer sequences are initiated, completed or aborted by the CS signal.
See Timing Diagrams and System Support Document, Document 2.
10
8
Reply Data: The “C-BUS,” serial data output to the µController. The transmission of Reply Data bytes
is synchronized to the Serial Data Clock under the control of the Chip Select input. This 3-state output
is held at high impedance when not sending data to the µController. See Timing Diagrams and System
Support Document, Document 2.
11
9
VBIAS: The output of the on-chip analogue circuitry bias system, held internally at VDD/2. This pin should
be decoupled to VSS by a capacitor C1, See Figure 2.
12
10
Audio Out: The analogue signal output.
13
11
Audio In: The audio (speech) input. The signal to this pin must be a.c. coupled by a capacitor C4 and
decoupled to VSS by an HF bypass capacitor C6. For optimum noise performance this input should be
driven from a source impedance of less than 100Ω.
14
12
VSS: Negative supply rail (GND).
2
Pin Number Function
FX802
J
FX802
LG/LS
15
13
DRAM Data In/A0/ (Direct Access – Encoder Out (ENO)): Connected to the DRAM data input and
address line A0. With no DRAM employed this output is available (in Direct Access mode) as the Delta
Encoder digital data output. Direct Access control is achieved by Control Register byte 1 – bit 6.
16
14
DRAM Data Out/ A1/ (Direct Access – Decoder In (DEI)): Connected to the DRAM data output and
address line A1. With no DRAM employed this pin is available (in Direct Access mode) as the Delta
Decoder digital data input. Direct Access control is achieved by Control Register byte 1 – bit 6.
17
15
DRAM A2/ (Direct Access – Decoder Clock (DCK)): DRAM address line A2. With no DRAM
employed this pin is available (in Direct Access mode) as the Delta Decoder Clock input. Direct Access
control is achieved by Control Register byte 1 – bit 6.
18
16
DRAM A3/ (Direct Access – Encoder Clock (ECK)): DRAM address line A3. With no DRAM
employed this pin is available (in Direct Access mode) as the Delta Encoder Clock output. Direct
Access control is achieved by Control Register byte 1 – bit 6.
19
17
DRAM A4:
DRAM address line A4.
20
18
DRAM A5:
DRAM address line A5.
21
19
DRAM A6:
DRAM address line A6.
22
20
DRAM A7:
DRAM address line A7.
23
21
DRAM A8:
DRAM address line A8.
24
Row Address Strobe 4 (RAS4): Should be connected to the Row Address Strobe input of the fourth
1Mbit DRAM chip (if fitted).
25
Row Address Strobe 3 (RAS3): Should be connected to the Row Address Strobe input of the third
1Mbit DRAM chip (if fitted).
26
22
DRAM A9: DRAM address line A9. This pin is not connected when a 256kbit DRAM is employed.
Note: To simplify PCB layout, the DRAM address inputs A0 – A8 may be connected in any physical
order to the DVSR Codec output pins A0 – A8.
27
23
Column Address Strobe (CAS): The DRAM Column Address Strobe pin. Should be connected to the
CAS pins of all DRAM chips.
28
24
VDD: Positive supply rail. A single, stable +5-volt supply is required. Levels and voltages within the
DVSR Codec are dependant upon this supply.
3
External Components
VDD
C5
4 x 1Mbit
DRAM
A0 – A9
WE
CAS
RAS
VSS
RAS2
R
1
RAS1
WE
VDD
1 §
28
2
27
3
XTAL/CLOCK
IRQ
C-BUS
INTERFACE
SERIAL CLOCK
COMMAND DATA
CS
REPLY DATA
VBIAS
AUDIO OUT
AUDIO IN
C4
C6
VSS
4 §
§ 24
6
23
7
22
8
RAS3
§ 25
5
FX802J
20
10
19
11
18
12
17
13
16
14
15
Q
A0 – A9
WE
CAS
RAS
RAS4
A8
D
A7
Q
A6
21
9
D
A9
26
XTAL
See INSET
CAS
A0 – A9
WE
CAS
RAS
A5
A4
A3/ECK
D
Q
A2/DCK
A1/DEI
A0/ENO
C1
R3
A0 – A9
WE
CAS
RAS
D
Q
VSS
INSET
XTAL
X1
R
2
XTAL/CLOCK
C3
C2
Component
Value
R1
R2
R3
C1
C2
C3
22.0kΩ
1.0MΩ
1.0kΩ
1.0µF
33.0pF
33.0pF
4§
FX802J
5
=
C4
C5
C6
X1
=
or
or
1.0µF
1.0µF
1.0nF
4.00MHz
4.032MHz
4.096MHz
Tolerance: R = ±10% C = ±20%
VSS
Fig.2 Recommended Component and DRAM Connections
Notes
1. Xtal circuitry shown INSET is in accordance with CML
Application Note D/XT/2 December 1991.
6. Recommended DRAM Parameters:
256kbit x 1 or 1Mbit x 1 Dynamic Random Access Memory
with ‘CAS before RAS’ refresh mode, maximum Row
Address Access time = 200nsec.
2. External Xtal circuitry is not applicable to the 24-pin/lead
versions of this device, only a clock pulse input can be
used.
Example DRAM types:
256kbit (262,144bits)
Texas Instruments
Hitachi
1Mbit (1,048,576bits)
Texas Instruments
Hitachi
3. Functions whose pins are marked § above are not
available on the 24-pin/lead versions of this device. Pin
numbers illustrated are for 28-pin versions.
4. Table 3 details the actual encoder/decoder sample rates
available using the Xtal frequencies recommended above.
TMS4256–20
HM51256–15
TMX4C1024–15
HM511000–15
7. Figure 2 (above) shows connections to 4 x 1Mbit sections
of DRAM. If desired, to simplify PCB layout, the DRAM
inputs A0 to A8 may be connected in any order to the
FX802 DVSR Codec output pins A0 to A8. Connections to
256kbit DRAM are similar, but A9 unconnected.
5. R1 is used as the DBS 800 system common-pullup for the
“C-BUS” Interrupt Request (IRQ) line, the optimum value
will depend upon the circuitry connected to the IRQ line.
Up to 8 peripherals may be connected to this line.
8. When using the FX802 “stand-alone (Direct Access),” no
DRAM should be connected.
4
Controlling Protocol
Control of the functions of the FX802 DVSR Codec is by a group of Address/Commands (A/Cs) and appended instructions or
data to and from the system µController (see Figure 5). The use and content of these instructions is detailed in the following
paragraphs and tables.
Command
Assignment
General Reset
Write to Control Register
Read Status Register
Store ‘N’ pages. Start page ‘X’
Store ‘N’ pages. Start page ‘X’
Play ‘N’ pages. Start page ‘X’
Play ‘N’ pages. Start page ‘X’
Write Data. Start page ‘P’
Read Data. Start page ‘P’
Write Data – Continue
Read Data – Continue
Address/Command (A/C) Byte
Hex.
Binary
MSB
LSB
01
60
61
62
63
64
65
66
67
68
69
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
+
+
+
+
+
+
+
+
+
+
+
Data
Byte/s
2 byte Instruction to Control Register
1 byte Reply from Status Register
2 bytes Command – Immediate
2 bytes Command – Buffered
2 bytes Command – Immediate
2 bytes Command – Buffered
2 bytes ‘P’ + Write data
2 bytes ‘P’ + Read data
Write data
Read data
Table 1 “C-BUS” Address/Commands
Address/Commands
Speech
Instruction and data transactions to and from this device
consist of an Address/Command (A/C) byte followed by
either:
(i) a further instruction or data, or
(ii) a Status or data Reply.
Control and configuration is by writing instructions from the
µController to the Control Register (60H).
Reporting of FX802 configurations is by reading the Status
Register (61H). Instructions and data are transferred, via
“C-BUS,” in accordance with the timing information given in
Figures 5 and 6.
A complete list of DBS 800 “C-BUS” Address locations is
published in the System Support Document.
The delta encoder and decoder sampling rates are
independently set, via the Control Register (Table 4), to
(nominally) 16, 25, 32, 50 or 64kbits/s (see Tables 2 and 3),
allowing the user to choose between speech-quality and
storage-time, whilst providing for time-compression or
expansion of the speech signals.
The DVSR Codec can handle from 256kbits to 4Mbits of
DRAM, giving, in the case of 32kbit/s sampling rate, from 8
to 131 seconds of speech storage.
For speech storage purposes, the memory is divided into
'pages' of 1024 bits each, corresponding to 32ms at a
32kbit/s sampling rate.
A 256kbit DRAM contains
256 pages.
A 1Mbit DRAM contains
1024 pages.
4Mbit of DRAM contains
4096 pages.
The Delta Codec may be used without DRAM, when the
decoder sampling rate (8 to 64 kbits/s) is determined by an
external clock source applied to the Decoder Clock pin.
Operation with DRAM
Store and Play Speech Commands
Speech storage and playback may take place
simultaneously.
These commands are transmitted, via “C-BUS,” to the
FX802, in the form:
The FX802 can operate with up to 4Mbits of DRAM. When
used with DRAM the DVSR Codec performs four main
functions under the control of commands received over the
“C-BUS” interface from the µController:
Stores Speech by digitally encoding the analogue input
signal and writing the resulting digital data into the
associated Dynamic RAM (DRAM).
Plays stored speech by reading the digital data stored in the
DRAM and decoding it to provide an analogue output
signal.
Writes data sent over the “C-BUS” from the µController to
DRAM.
Reads data from DRAM, sending it to the µC over the
“C-BUS”.
STORE or PLAY ‘N’ (1024-bit) pages (of encoded
speech data) starting at page ‘X.’
‘N’ is any number from 1 to 16 (pages) and ‘X’ from (page) 0
to 4095 (4Mbit DRAM), as illustrated below.
Preceded by the A/C, this command writes 16-bits (byte 1
(first) and byte 0) of data from the µC to the FX802 Store or
Play Command Buffer.
MSB
‘Data’ is directed to and from DRAM by the on-chip DRAM
Controller.
Byte 1
15 14 13 12 11 10 9
‘N’
5
Byte 0
8
7
6
5
‘X’
4
3
LSB
2
1
0
Controlling Protocol ......
Store and Play Speech
Speech Store Commands
62H
63H
The IRQ output is cleared by reading the Status Register.
STORE ‘N’ PAGES – START PAGE ‘X’
(immediate).
STORE ‘N’ PAGES – START PAGE ‘X’
(buffered).
61H
READ STATUS REGISTER
(Table 6).
The digitised speech from the Delta Encoder is stored
in consecutive DRAM locations with the Speech Store
Counters sequencing through the DRAM addresses and
counting the number of complete ‘pages’ stored since the
start of execution of the command.
As soon as the command has terminated the following
events take place:
(1) The “Store Command Complete” bit in the Status
Register (Table 6) is set.
(2) An “Interrupt Request” (IRQ) is sent (if enabled) to
the µC.
(3) The next Speech Store command (if present) is
immediately taken from the Store Command
Buffer and execution of the new command
commences.
To provide continuity of speech commands, both Store
and Play commands can be presented to the FX802 in
one of two formats; Immediate or Buffered.
An Immediate command will be started on completion
of its loading, irrespective of the condition of the current
command.
A Buffered command will be acted upon on the
completion of the current Store or Play command, unless
Speech Synchronization Bits (Control Register) are set.
Buffering of commands lets the DVSR Codec execute
a series of commands without intervening gaps, even
though the µController may take several milliseconds to
respond to each “Command Complete” Interrupt
Request.
In either case, the Store or Play Command Complete
bit of the Status Register will be cleared.
Speech Playback is controlled by similar commands:
Store/Play Speech Synchronization – (Table 4)
64H
65H
PLAY ‘N’ PAGES – START PAGE ‘X’
(immediate).
PLAY ‘N’ PAGES – START PAGE ‘X’
(buffered).
This facility is provided, primarily, for Time Domain
Scrambling applications.
Speech Synchronization bits in the Control Register
will produce the effects described below:
using the Speech Play Counters and Play Command
Buffer.
As soon as the Play Command has completed, the
“Play Command Complete” bit in the Status Register is
set and an Interrupt Request generated (if enabled).
If no 'next' command is waiting in the Play Command
Buffer when a speech Play command finishes,
a continuous idle code (0101.....0101) will be fed to the
Delta Decoder.
Speech “data” is stored or recovered at the selected
Encode or Decode sample rate (Table 3).
Store or Play Command Complete bits in the Status
Register are cleared by the next Store or Play command
received from the µC, or by a General Reset command.
No Speech Sync Set; Store and Play operations may
take place completely independently.
Store after Play; The next “buffered” Store command
will start on completion of a Play operation, whilst the
next Play command (if any) sequence continues
normally.
Play after Store; The next “buffered” Play command will
start on completion of a Store operation, whilst the next
Store command (if any) sequence continues normally.
These actions will continue whilst ‘Speech Sync’ bits
remain set.
DRAM Speech Capacity
28-pin/lead versions of the FX802 may be used with a single 256kbit DRAM or with up to 4 x 1Mbit DRAM.
24-pin/lead versions may only be used with a single 256kbit or 1Mbit DRAM. The different Encode and Decode
sampling clock rates available enable the user to set voice store and play times against recovered speech quality.
Table 2 gives information on storage capacity and Store/Playback times. Speech data can be replayed at a different
sample rate or in a reverse sequence, see Control Register for details.
DRAM
Size
Available
Bits
“Speech
Pages”
16
256kbits
1024k
262144
1048576
256
1024
16.0
65.0
Nominal Sample Rates (kbits/s)
25
32
50
64
10.0
42.0
8.0
32.0
5.0
20.0
4.0
16.0
2Mbits
2097152
2048
131.0
84.0
65.0
42.0
32.0
3M
3145728
3072
196.0
126.0
98.0
63.0
49.0
4M
4194304
4096
262.0
168.0
131.0
84.0
65.5
Store and Play Times (seconds)
Table 2 Sampling Clock Rates vs Speech Storage/Playback Times
6
Controlling Protocol ......
Data Operations
Data Storage and Recovery
“C-BUS” Data Transfer Limitations
For the purpose of storing data sent via “C-BUS” from the
µC, the memory (DRAM) is divided into ‘data-pages’ of
64-bits (8-bytes).
For those commands which transfer data over the
“C-BUS” between DRAM and the µController (Write and
Read Data) the “C-BUS” Serial Clock rate is limited to a
maximum of:
125kHz if the VSR Codec is executing Store and
Play commands.
250kHz if no speech Store or Play commands are
active.
All other commands and replies (Control, Status,
General Reset) may use a maximum clock rate of
500kHz. See Figure 5.
A single 256kbit DRAM contains
4096 data-pages.
A single 1Mbit DRAM contains
16384 data-pages.
4Mbit DRAM contains
65536 data-pages.
In accordance with “C-BUS” timing specifications, data
is handled 8-bits (1-byte) at a time although any number
of 8-bit blocks of data may be written-to or read-from the
DRAM by a single command.
The data transfer action is terminated by the Chip
Select line being taken to a logic “1.
Read and Write Data actions are explained below
Write Data
Read Data
66H
READ DATA – START PAGE “P”
67H
Sets the Data Read Counter to “P” page and then
reads data bytes from successive DRAM locations,
sending them to the µC as Reply Data bytes
incrementing the Data Read Counter by 1 for each bit
read.
Sets the Data Write Counter to “P” page and then
writes data bytes to successive DRAM locations,
incrementing the Data Write Counter by 1 for each bit
received via the “C-BUS.”
The Start Page “P,” is indicated by loading a 2-byte
word after the relevant Address/Command byte. This
16-bit word allows data-page addresses from 0 to 65535
(4Mbits DRAM).
READ DATA – CONTINUE
69H
WRITE DATA – START PAGE “P”
Reads data bytes from successive DRAM locations
determined by the Data Read Counter incrementing the
counter by 1 for each bit read.
68H
WRITE DATA – CONTINUE
Writes data bytes to successive DRAM locations
determined by the Data Write Counter, incrementing the
counter by 1 for each bit received over the “C-BUS.”
Encoder and Decoder Sampling Clocks
Encoder and decoder sampling clock rates are programmable via the Control Register. Table 3 shows the range of
sampling rates available for differing Xtal/clock input frequencies, and the counter ratios used to produce them.
If different “Store and Play” sampling rates are used in a single operation, only combinations of 25kb/s with 32kb/s or
50kb/s with 64kb/s will give correct output levels in accordance with current specifications. Consideration should be given
to the effect of differing Xtal/clock frequencies upon the audio frequency performance of the device.
Xtal/clock Frequency (MHz)
Control Register
Byte 0, Bits
5
4
3 Dec.
2
1
0 Enc.
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
4.0
Internal Counter
Division
Ratio
256
160
128
80
64
4.032
4.096
Sampling Rate
(kbits/s)
15.625
25.0
31.25
50.0
62.50
15.75
25.20
31.50
50.4
63.0
16.0
25.60
32.0
51.20
64.0
Table 3 Sampling Clock Rates Available
With respect to using a single Xtal/clock frequency for all DBS 800 devices in use it should be noted that:
(a) a 4.032MHz Xtal/clock input will produce an accurate 1200 baud rate for the FX809 FFSK Modem
(b) a 4.096MHz Xtal/clock input will generate exactly 16kb/s and 32kb/s Codec sampling clock rates.
7
“Write to Control Register” –
Setting
Address/Command 60H, followed by 2 bytes of Command Data
Byte 1
Upon Power-Up the “bits” in the FX802 registers will be
random (either “0” or “1”). A General Reset command (01H)
will be required to “reset” all microcircuits on the “C-BUS,”
and has the following effect upon the FX802:
Control Register
Set as 00H
Status Register
Set as 00H
Clear Store and Play Command Buffers
First Byte for Transmission
(MSB)
Bit 7
Not used – Set to “0”
6
1
0
Direct Access
– Encoder Data Out to A0/ENO
– Encoder Clock to A3/ECK
– Decoder Input from A1/DEI
– Decoder Clock from A2/DCK
Normal DVSR Operation
5
1
0
Play Counter
Decrement
Increment
4
1
0
DRAM Control
Disable DRAM
Enable DRAM
3
1
0
Codec Powersave
Powersave Delta Codec
Enable Delta Codec
2
1
0
Store Command Interrupt
Enable Interrupt
Disable
1
1
0
Play Command Interrupt
Enable Interrupt
Disable
0
1
0
Power Reading Interrupt
Enable Interrupt
Disable
Byte 0
(MSB)
7
0
0
1
1
General Reset
Function
Direct Access
Allows external circuitry “Direct Access” to the Delta Codec
data and sampling clocks, disabling the DRAM timing
circuitry. This permits the Delta Codec section of the FX802
to be used as a “stand-alone” delta modulation voice
encoder and decoder.
Input Audio is encoded and made available at the
Encoder Out (ENO) pin. Speech data input to the Decoder
In (DEI) pin is decoded to give voice-band audio at the
Audio Output.
The following points, with respect to Control Register
settings, should be considered. Analogue output switching
remains under the control of the Control Register, but the
Decoder sampling clock rate (8kbit/s to 64kbit/s) must be
provided from an external source to the Decoder Clock
(DCK) pin. To ensure correct filter setting, Decoder Control
bits (Byte 0, Bits 5, 4, 3) should be set to (binary) 1, 1, 1,
where the required rate approximates to a multiple of
16kb/s, or (binary) 1, 1, 0, where the required rate
approximates to a multiple of 25kb/s.
Both the Encoder internal sampling clock rate and
input switching (Table 5) remain under the control of the
Control Register. The sampling clock rate is available to
external circuitry at the Encoder Clock Out (ECK) pin.
Play Counter
The Play Counter direction may be set to run backwards as
well as forwards. This can be used in a scrambling system
by replaying speech data in reverse order.
Last Byte for Transmission
6
0
1
0
1
DRAM Control
A logic “1” will disable the DRAM Control timing
circuits and associated counters. The “C-BUS” Interface,
Clock Generator, Delta Codec and filters remain active.
This bit should be set to logic “1” when the FX802 is used in
the Direct Access mode.
Minimum DVSR Codec power consumption is
achieved by setting both DRAM Control and Powersave
bits to a logic “1.”
Store/Play Speech Sync
No Sync
No Sync
Sync – Play after Store
Sync – Store after Play
5
0
0
0
0
1
1
1
1
4
0
0
1
1
0
0
1
1
3
0
1
0
1
0
1
0
1
Decoder Control
Idle (32kbit/s); Aud O/P via L.P.F.
Idle (32kbit/s); Aud By-Pass
Idle (32kbit/s); Aud O/P at High Z
On – Sampling Rate 16kbit/s
On –
"
25kbit/s
On –
"
32kbit/s
On –
"
50kbit/s
On –
"
64kbit/s
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Encoder Control
– F/Idle (32kbit/s)
I/P at VBIAS
I/P at High Z – F/Idle (32kbit/s)
I/P at High Z – F/Idle (32kbit/s)
On – Sampling Rate 16kbit/s
On –
"
25kbit/s
On –
"
32kbit/s
On –
"
50kbit/s
On –
"
64kbit/s
Codec Powersave
A logic “1” puts the Delta Codec and filters into a
Powersave mode, with VBIAS maintained.
The Clock Generator, “C-BUS” Interface and DRAM
Control and Timing remain active.
Command Interrupt Enable
A logic “1” set at the relevant bit will enable Interrupt
Requests to the µController when that command operation
is complete.
Store and Play Speech Synchronization
Intended, primarily, for Time Domain Scrambling.
Decoder and Encoder Control
Sets individually, decoder and encoder sampling clock
rates and the source of the Audio Output.
Table 4 Control Register
8
Encoder and Decoder Control
Analogue Input and Output Switching
The Control Register, Byte 0 – bits 0 to 5, are used, in conjunction with the codec Powersave Bit (Byte 1 – bit 3) to control codec
input/output conditions and sample rates. Figure 3 shows the codec functional situation.
AUDIO IN
AUDIO OUT
MOD
DEMOD
CVSD Codec
INPUT
BIAS
200kΩ
(nom)
AUDIO
BYPASS
V
VBIAS
BIAS
500kΩ
(nom)
OUTPUT
BIAS
Fig.3 Analogue Control – with reference to Fig.1
Control Register
Codec
Decoder
Powersave
Control
Bit
“5”
“4”
0
0
0
0
0
0
0
0
1
0
0
1
–
–
–
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
–
–
–
1
1
1
Encoder
Control
“2”
“1”
0
0
0
0
0
0
0
0
1
0
0
1
–
–
–
0
1
1
1
0
0
–
–
–
1
1
1
Circuit Switches
“3”
0
1
0
1
–
1
0
1
0
1
–
1
OFF
ON
=
=
Switch Open
Switch Closed
Audio
By-Pass
Audio
Out
Output
Bias
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
Decoder ‘idling’ fed with “1010101
....” pattern at 32kb/s.
1
OFF
–
OFF
ON
–
ON
OFF
–
OFF
Decoder running at the selected
sampling rate.
1
OFF
ON
OFF
OFF
–
OFF
OFF
OFF
OFF
OFF
–
OFF
ON
OFF
ON
ON
–
ON
Decoder circuits Powersaved
“0”
0
1
0
1
–
1
0
–
1
Note
Input
Bias
2
ON
OFF
OFF
Encoder running at 32kb/s but
Encoder Data Output forced to ‘idle’
pattern “01010 ...”
OFF
–
OFF
Encoder running at selected
Sampling Rate
ON
–
Encoder circuits Powersaved
ON
Table 5 Analogue Control – with reference to Fig.3
Notes
1. If the Delta Codec is in the Direct Access mode, these
sampling rates will be as provided by the externally
applied clock.
relatively low impedance path for VBIAS to charge the input
coupling capacitor whenever the codec is powersaved, or the
Encoder control bits are set to “0,” so that input bias can be
established quickly prior to operation.
2. The Input Bias switch is operated by the Control Register
Codec Powersave’ and ‘Encoder Control’ bits to provide a
Time Compression of Speech
at 64kb/s and playing out at 50kb/s. A similar result (with a
degraded SINAD) may be achieved by using 25kb/s and
32kb/s sampling rates.
However, the speech frequencies are raised by time
compression, and since the signal transmitted to air must be
band limited to 3400Hz, the effective end-to-end bandwidth
is 0.8 x 3400Hz, which is approximately 2700Hz.
The 25kb/s and 50kb/s sampling rate options are provided
for time compression (and subsequent expansion) of speech
signals.
For example, 1.0 second of speech stored at 50kb/s may
be transmitted in 0.8 seconds if played out at 64kb/s, and
finally restored to its original speed at the receiver by storing
9
“Read Status Register”
Function
Reading
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
– Address/Command, 61H, followed by 1 byte of Reply Data.
MSB
Bit 7
1
Power Reading
Ready
6
1
Store Command
Complete
5
1
Play Command
Complete
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupts
An Interrupt Request (IRQ), (if enabled by the Control
Register) is produced by the FX802 to report the following
actions:
Power Reading Ready
Store Command Complete
Play Command Complete.
When an Interrupt Request is produced the Status Register
must be read to ascertain the source of the interrupt. This
action will clear the IRQ output.
Store Command Complete bit
(and an interrupt) is set on completion of a Store command.
This bit is cleared by loading the next Store command, or by
a General Reset command (01H).
Power Register
Compand Bits/page
0
1
2
3
4
5
6
7
-39.0 dB
8
10
-36.0
12
14
-33.5
16
18
-30.0
20
22
-28.0
24
32
-25.0
40
48
-22.0
56
64
-19.0
72
80
-16.0
88
128
-10.0
192
256
-6.0
320
384
0dB
448
512
Pwr
Play Command Complete bit
(and an interrupt) is set on completion of a Play command.
This bit is cleared by loading the next Play command, or by a
General Reset command (01H).
Power Reading Ready bit
(and an interrupt) is set for every 1024 (1 page) voice-data
bits from the Encoder. This bit is cleared after reading the
Status Register, or by a General Reset command (01H).
Power Register
The power assessment element shown in Figure 1 assesses
the input signal power for each encoded ‘page’ (every 1024
encoder output bits) by counting the number of 'compand
bits' (000 or 111 sequences in the output bit-stream)
produced during that ‘page,’ shown in Table 6, with typical
encoder input power levels (dB).
Power Reading measurements (Bits 0 – 4) are produced
under the same conditions as in Figure 4.
At the end of each ‘page’ the “Power Reading Ready” bit of
the Status Register is set, an Interrupt Request is generated
(if enabled) and the resulting count converted to a 5-bit
quasi-logarithmic form.
The Power Register reading is interpreted as below.
00000 represents
00001 represents
11111 represents
0 compand bits
1 compand bit
512 compand bits
– the maximum.
This “Power” reading is placed in the Status Register
where it can be read by the µC.
Figure 4 shows this output in graphical form, indicating the
typical Input Power Level.
Table 6 Status Register
5-Bit Power Reading
(Status Register – bits 0 to 4)
30
20
Input Frequency
= 1.0kHz
Sample Clock Rate = 32kb/s
0dB Ref:
= 308mVrms
10
308mVrms
0
-50
-40
-30
-20
Fig.4 Typical “Power” Readings vs Input Level
10
-10
0dB
5.0
Average Input ‘Power Level’ (dB )
Timing Information
t CSOFF
CHIP SELECT
t CSE
t NXT
t NXT
SERIAL CLOCK
t CSH
t CK
COMMAND DATA
7
6
5
4
3
2
1
MSB
0
7
6
ADDRESS/COMMAND
BYTE
REPLY DATA
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
LSB
FIRST DATA BYTE
LAST DATA BYTE
t HIZ
7
6
5
4
3
2
1
0
MSB
7
6
4
3
2
LSB
FIRST REPLY DATA BYTE
Logic level is not important
5
LAST REPLY DATA BYTE
Fig.5 “C-BUS” Timing Information
NOT TO SCALE
Direct Access Timing – Figure 6
“C-BUS” Timing – Figure 5
Parameter
Min.
Max.
Parameter
Unit
tCSE
a
2.0
b
4.0
c
8.0
–
µs
tCSH
tHIZ
tCSOFF
tNXT
tCK
4.0
–
2.0
4.0
2.0
4.0
–
4.0
8.0
4.0
8.0
–
8.0
16.0
8.0
–
2.0
–
–
–
µs
µs
µs
µs
µs
Min.
Typ
Max.
Unit
–
–
–
–
750
µs
µs
ns
ns
ns
tCH
1.0
–
tCL
1.0
–
450
–
tSU
tH
600
–
tPCO
–
–
tSU + tH = Data True Time
Notes
(1) Minimum Timing Values
(a) For all commands except “Read Data” and “Write Data” commands.
(b) For “Read Data” and “Write Data” commands when no “Speech Store” or “Speech Play” commands are active.
(c) For “Read Data” and “Write Data” commands when “Speech Store” or “Speech Play” commands are active.
(2) Depending on the command, 1 or 2 bytes of Command Data are transmitted to the peripheral MSB (bit7) first, LSB
(bit0) last. Reply Data is read from the peripheral MSB (bit7) first, LSB (bit0) last.
(3) To allow for differing µController serial interface formats “C-BUS” compatible ICs are able to work with either polarity
Serial Clock pulses.
(4) Data sent from the µController is clocked into the FX802 on the rising edge of the Serial Clock pulses. Reply Data
sent from the FX802 to the µController is clocked into the µController when the Serial Clock is “high.”
(5) Loaded commands are acted upon at the end of each command.
Direct Access
ENCODER TIMING
DECODER TIMING
t CH
t CL
t CH
ENCODER CLOCK
t CL
DECODER CLOCK
t PCO
Data Clocked
ENCODER DATA
BITS OUT
DECODER DATA
BITS IN
t SU
t
H
Data True Time
Data Clocked
Fig.6 Codec Direct Access Timing
NOT TO SCALE
11
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied.
Supply voltage
-0.3 to 7.0V
Input voltage at any pin (ref VSS = 0V)
-0.3 to (VDD + 0.3V)
Sink/source current (supply pins)
+/- 30mA
(other pins)
+/- 20mA
Total device dissipation @ TAMB 25°C
800mW Max.
Derating
10mW/°C
Operating temperature range:
FX802J
-40°C to +85°C (cerdip)
FX802LG/LS
-40°C to +85°C (plastic)
Storage temperature range:
FX802J
-55°C to +125°C (cerdip)
FX802LG/LS
-40°C to +85°C (plastic)
Operating Limits
All device characteristics are measured under the following conditions unless otherwise specified:
VDD = 5.0V. TAMB = 25°C. Xtal/Clock f0 = 4.0MHz. Standard Test Signal fo = 1.0kHz. Sample Rate = 31.25kbits/s
Audio Level 0dB ref: = 308mVrms .
Characteristics
Static Values
Supply Voltage (VDD)
Supply Current (enabled)
Supply Current (all powersaved)
Digital Interface
Input Logic “1”
Input Logic “0”
Output Logic “1”
at IOH = -120µA
at IOH = -50µA
at IOH = 20µA
Output Logic “0”
at IOL = 20µA
at IOL = 100µA
at IOL = 360µA
Digital Input Current
(VIN = Logic “1” or “0”)
Leakage Current into IRQ “OFF” Output
Digital Input Capacitance
Analogue Impedance
Input Impedance
Output Impedance
Dynamic Values
Encoder
Analogue Signal Input Levels
Passband
Decoder
Analogue Signal Output Levels
Passband
Encoder/Decoder (Full Codec)
Passband
Passband Gain
Passband Ripple
Stopband
Stopband Attenuation
SINAD Level (-6dB)
Output Noise (Input short circuit)
Idle Channel Noise (Forced )
Xtal/clock Frequency
Notes
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
See Note
Min.
Typ.
Max.
Unit
1
1
4.5
–
–
5.0
7.0
1.0
5.5
–
–
V
mA
mA
2, 4
2, 4
3.5
–
–
–
–
1.5
V
V
8, 4
3, 4
4, 10
4.6
4.6
4.6
–
–
–
–
–
–
V
V
V
4, 10
3, 4
4, 8, 9
–
–
–
–
–
–
0.4
0.4
0.4
V
V
V
2
5
2
–
–
–
–
–
–
1.0
4.0
7.5
µA
µA
pF
13
–
–
500
1.5
–
–
kΩ
kΩ
6
11, 12
-24.0
–
–
3400
4.0
–
dB
Hz
6
11, 12
-24.0
300
–
–
4.0
3400
dB
Hz
11, 12
12
12
300
–
-3.0
6.0
–
–
–
–
–
0
–
–
50.0
23.0
-50
-55
4.0
3400
–
3.0
10
–
–
–
–
–
Hz
dB
dB
kHz
dB
dB
dBp
dBp
MHz
7
Does not include current drawn by any attached DRAM.
Serial Clock, Command Data, CS, A1/DEI and A2/DCK inputs.
CAS, WE and A0 to A9 outputs.
All measurements are made at 5.0 volts VDD, any variations may alter parameters accordingly.
When the IRQ Output is at VDD.
The optimum range of levels for a good Signal-to-Noise Ratio.
Audio frequency responses will vary with respect to Xtal/clock frequency.
Reply Data output.
IRQ output.
RAS Outputs.
Passband is reduced to (typically) 2700Hz when a sample rate of 25kb/s or 50kb/s is employed.
Measured with a -20dB input level to avoid codec slope-overload.
For optimum noise performance this input should be driven from a source impedance of less than 100Ω.
12
Codec Performance
+ 10
Gain (dB)
0dB
0
- 10
Input 0dB Ref: = 308mVrms
Input Level
- 20
= -20dB
Sample Rates = 16, 32 or 63kb/s
- 30
- 40
- 50
- 60
0
1
0.2
2
3
4
5
6
Frequency (kHz)
Fig.7 Typical Overall (Encoder + Decoder) Frequency Response
SINAD
(dB)
SINAD
(dB)
64kb/s
30
30
50kb/s
600Hz
20
20
32kb/s
1000Hz
25kb/s
1500Hz
Sample Rate = 32kb/s
0dB Ref:
= 308mVrms
Input Frequency = 1.0kHz
0dB Ref:
= 308mVrms
Input Level (dB
Input Level (dB)
10
10
-30
-24
-18
-12
-6
0
-30
Fig.8 SINAD vs Input Level at Differing Sample Rates
+ 10
-24
-18
-12
-6
0
Fig.9 SINAD vs Input Level at Differing Frequencies
Gain (dB)
0dB
0
- 10
Input 0dB Ref: = 308mVrms
Input Level
- 20
= -20dB
Sample Rates = 25 or 50kb/s
- 30
- 40
- 50
- 60
0
0.2
1
2
3
4
5
6
Frequency (kHz)
Fig.10 Typical Overall (Encoder + Decoder) Frequency Response
13
Package Outlines
Handling Precautions
The FX802 is available in the package styles outlined
below. Mechanical package diagrams and specifications
are detailed in Section 10 of this document.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.
The FX802 is a CMOS LSI circuit which includes input
protection. However precautions should be taken to
prevent static discharges which may cause damage.
FX802J
FX802LG 24-pin quad plastic encapsulated
bent and cropped
(L1)
28-pin cerdip DIL
(J5)
NOT TO SCALE
NOT TO SCALE
Max. Body Length
Max. Body Width
37.05mm
13.36mm
Max. Body Length
Max. Body Width
FX802LS
10.25mm
10.25mm
24-lead plastic leaded chip carrier
(L2)
NOT TO SCALE
Ordering Information
FX802J
28-pin cerdip DIL
(J5)
FX802LG
24-pin encapsulated bent and
cropped
(L1)
FX802LS
24-lead plastic leaded chip
carrier
(L2)
Max. Body Length
Max. Body Width
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.
10.40mm
10.40mm