Fujitsu MB91V350A 32-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16504-3E
32-Bit Proprietary Microcontroller
CMOS
FR60 MB91350A Series
MB91F355A/F356B/355A/354A/V350A
■ DESCRIPTION
The FR families are lines of standard single-chip microcontrollers each based on a 32-bit high-performance RISC
CPU, incorporating a variety of I/O resources and bus control features for embedded control applications which
require high CPU performance for
This FR60 family is based on FR30 and FR40 families and enhanced is bus access. The FR60 family is a line of
single-chip oriented microcontrollers incorporating a wealth of peripheral resources.
The FR60 family is optimized for embedded control applications requiring high processing power of the CPU,
such as DVD player, navigation, high performance Fax machine, and printer controls.
■ FEATURES
1. FR CPU
•
•
•
•
32-bit RISC, load/store architecture with a five-stage pipeline
Maximum operating frequency: 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz)
16-bit fixed length instructions (basic instructions), 1 instruction per cycle
Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift
etc.
• Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store instructions
(Continued)
■ PACKAGE
176-pin plastic LQFP
(FPT-176P-M02)
I2C license
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system
provided that the system conforms to the I2C Standard Specification as defined by Philips.
MB91350A Series
• Register interlock functions: Facilitating coding in assemblers
• On-chip multiplier supported at the instruction level.
Signed 32-bit multiplication: 5 cycles.
Signed 16-bit multiplication: 3 cycles
• Interrupt (PC, PS save): 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• FR family instruction compatible
2. Bus Interface
•
•
•
•
•
•
•
•
•
•
•
Maximum operating frequency: 25 MHz
Capable of up to 24-bit address full output (16 MB of space)
8,16-bit data output
Built-in pre-fetch buffer
Non-used data and address pin are usable as general I/O port.
Capable of chip-select signal output for completely independent four areas settable in 64 KB minimum
Support for various memory interfaces:
SRAM, ROM/Flash,
page mode Flash ROM, page mode ROM
Basic bus cycle: 2 cycles
Programmable automatic wait cycle generator capable of inserting wait cycles for each area
RDY input for external wait cycles
Support for fly-by transfer for DMA, which enables wait control of independent I/O
3. Mounted Memory
Memory
ROM
RAM (stack)
RAM (executable)
MB91V350A
No
16 KB
16 KB
MB91F355A
512 KB
16 KB
8 KB
MB91F356B
256 KB
16 KB
8 KB
MB91355A
512 KB
16 KB
8 KB
MB91354A
384 KB
8 KB
8 KB
4. DMAC (DMA Controller)
• Capable of simultaneous operation of up to 5 channels (3 channels for external→external operation)
• Three transfer sources (external pin, internal peripheral, software) selectable by software. (Transfer can be
started from UART0/1/2.)
• Addressing using 32-bit full addressing mode (increment, decrement, fixed)
• Transfer modes (demand transfer, burst transfer, step transfer, block transfer)
• Support for fly-by transfer (between external I/O and memory)
• Selectable transfer data size: 8, 16, or 32-bit
• Multi-byte transfer enabled (by software)
• DMAC descriptor in IO areas (200H to 240H, 1000H to 1024H)
5. Bit Search Module (for REALOS)
• Search for the position of the bit 1/0-changed first in 1 word from the MSB
6. Various Timers
• 4 channels of 16-bit reload timer (including 1 channel for REALOS):
Internal clock frequency selectable from among divisions by 2/8/32 (division by 64/128 selectable only for ch3)
• 16-bit free-running timer: 1 channel.
Output compare module: 8 channels. Input capture module: 4 channels
• 16-bit PPG timer 6 channels
7. UART
• UART Full duplex double buffer 5 channel
• Selectable parity On/Off
• Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable
(Continued)
2
MB91350A Series
(Continued)
• Internal timer for dedicated baud rate
• External clock can be used as transfer clock
• Assorted error detection functions (for parity, frame, and overrun errors)
• 115 Kbps support
8. SIO
• 3 channels for 8-bit data serial transfer
• Shift clock selectable from among internal three and external one
• Shift direction selectable (transfer from LSB or MSB) selectable
9. Interrupt Controller
• Total of 17 external interrupt lines (1 nonmaskable interrupt pin and 16 normal interrupt pins available for Wake
Up from STOP)
• interrupt from internal peripheral
• Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt
10. D/A Converter
• 8-bit resolution. 3 channels
11. A/D Converter
•
•
•
•
10-bit resolution. 12 channels
Casting time for serial/parallel conversion: 1.48 µs
Conversion mode (single conversion mode, continuous conversion mode)
Activation source (software, external trigger, peripheral interrupt)
12. Other Interval Timer/Counter
• 8/16-bit up/down counter
• 16-bit PPG timer 5 channels
• Watch dog timer
13. I2C Bus Interface (400 Kbps supported)
• 1channel master/slave sending and receiving
• Arbitration and clock synchronization
14. I/O Port
• 3 V I/O ports (16 ports shared for external interrupts support 5 V input.)
• Max 126 ports
15. Other Features
• Internal oscillator circuit as clock source, allowing PLL multiplication to be selected
• Provided with INIT as a reset pin (The CPU operates without oscillation stabilization wait interval when the
INIT pin is reset.)
• others, watch-dog timer reset, software reset enable
• Support for stop and sleep modes for low power consumption, capable of saving power during CPU operation
at 32 kHz.
• Gear function
• Built-in time base timer
• Package: LQFP-176 (lead pitch: 0.50 mm)
• CMOS technology(0.35 µm)
• Power supply voltage: 3.3 V ± 0.3 V
3
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
VSS
VCC
P40/A00
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
P50/A08
P51/A09
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
VSS
VCC
P60/A16
P61/A17
P62/A18
P63/A19
P64/A20
P65/A21
P66/A22
P67/A23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PG4/SO5
PG3/SI5
PG2/SCK4
PG1/SO4
PG0/SI4
PH5/SCK3
PH4/SO3
PH3/SI3
PH2/SCK2
PH1/SO2
PH0/SI2
PI5/SCK1
PI4/SO1
PI3/SI1
PI2/SCK0
PI1/SO0
PI0/SI0
VCC
VSS
PJ7/INT15
PJ6/INT14
PJ5/INT13
PJ4/INT12
PJ3/INT11
PJ2/INT10
PJ1/INT9
PJ0/INT8
PK7/INT7/ATG
PK6/INT6/FRCK
PK5/INT5
PK4/INT4
PK3/INT3
PK2/INT2
PK1/INT1
PK0/INT0
VCC
VSS
PL1/SCL
PL0/SDA
VSS
PM5/SCK7/ZIN1/TRG5
PM4/SO7/BIN1/TRG4
PM3/SI7/AIN1/TRG3
PM2/SCK6/ZIN0/TRG2
MB91350A Series
■ PIN ASSIGNMENT
(TOP VIEW)
PG5/SCK5
NMI
X1A
VSS
X0A
MD2
MD1
MD0
X0
VCC
X1
INIT
VSS
VCC
PC0/DREQ2
PC1/DACK2
PC2/DSTP2/DEOP2
PB0/DREQ0
PB1/DACK0
PB2/DSTP0/DEOP0
PB3/DREQ1
PB4/DACK1
PB5/DSTP1/DEOP1
PB6/IOWR
PB7/IORD
PA0/CS0
PA1/CS1
PA2/CS2
PA3/CS3
VSS
VCC
P80/IN0/RDY
P81/IN1/BGRNT
P82/IN2/BRQ
P83/RD
P84/WR0
P85/IN3/WR1
P90/SYSCLK
P91
P92/MCLK
P93
P94/AS
VSS
VCC
4
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
(FPT-176P-M02)
PM1/SO6/BIN0/TRG1
PM0/SI6/AIN0/TRG0
PN5/PPG5
PN4/PPG4
PN3/PPG3
PN2/PPG2
PN1/PPG1
PN0/PPG0
VCC
VSS
PO7/OC7
PO6/OC6
PO5/OC5
PO4/OC4
PO3/OC3
PO2/OC2
PO1/OC1
PO0/OC0
PP3/TOT3
PP2/TOT2
PP1/TOT1
PP0/TOT0
VCC
VSS
AVSS/AVRL
AVRH
AVCC
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
DA2
DA1
DA0
DAVC
DAVS
MB91350A Series
■ PIN DESCRIPTION
Pin no.
1 to 8
9 to 16
19 to 26
27 to 34
Pin name
D16 to D23
P20 to P27
D24 to D31
P30 to P37
A00 to A07
P40 to P47
A08 to A15
P50 to P57
Circuit
type
C
C
C
C
A16 to A20
37 to 41
P60 to P64
P65 to P67
External data bus bit 16 to bit 23. Enabled in external bus mode.
Available as a port in external bus 8-bit mode.
external data bus bit 24 to bit 31. Enabled in external bus mode.
Usable as port at single chip mode.
Bits 0 to 7 of external address bus. Enabled in external bus mode.
Usable as port at single chip mode.
Bits 8 to 15 of external address bus. Enabled in external bus mode.
Usable as port at single chip mode.
Bits 16 to 20 of external address bus. Enabled in external bus mode.
C
A21 to A23
42 to 44
Description
Available as a port either in single chip mode or with no external address bus in
use.
Bits 21 to 23 of external address bus. Enabled in external bus mode.
C
Available as a port either in single chip mode or with no external address bus in
use.
47 to 48
DA0, DA1
⎯
D/A converter output pin.
49
DA2
⎯
D/A converter output pin.
50 to 57 AN0 to AN7
G
Analog input pin.
58 to 61 AN8 to AN11
G
Analog input pin.
Reload timer output port. This function is enabled when timer output is enabled.
TOT0 to TOT3
67 to 70
PP0 to PP3
D
OC0
71
PO0
Output compare pin.
D
OC1
72
PO1
PO2
D
PO3 to PO7
PN0
General purpose I/O. This function is available as a port when the output compare output is not in use.
Output compare pin.
D
PPG0
81
General purpose I/O. This function is available as a port when the output compare output is not in use.
Output compare pin.
D
OC3 to OC7
74 to 78
General purpose I/O. This function is available as a port when the output compare output is not in use.
Output compare pin.
OC2
73
General purpose input/output port. This function is enabled when the timer output function is disabled.
General purpose I/O. This function is available as a port when the output compare output is not in use.
PPG timer output pin.
D
General purpose I/O. This function is available as a port when the PPG timer output is not in use.
(Continued)
5
MB91350A Series
Pin no.
Pin name
Circuit
type
PPG1
82
PN1
PPG timer output pin.
D
PPG2
83
PN2
PN3
D
PN4
D
PN5
D
General purpose I/O. This function is available as a port when the PPG timer output is not in use.
PPG timer output pin.
D
General purpose I/O. This function is available as a port when the PPG timer output is not in use.
Data input for serial I/O6. Since this input is used as required when serial I/O 6 is
in input operation, the port output must remain off unless intentionally turned on.
SI6
AIN0
87
General purpose I/O. This function is available as a port when the PPG timer output is not in use.
PPG timer output pin.
PPG5
86
General purpose I/O. This function is available as a port when the PPG timer output is not in use.
PPG timer output pin.
PPG4
85
General purpose I/O. This function is available as a port when the PPG timer output is not in use.
PPG timer output pin.
PPG3
84
Description
D
8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on.
TRG0
External trigger input for PPG timer0. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.
PM0
General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use.
SO6
Data output for serial I/O 6. This function is enabled when the serial I/O6 data output is enabled.
BIN0
8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on.
88
D
TRG1
External trigger input for PPG timer1. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.
PM1
General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use.
SCK6
Clock input/output for serial I/O 6. This function is enabled when serial I/O6 is using the external shift clock mode, or serial I/O5 clock output function is enabled.
ZIN0
8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on.
89
D
TRG2
External trigger input for PPG timer2. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.
PM2
General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use.
(Continued)
6
MB91350A Series
Pin no.
Pin name
Circuit
type
Data input for serial I/O 7. Since this input is used as required when serial I/O 7
is in input operation, the port output must remain off unless intentionally turned
on.
SI7
90
AIN1
D
8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on.
TRG3
External trigger input for PPG timer 3. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.
PM3
General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use.
SO7
Data output for serial I/O 7. This function is enabled when the serial I/O 7 data
output is enabled.
BIN1
8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on.
91
D
TRG4
External trigger input for PPG timer 4. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.
PM4
General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use.
SCK7
Clock input/output for serial I/O5. This function is enabled when serial I/O 7 is using the external shift clock mode, or serial I/O 5 clock output function is enabled.
ZIN1
92
D
8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on.
TRG5
External trigger input for PPG timer 5. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.
PM5
General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use.
SDA
Clock input/output pin for I2C bus. This function is enabled when the I2C system
is enabled for operation in standard mode. The port output must remain off unless
intentionally turned on. (Open drain input)
94
F
PL0
General purpose input/output port. This function is available as a port when the
I2C system is disabled for operation. (Open drain input)
SCL
Clock input/output pin for I2C bus. This function is enabled when the I2C system
is enabled for operation in standard mode. The port output must remain off unless
intentionally turned on. (Open drain input)
95
98 to 103
Description
F
PL1
General purpose input/output port. This function is available as a port when the
I2C system is disabled for operation. (Open drain input)
INT0 to
INT5
External interrupt input. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless intentionally turned on.
PK0 to PK5
E
General purpose input/output port.
(Continued)
7
MB91350A Series
Pin no.
Pin name
Circuit
type
External interrupt input. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless intentionally turned on.
INT6
104
E
FRCK
General purpose input/output port.
INT7
External interrupt input. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless intentionally turned on.
ATG
External trigger input for A/D converter. Since this input is used as required when
selected as an A/D activation source, the port output must remain off unless intentionally turned on.
PK7
General purpose input/output port.
E
INT8 to
INT15
E
PJ0 to PJ7
116
SI0
External interrupt input. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless intentionally turned on.
General purpose input/output port.
D
UART0 data input. Since this input is used as required when UART0 is in input
operation, the port output must remain off unless intentionally turned on.
PI0
General purpose input/output port.
SO0
UART0 data output. This function is enabled when the UART0 data output is enabled.
117
D
PI1
General purpose input/output port. This function is enabled when the data output
function of UART0 is disabled.
SCK0
UART0 clock input/output pin. This function is enabled either when clock output
enabled or when UART0 inputs the external clock signal.
118
D
PI2
119
External clock input pin for freerun timer. Since this input is used as required
when selected as the external clock input for the free running timer, the port output must remain off unless intentionally turned on.
PK6
105
106 to
113
Description
SI1
D
General purpose input/output port. This function is enabled when UART0 is not
using the external clock signal with the UART0 clock output function disabled.
UART1 data input. Since this input is used as required when UART1 is in input
operation, the port output must remain off unless intentionally turned on.
PI3
General purpose input/output port.
SO1
UART1 data outpu. This function is enabled when the UART1 data output is enabled.
120
D
PI4
General purpose input/output port. This function is enabled when the data output
function of UART1 is disabled.
SCK1
UART1 clock input/output pin. This function is enabled either when clock output
enabled or when UART1 inputs the external clock signal.
121
D
PI5
General purpose input/output port. This function is enabled when UART1 is not
using the external clock signal with the UART1 clock output function disabled.
(Continued)
8
MB91350A Series
Pin no.
122
Pin name
SI2
SO2
UART2 data outpu. This function is enabled when the UART2 data output is enabled.
D
PH1
General purpose input/output port. This function is enabled when the data output
function of UART2 is disabled.
SCK2
UART2 clock input/output pin. This function is enabled either when the UART2
clock output is enabled or when UART2 inputs the external clock signal.
D
PH2
General purpose input/output port. This function is enabled when UART2 is not
using the external clock signal with the UART2 clock output function disabled.
SI3
UART3 data input. Since this input is used as required when UART3 is in input
operation, the port output must remain off unless intentionally turned on.
D
PH3
General purpose input/output port.
SO3
UART3 data outpu. This function is enabled when the UART3 data output is enabled.
126
D
PH4
General purpose input/output port. This function is enabled when the data output
function of UART3 is disabled.
SCK3
UART0 clock input/output pin. This function is enabled either when the UART3
clock output is enabled or when UART3 inputs the external clock signal.
127
D
PH5
General purpose input/output port. This function is enabled when UART3 is not
using the external clock signal with the UART3 clock output function disabled.
SI4
UART4 data input. Since this input is used as required when UART4 is in input
operation, the port output must remain off unless intentionally turned on.
D
PG0
General purpose input/output port.
SO4
UART4 data output. This function is enabled when the UART4 data output is enabled.
129
D
PG1
General purpose input/output port. This function is enabled when the data output
function of UART4 is disabled.
SCK4
UART4 clock input/output pin. This function is enabled either when the UART4
clock output is enabled or when UART4 inputs the external clock signal.
130
131
UART2 data input. Since this input is used as required when UART2 is in input
operation, the port output must remain off unless intentionally turned on.
General purpose input/output port.
124
128
D
Description
PH0
123
125
Circuit
type
D
PG2
General purpose input/output port. This function is enabled when UART4 is not
using the external clock signal with the UART4 clock output function disabled.
SI5
Data input for serial I/O5. Since this input is used as required when serial I/O5 is
in input operation, the port output must remain off unless intentionally turned on.
D
PG3
General purpose input/output port.
SO5
Data output for serial I/O5. This function is enabled when the serial I/O5 data output is enabled.
132
D
PG4
General purpose input/output port. This function is enabled when the I/O5 data
output function is disabled.
(Continued)
9
MB91350A Series
Pin no.
Pin name
Circuit
type
SCK5
133
D
PG5
Description
Clock innput/output for serial I/O5. This function is enabled when serial I/O5 is
using the external shift clock mode, or serial I/O5 clock output function is enabled.
General purpose input/output port. This function is enabled when serial I/O5 is
not using the external shift clock mode with the serial I/O5 clock output function
disabled.
134
NMI
H
NMI (Non Maskable Interrupt) input
135
X1A
B
Output clock cycle time. Sub clock
137
X0A
B
Input clock cycle time. Sub clock
2 to 0Mode Pins. The levels applied to these pins set the basic operating mode.
Connect VCC or VSS.
Input circuit configuration:
The production model (masked-ROM model) is type “H”.
The Flash ROM model is type “J”.
138 to
140
MD2 to
MD0
H, J
141
X0
A
Input clock cycle time. Main clock
143
X1
A
Output clock cycle time. Main clock
144
INIT
I
External reset input
C
External input for DMA transfer requests. Since this input is used as required
when selected as a DMA start source, the port output must remain off unless intentionally turned on.
147
DREQ2
PC0
General purpose input/output port.
DACK2
148
149
C
PC1
General purpose input/output port. This function is enabled when the transfer request acceptance output for DMA is enabled.
DEOP2
Completion output for DMA external transfer. This function is enabled when the
external transfer end output for DMA is enabled.
DSTP2
C
DREQ0
C
PB0
C
PB1
External input for DMA transfer requests. Since this input is used as required
when selected as a DMA start source, the port output must remain off unless intentionally turned on.
General purpose input/output port.
DACK0
151
Stop input for DMA external transfer. This function is enabled when the external
transfer stop input for DMA is enabled.
General purpose input/output port. This function is enabled when the external
transfer end output and external transfer stop input for DMA are disabled.
PC2
150
External acknowledge output for DMA transfer requests. This function is enabled
when the transfer request acceptance output for DMA is enabled.
External acknowledge output for DMA transfer requests. This function is enabled
when the transfer request acceptance output for DMA is enabled.
General purpose input/output port. This function is enabled when the transfer request acceptance output for DMA is disabled.
(Continued)
10
MB91350A Series
Pin no.
Pin name
Circuit
type
Completion output for DMA external transfer. This function is enabled when the
external transfer end output for DMA is enabled.
DEOP0
152
DSTP0
C
153
C
PB3
C
PB4
DSTP1
General purpose input/output port. This function is enabled when the external
transfer request acceptance output for DMA is disabled.
C
Stop input for DMA external transfer. This function is enabled when the external
transfer stop input for DMA is enabled.
PB5
General purpose input/output port. This function is enabled when the external
transfer end output and external transfer stop input for DMA are disabled.
IOWR
Write strobe output for DMA fly-by transfer. This function is enabled when the
DMA fly-by transfer write strobe output is enabled.
C
156
PB6
General purpose input/output port. This function is enabled when the DMA fly-by
transfer write strobe output is disabled.
IORD
Read storobe output for DMA fly-by transfer. This function is enabled when the
DMA fly-by transfer read strobe output is enabled.
C
157
PB7
158
External acknowledge output for DMA transfer requests. This function is enabled
when the transfer request acceptance output for DMA is enabled.
Completion output for DMA external transfer. This function is enabled when the
external transfer end output for DMA is enabled.
DEOP1
155
External input for DMA transfer requests. Since this input is used as required
when selected as a DMA start source, the port output must remain off unless intentionally turned on.
General purpose input/output port.
DACK1
154
Stop input for DMA external transfer. This function is enabled when the external
transfer stop input for DMA is enabled.
General purpose input/output port. This function is enabled when the external
transfer end output and external transfer stop input for DMA are disabled.
PB2
DREQ1
Description
CS0
PA0
C
CS1
C
159
General purpose input/output port. This function is enabled when the DMA fly-by
transfer read strobe output is disabled.
Chip select 0 output. Enable at external bus mode
General purpose input/output port. This is enabled at single chip mode.
Chip select 1 output. This function is enabled when the chip select 1 output is enabled.
PA1
General purpose input/output port. This function is enabled when the chip select
1 output is disabled.
CS2
Chip select 2 output. This function is enabled when the chip select 2 output is enabled.
160
C
PA2
General purpose input/output port. This function is enabled when the chip select
2 output is disabled.
(Continued)
11
MB91350A Series
Pin no.
Pin name
Circuit
type
CS3
161
164
165
166
C
168
General purpose input/output port. This function is enabled when the chip select
3 output is disabled.
RDY
External ready input. The pin has this function when external ready input is enabled.
IN0
D
General purpose input/output port. This function is enabled when external ready
signal input is disabled.
BGRNT
Acknowledge output for external bus release. Outputs “L” when the external bus
is released. The pin has this function when output is enabled.
IN1
D
Input capture input pin. Since this input is used as required when selected as an
input capture input, the port output must remain off unless intentionally turned on.
P81
General purpose input/output port. This function is enabled when external bus release acknowledge output is disabled.
BRQ
External bus release request input. Input “1” to request release of the external
bus. The pin has this function when input is enabled.
IN2
D
RD
P83
WR0
P84
IN3
D
D
D
General purpose input/output port. This is enabled at single chip mode.
External bus write strobe output. It is available in the external bus mode.
General purpose input/output port. This is enabled at single chip mode.
Input capture input pin. Since this input is used as required when selected as an
input capture input, the port output must remain off unless intentionally turned on.
General purpose input/output port. The pin has this function when the external
bus write-enable output is disabled.
C
System clock output The pin has this function when system clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in stop mode.)
General purpose input/output port. The pin has this function when system clock
output is disabled.
P90
P91
External bus read strobe output. It is available in the external bus mode.
External bus write strobe output. This function is enabled when WR1 output is enabled in external bus mode.
SYSCLK
170
Input capture input pin. Since this input is used as required when selected as an
input capture input, the port output must remain off unless intentionally turned on.
General purpose input/output port. The pin has this function when the external
bus release request input is disabled.
P85
171
Input capture input pin. Since this input is used as required when selected as an
input capture input, the port output must remain off unless intentionally turned on.
P80
WR1
169
Chip select 3 output. This function is enabled when the chip select 3 output is enabled.
PA3
P82
167
Description
C
General purpose input/output port.
(Continued)
12
MB91350A Series
(Continued)
Pin no.
Pin name
Circuit
type
Description
Memory clock output. This function is enabled when the memory clock output is
enabled. This outputs the same clock as the external bus operating frequency.
(Output halts in sleep/stop mode.)
MCLK
172
C
General purpose input/output port. This function is enabled when the memory
clock output is disabled.
P92
173
P93
C
General purpose input/output port.
Address strobe output. This function is enabled when address strobe output is
enabled.
AS
C
174
General purpose input/output port. This function is enabled when address load
output is disabled.
P94
• Power supply and GND pins
Pin no.
Pin name
Description
17, 35, 65, 79, 93, 96,
114, 136, 145, 162, 175
VSS
GND pins. Apply equal potential to all of the pins.
18, 36, 66, 80, 97, 115,
142, 146, 163, 176
VCC
3.3 V power supply pin. Apply equal potential to all of the pins.
45
DAVS
GND pin for D/A converter
46
DAVC
Power supply pin for D/A converter
62
AVCC
Analog power supply pin for A/D converter
63
AVRH
Reference power supply pin for A/D converter
64
AVSS/AVRL
Analog GND pin for A/D converter
13
MB91350A Series
■ I/O CIRCUIT TYPE
Type
Circuit type
Remarks
• Oscillation feedback resistance:
approx. 1 MΩ
X1
Clock input
A
X0
Standby control
X1A
Clock input
B
• Oscillation feedback resistance for
low speed (subclock oscillation):
approx. 7 MΩ
X0A
Standby control
Pull-up control
• CMOS level output
• CMOS level input
Digital output
With standby control
Digital output
C
Digital input
Standby control
With Pull-up control
Pull-up resistance = approx. 50 kΩ
(Typ)
IOL = 8 mA
Pull-up control
• CMOS level output
• CMOS level hysteresis input
Digital output
With standby control
Digital output
D
Digital input
Standby control
With Pull-up control
Pull-up resistance = approx. 50 kΩ
(Typ)
IOL = 4 mA
(Continued)
14
MB91350A Series
Type
Circuit type
Remarks
Digital output
E
• CMOS level output
• CMOS level hysteresis input
Digital output
With stand voltage of 5 V
Digital input
IOL = 4 mA
• Nch open drain output
• CMOS level hysteresis input
Digital output
with standby control
F
Digital input
Standby control
With stand voltage of 5 V
IOL = 15 mA
• Analog input with switch
G
Analog input
Control
• CMOS level hysteresis input
H
Digital input
• CMOS level hysteresis input
with pull-up resistor
Pull-up resistance = approx. 50 kΩ
(Typ)
I
Digital input
(Continued)
15
MB91350A Series
(Continued)
Type
Circuit type
Remarks
• CMOS level input
• Flash product only
J
Control signal
Mode input
Diffused resistor
16
MB91350A Series
■ HANDLING DEVICES
• Preventing Latchup
Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output
pin or if an above-rating voltage is applied between VCC and VSS. A latchup,if it occurs, significantly increases
the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very
careful not to exceed the maximum rating.
• Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor.
• About power supply pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to an external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near
this device.
• About Crystal oscillator circuit
Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the circuit board so that
X0, X1, X0A, X1A, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located
as close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by
ground plane because stable operation can be expected with such a layout.
• Notes on Using External Clock
When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to
X0 must be supplied to X1 pin. However, in this case the stop mode(oscillator stop mode) must not be used.
(This is because the X1 pin stops at High level output in STOP mode.)
Using an external clock (normal)
X0
X1
Note: STOP mode (oscillation stop mode) cannot be used.
• Clock control block
Take the oscillation stabilization wait time during Low level input to the INIT pin.
17
MB91350A Series
• Notes on not using the sub clock
When no oscillator is connected to the X0A and X1A pins, pull down the X0A pin and open the X1A pin.
X0
OPEN
X1
MB91350A
• Treatment of NC and OPEN pins
Pins marked as NC and OPEN must be left open-circuit.
• Mode pins (MD0 to MD2)
These pins should be connected directly to VCC or VSS.
To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low.
• Operation at start-up
The INIT pin must be at Low level when the power supply is turned on.
Immediately after the power supply is turned on, hold the Low level input to the INIT pin for the settling time
required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit. (For INIT
via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.)
• About oscillation input at power on
When turning the power on, maintain clock input until the device is released from the oscillation stabilization
wait state.
• Caution on Operations during PLL Clock Mode
Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the
microcontroller may continue to operate at the free-running frequency of the PLL’s internal self-oscillating oscillator circuit. Performance of this operation, however, cannot be guaranteed.
• External bus setting
This model guarantees an external bus frequency of 25 MHz.
Setting the base clock frequency to 50 MHz with DIVR1 (external bus base clock division setting register)
initialized sets the external bus frequency also to 50 MHz. Before changing the base clock frequency, set the
external bus frequency not exceeding 25 MHz.
• MCLK and SYSCLK
MCLK and SYSCLK has a difference that MCLK stops in SLEEP/STOP mode but SYSCLK stops only in STOP
mode. Use either depending on each application.
Upon initialization, MCLK becomes invalid (PORT) and SYSCLK becomes valid. To use MCLK, set the port
function register (PFR) to select the use of that clock.
• Pull-up control
Connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the “■ ELECTRICAL
CHARACTERISTICS 4. AC Characteristics (4) Normal Bus Access Read/Write Operation, (5) Multiplex Bus
Access Read/Write operation and (7) Hold Timing”.
Even the port for which a pull-up resistor has been set is invalid in stop mode with HIZ = 1 or in hardware standby
mode.
18
MB91350A Series
• Sub clock select
Immediately after switching from main clock mode to subclock mode for the clock source, insert at least one
NOP instruction.
(ldi
#0x0b, r0)
(ldi
#_CLKR, r12)
stb
r0, @r12
// sub-clock mode
nop
// Must insert NOP instruction
• Bit Search Module
The BSD0, BSD1, and BDSC registers are accessed only in words.
• D-bus memory
Do not allocate the code area in memory on the D-bus because no instruction fetch takes place to the D-bus.
Executing an instruction fetch to the D-bus area causes wrong data to be interpreted as code, possibly letting
the device to run out of control.
• Low Power Consumption Mode
To enter the sleep or stop mode, be sure to read the standby control register (STCR) immediately after writing to it.
Precisely, use the following sequence.
Set the I flag, ILM, and ICR to, after returning from standby mode, branch to the interrupt handler having caused
the device to return.
(ldi
#value_of_standby, r0)
(ldi
#_STCR, r12)
stb
r0, @r12
// set STOP/SLEEP bit
ldub
@r12, r0
// Must read STCR
// after reading, go into standby
ldub
@r12, r0
mode
nop
// Must insert NOP *5
nop
nop
nop
nop
• Switch shared port function
To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR). Note,
however, that bus pins are switched depending on external bus settings.
• Pre-fetch
When accessing a prefetch-enabled little endian area, be sure to use word access (in 32-bit, word length) only.
Byte or halfword access results in wrong data read.
• I/O port access
Ports are accessed only in bytes.
• Built-in RAM
Immediately after a reset is canceled, the internal RAM allocation restricting function is still working, allowing
only 4 KB to be used for data and for program execution irrespective of the on-chip RAM capacity.
19
MB91350A Series
• Flash memory
In programming mode, Flash memory cannot be used as an interrupt vector table. A reset is possible.
• Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it
performs operations before and after the EIT as specified in either case.
1. The following operations are performed when the instruction followed by a DIVOU/DIVOS instruction results in:
(a) acceptance of a user interrupt or NMI, (b) single-stepping, or (c) a break at a data event or emulator menu.
• The D0 and D1 flags are updated in advance.
• An EIT handling routine (user interrupt, NMI, or emulator) is executed.
• Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
updated to the same values as in (1).
2. The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed.
• The PS register is updated in advance.
• An EIT handling routine (user interrupt, NMI, or emulator) is executed.
• Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in (1).
20
MB91350A Series
[Note on debugger]
• Step execution of RETI command
If an interrupt occurs frequently during single-stepping, the corresponding interrupt handling routine is executed
repeatedly. This will prevent the main routine and low-interrupt-level programs from being executed. (Whenever
RETI is single-stepped when interrupts by the timebase timer have been enabled, for example, the timebase
timer routine causes a break at the beginning.)
Disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs debugging.
• Break function
If the address at which to cause a hardware break (including a event break) is set to the address currently
contained in the system stack pointer or in the area containing the stack pointer, the user program causes a
break after execution of one instruction.
To prevent this, do not set (word) access to the area containing the address in the system stack pointer as the
target of a hardware break (including an event break).
• Internal ROM area
Do not set an area of internal ROM as a DMAC transfer destination.
• Simultaneous occurrences of a software break (INTE instruction) and a user interrupt/NMI
When an INTE instruction and a user interrupt/NMI are accepted simultaneously, the emulator debugger reacts
as follows.
The emulator debugger stops while indicating a location in the user program, which is not a user-specified
breakpoint. (It stops with the beginning of the user interrupt/NMI handling routine indicated.)
The user program cannot be re-executed correctly.
To prevent this problem, follow the instructions below.
When a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may react as
follows.
• The debugger stops pointing to a location other than the programmed breakpoints.
• The halted program is not re-executed correctly.
If this symptom occurs, use a hardware break in place of a hardware break. When using a monitor debugger,
do not set a break at the relevant location.
• A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data
event break to access to the area containing the address of a system stack pointer.
21
MB91350A Series
■ BLOCK DIAGRAM
FR CPU
32
32
DMAC 5 channels
Bit search
DREQ0 to DREQ2
DACK0 to DACK2
DEOP0/DSTP0 to DEOP2/DSTP2
IOWR
IORD
RAM (Stack)
RAM (Executable)
X0, X1
MD0 to MD2
INIT
Clock
control
A23 to A00
D31 to D16
Bus
Converter
ROM/Flash
32
32
External
memory
I/F
32 ↔ 16
Adapter
RD
WR1, WR0
RDY
BRQ
BGRNT
SYSCLK
X0A, X1A
Clock timer
16
Interrupt
DMAC (DMA
Controller)
16 channels
External interrupt
SI0 to SI4
SO0 to SO4
SCK0 to SCK4
5 channels
UART
4 channels
reload timer
16-bit free-run
timer
5 channels
U-Timer
4 channels
input capture
3 channels
SIO
8 channels
output compare
AN0 to AN11
ATG
AVRH, AVCC
AVSS/AVRL
12 channels
A/D
DA0 to DA2
DAVC, DAVS
3 channels
D/A
1 channel
I2C
ROM/Flash
RAM (Stack)
RAM (Executable)
22
6 channels
PPG
INT0 to INT15
NMI
SI5 to SI7
SO5 to SO7
SCK5 to SCK7
PORT I/F
2 channels
8/16-bit up/down
counter
MB91F355A
512 KB (Flash)
16 KB
8 KB
MB91F356B
256 KB (Flash)
16 KB
8 KB
MB91355A
512 KB
16 KB
8 KB
PORT
TRG0 to TRG5
PPG0 to PPG5
TOT0 to TOT3
FRCK
IN0 to IN3
OC0 to OC7
SDA
SCL
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
MB91354A
384 KB
16 KB
8 KB
MB91350A Series
■ CPU AND CONTROL UNIT
Internal architecture
The FR family CPU is a high performance core based on a RISC architecture while incorporating advanced
instructions for embedded controller applications.
1. Features
•
•
•
•
•
•
•
•
•
RISC architecture employed. Basic instructions: Executed at 1 instruction per cycle
General-purpose registers: 32-bit × 16 registers
4GB linear memory space
Multiplier integrated.
32-bit x 32-bit multiplication: 5 cycles.
16-bit x 16-bit multiplication: 3 cycles
Enhanced interrupt servicing.
Fast response speed (6 cycles).
Multiple interrupts supported.
Level masking (16 levels)
Enhanced I/O manipulation instructions.
Memory-to-memory transfer instructions, Bit manipulation instructions
High code efficiency. Basic instruction word length: 16-bit
Low-power consumption. Sleep mode and stop mode
Gear function
23
MB91350A Series
2. Internal architecture
The FR-family CPU has a Harvard architecture in which the instruction and data buses are separated.
The 32-bit/16-bit bus converter is connected to a 32-bit bus (F-bus), providing an interface between the CPU
and peripheral resources. The Harvard-Princeton bus converter is connected to both of the I-bus and D-bus,
providing an interface between the CPU and the bus controller.
FR CPU
D-bus
I-bus
32
I address
32
External address
24
32
External data
16
Harvard
I data
D address
Data
RAM
D data
32
Address
32
Data
32
32-bit
16-bit
bus converter
Princeton
bus
converter
16
R-bus
Peripherals resource
24
F-bus
Internal I/O
bus controller
MB91350A Series
3. Programming model
• Basic programming model
32-bit
Initial Value:
R0
XXXX XXXXH
R1
GENERAL
PURPOSE
REGISTERS
R12
R13
AC
R14
FP
XXXX XXXXH
R15
SP
0000 0000 H
Program counter
PC
program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiplication and division
result register
MDH
⎯
ILM
⎯
SCR
CCR
MDL
25
MB91350A Series
4. Register
General purpose registers
32-bit
Initial Value:
R0
XXXX XXXXH
R1
R12
R13
AC
R14
FP
XXXX XXXXH
R15
SP
0000 0000 H
Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memory
access pointers for CPU operations.
Of these 16 registers, the registers listed below are intended for special applications, for which some instructions
are enhanced.
R13 : Virtual accumulator
R14 : frame pointer
R15 : Stack pointer
The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 0000 0000H (SSP value).
• PS (Program Status)
This register holds the program status and is divided into the ILM, SCR, and CCR.
The undefined bits in the following illustration are all reserved bits. Reading these bits always returns “0”. Writing
to them has no effect.
Bit position→ 31
20
16
⎯
ILM
SCR
PS
26
10
0
8 7
⎯
CCR
MB91350A Series
• CCR (Condition Code Register )
7
6
5
4
3
2
1
0
Initial Value:
⎯
⎯
S
I
N
Z
V
C
- - 00XXXXB
CCR
S
I
N
Z
V
C
: Stack flag. Cleared to “0” by a reset.
: Interrupt enable flag. Cleared to “0” by a reset.
: Negative flag. The initial value after a reset is indeterminate.
: Zero flag. The initial value after a reset is indeterminate.
: Overflow flag. The initial value after a reset is indeterminate.
: Carry flag. The initial value after a reset is indeterminate.
• SCR (System Condition code Register )
10
9
8
Initial Value:
D1
D0
T
XX0B
SCR
Flag for step dividing
Stores intermediate data for stepwise multiplication operations.
Step trace trap flag
A flag specifying whether the step trace trap function is enabled or not.
Emulator use step trace trap function. The function cannot be used by the user program when using
the emulator.
• ILM
20
19
18
17
16
ILM4 ILM3 ILM2 ILM1 ILM0
Initial Value:
01111B
ILM
This register stores the interrupt level mask value. The value in the ILM register is used as the level mask.
Initialized to “15” (01111B) by a reset.
• PC (Program Counter)
31
0
PC
Initial Value:
XXXXXXXXH
PC
The program counter contains the address of the instruction currently being executed.
The initial value after a reset is indeterminate.
27
MB91350A Series
• TBR (Table Base Register)
31
0
TBR
Initial Value:
0 0 0 FFC0 0 H
TBR
The table base register contains the start address of the vector table used for servicing EIT events.
The initial value after a reset is 000FFC00H
• RP (Return Pointer)
31
0
RP
Initial Value:
XXXXXXXXH
RP
The return pointer contains the address to which to return from a subroutine.
When the CALL instruction is executed, the value in the PC is transferred to the RP.
When the RET instruction is executed, the value in the RP is transferred to the PC.
The initial value after a reset is indeterminate.
• SSP (System Stack Pointer)
31
0
SSP
Initial Value:
00000000H
SSP
The SSP is the system stack pointer and functions as R15 when the S flag is “0”.
The SSP can be explicitly specified.
The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event
occurs.
The initial value after a reset is 00000000H
• USP (User Stack Pointer)
31
0
USP
Initial Value:
XXXXXXXXH
USP
The USP is the user stack pointer and functions as R15 when the S flag is “1”.
The SSP can be explicitly specified.
The initial value after a reset is indeterminate.
This pointer cannot be used by the RETI instruction.
28
MB91350A Series
• Multiply & Divide registers
31
0
MDH
MDL
Multiplication and division result register
These registers hold the results of a multiplication or division. Each of them is 32-bit long.
The initial value after a reset is indeterminate.
29
MB91350A Series
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode.
1. Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.
Mode Pins
MD2 MD1 MD0
Mode name
Reset vector
access area
0
0
0
Internal ROM mode vector
Internal
0
0
1
External ROM mode vector
External
Remarks
The bus width is specified by the mode register.
Values other than those listed in the table are prohibited.
2. Mode Register (MODR)
The data written to the mode register at 000F FFF8H using mode vector fetch is called mode data.
After an operation mode has been set in the mode register (MODR), the device operates in the operation mode.
The mode register is set by any reset source. User programs cannot write data to the mode register.
Note : Conventionally the FR family has nothing at addresses (0000 07FFH) in the mode register.
<Register description>
MODR
000F FFF8H
7
6
5
4
3
2
1
0
0
0
0
0
0
ROMA
WTH1
WTH0
Initial Value
XXXXXXXXB
Operation mode setting bits
[bit 7 to bit 3] Reserved bit
Be sure to set this bit to “00000”. Operation is not guaranteed when any value other than “00000” is set.
[bit 2] ROMA (internal ROM enable bit)
The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas.
30
ROMA
function
Remarks
0
External ROM mode
Internal F-bus RAM is valid; the area (80000H to 100000H) of internal ROM is used
as an external area.
1
Internal ROM mode Internal F-bus RAM and F-bus ROM become valid.
MB91350A Series
[bit 1, bit 0] WTH1, WTH0 (Bus width setting bits)
Used to set the bus width to be used in external bus mode.
When the operation mode is the external bus mode, this value is set in bits BW1 and BW0 in AMD0 (CS0 area).
WTH1
WTH0
function
Remarks
0
0
8-bit bus width
0
1
16-bit bus width
1
0
⎯
Setting disabled
1
1
single chip mode
single chip mode
External bus mode
31
MB91350A Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 GB of logical address space (232 addresses) available to the CPU by linear access.
• Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The size of directly addressable areas depends on the length of the data being accessed as shown below.
→ byte data access
: 000H to 0FFH
→ half word data access : 000H to 1FFH
→ word data access
: 000H to 3FFH
2. Memory Map
• Memory map of MB91F355A/MB91355A
Single chip mode
Internal ROM
external bus mode
External ROM
external bus mode
I/O
I/O
I/O
Direct
addressing area
I/O
I/O
I/O
Refer to “3. I/O Map”
Access
disallowed
Access
disallowed
Access
disallowed
Built-in RAM 8 KB
(Executable)
Built-in RAM 8 KB
(Executable)
Built-in RAM 8 KB
(Executable)
Built-in RAM 16 KB
(Stack)
Built-in RAM 16 KB
(Stack)
Built-in RAM 16 KB
(Stack)
Access
disallowed
Access
disallowed
0000 0000 H
0000 0400 H
0001 0000 H
0003 E000 H
0004 0000 H
0004 4000 H
0005 0000 H
Access
disallowed
External area
0008 0000 H
Built-in RAM
512 KB
Built-in RAM
512 KB
Access
disallowed
External area
External area
0010 0000 H
FFFF FFFFH
• Each mode is set depending on the mode vector fetch after INIT is negated.
• The MB91V350A uses the area of 512 KB of internal ROM as emulation RAM in the MB91355A memory map.
The internal RAM (Instruction) has been expanded from 8 KB to 16 KB.
• The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the
available area is updated, the instruction must be followed by at least 1 NOP instruction.
32
MB91350A Series
• Memory Map of MB91354A
Single chip mode
Internal ROM
external bus mode
External ROM
external bus mode
I/O
I/O
I/O
Direct
addressing area
I/O
I/O
I/O
Refer to “3. I/O Map”
Access
disallowed
Access
disallowed
Access
disallowed
Built-in RAM 8 KB
(Executable)
Built-in RAM 8 KB
(Executable)
Built-in RAM 8 KB
(Executable)
Built-in RAM 8 KB
(Stack)
Built-in RAM 8 KB
(Stack)
Built-in RAM 8 KB
(Stack)
Access
disallowed
Access
disallowed
0000 0000 H
0000 0400 H
0001 0000 H
0003 E000 H
0004 0000 H
0004 2000 H
0005 0000 H
Access
disallowed
0008 0000 H
000A 0000 H
External area
Access
disallowed
Built-in ROM
384 KB
Built-in ROM
384 KB
Access
disallowed
External area
External area
0010 0000 H
FFFF FFFFH
• Each mode is set depending on the mode vector fetch after INIT is negated.
• The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the
available area is updated, the instruction must be followed by at least 1 NOP instruction.
33
MB91350A Series
• Memory Map of MB91356B
Single chip mode
Internal ROM
external bus mode
External ROM
external bus mode
I/O
I/O
I/O
Direct
addressing area
I/O
I/O
I/O
Refer to “3. I/O Map”
Access
disallowed
Access
disallowed
Access
disallowed
Built-in RAM 8 KB
(Executable)
Built-in RAM 8 KB
(Executable)
Built-in RAM 8 KB
(Executable)
Built-in RAM 16 KB
(Stack)
Built-in RAM 16 KB
(Stack)
Built-in RAM 16 KB
(Stack)
Access
disallowed
Access
disallowed
0000 0000 H
0000 0400 H
0001 0000 H
0003 E000 H
0004 0000 H
0004 4000 H
0005 0000 H
Access
disallowed
0008 0000 H
000C 0000 H
External area
Access
disallowed
Built-in ROM
256 KB
Built-in ROM
256 KB
Access
disallowed
External area
External area
0010 0000 H
FFFF FFFFH
• Each mode is set depending on the mode vector fetch after INIT is negated.
• The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the
available area is updated, the instruction must be followed by at least 1 NOP instruction.
34
MB91350A Series
3. I/O Map
This shows the location of the various peripheral resource registers in the memory space.
(How to read the table)
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Block diagram
T-unit
Port Data Register
Read/write attribute, Access unit
(B : Byte, H : Half Word, W : Word)
Initial value after a reset
Register name (First-column register at address 4n, second-column register at
address 4n + 2)
Location of left-most register (When using word access, the register in column
1 is in the MSB side of the data.)
Note : Initial values of register bits are represented as follows :
“1” : Initial value is “1”.
“0” : Initial Value: “0”.
“X” : Initial value is “X”.
“−” : No physical register at this location
Address
Register
Block
diagram
+0
+1
+2
+3
000000H
⎯
⎯
PDR2 [R/W] B
XXXXXXXX
PDR3 [R/W] B
XXXXXXXX
000004H
PDR4 [R/W] B
XXXXXXXX
PDR5 [R/W] B
XXXXXXXX
PDR6 [R/W] B
XXXXXXXX
⎯
000008H
PDR8 [R/W] B
- - XXXXXX
PDR9 [R/W] B
- - - XXXXX
PDRA [R/W] B
- - - - XXXX
PDRB [R/W] B
XXXXXXXX
00000CH
PDRC [R/W] B
- - - - - XXX
000010H
PDRG[R/W] B
- - XXXXXX
PDRH [R/W] B
- - XXXXXX
PDRI [R/W] B
- - XXXXXX
PDRJ [R/W] B
XXXXXXXX
000014H
PDRK [R/W] B
XXXXXXXX
PDRL [R/W] B
- - - - - - XX
PDRM [R/W] B
- - XXXXXX
PDRN [R/W] B
- - XXXXXX
000018H
PDRO [R/W] B
XXXXXXXX
PDRP [R/W] B
- - - - XXXX
⎯
⎯
⎯
⎯
Reserved
SES5 [R/W] B*3
- - - - - - 00
SDR5 [R/W] B*3
XXXXXXXX
SIO 5*3
⎯
000024H
R-bus
Port Data
Register
⎯
00001CH
000020H
T-unit
Port Data
Register
⎯
⎯
SMCS5 [R/W] B, H*3
00000010 - - - - 00 - -
(Continued)
35
MB91350A Series
Address
Register
+0
+1
+2
+3
Block
diagram
000028H
SMCS6 [R/W] B, H
00000010 - - - - 00 - -
SES6 [R/W] B
- - - - - - 00
SDR6 [R/W] B
XXXXXXXX
SIO 6
00002CH
SMCS7 [R/W] B, H
00000010 - - - - 00 - -
SES7 [R/W] B
- - - - - - 00
SDR7 [R/W] B
XXXXXXXX
SIO 7
000030H
⎯
⎯
CDCR5 [R/W] B
0---1111
⎯*1
SIO Prescaler
5
000034H
CDCR6 [R/W] B
0 - - - 1111
⎯*1
CDCR7 [R/W] B
0 - - - 1111
⎯*1
SIO Prescaler
6, 7
000038H
⎯
SRCL5 [W] B
--------
SRCL6 [W] B
--------
SRCL7 [W] B
--------
SIO5 to SIO7
00003CH
⎯
⎯
⎯
⎯
Reserved
000040H
EIRR0 [R/W] B, H, W ENIR0 [R/W] B, H, W
00000000
00000000
ELVR0 [R/W] B, H, W
00000000
Ext int
(INT0 to INT7)
000044H
DICR [R/W] B, H, W HRCL [R/W] B, H, W
-------0
0 - - 11111
⎯
DLYI/I-unit
000048H
TMRLR [W] H, W
XXXXXXXX XXXXXXXX
TMR [R] H, W
XXXXXXXX XXXXXXXX
00004CH
⎯
TMCSR [R/W] B, H, W
- - - - 0000 00000000
000050H
TMRLR [W] H, W
XXXXXXXX XXXXXXXX
TMR [R] H, W
XXXXXXXX XXXXXXXX
000054H
⎯
TMCSR [R/W] B, H, W
- - - - 0000 00000000
000058H
TMRLR [W] H, W
XXXXXXXX XXXXXXXX
TMR [R] H, W
XXXXXXXX XXXXXXXX
⎯
TMCSR [R/W] B, H, W
- - - - 0000 00000000
00005CH
000060H
000064H
000068H
00006CH
000070H
000074H
SSR [R/W] B, H, W
00001000
SIDR/SODR [R/W]
B, H, W
XXXXXXXX
UTIM [R] H (UTIMR [W] H)
00000000 00000000
SSR [R/W] B, H, W
00001000
SIDR/SODR [R/W]
B, H, W
XXXXXXXX
UTIM [R] H (UTIMR [W] H)
00000000 00000000
SSR [R/W] B, H, W
00001000
SIDR/SODR [R/W]
B, H, W
XXXXXXXX
UTIM [R] H (UTIMR [W] H)
00000000 00000000
SCR [R/W] B, H, W SMR [R/W] B, H, W
00000100
00 - - 0 - - DRCL [W] B
--------
UTIMC [R/W] B
0 - - 00001
SCR [R/W] B, H, W SMR [R/W] B, H, W
00000100
00 - - 0 - - DRCL [W] B
--------
UTIMC [R/W] B
0 - - 00001
SCR [R/W] B, H, W SMR [R/W] B, H, W
00000100
00 - - 0 - - DRCL [W] B
--------
UTIMC [R/W] B
0 - - 00001
Reload Timer 0
Reload Timer 1
Reload Timer 2
UART0
U-Timer/
UART 0
UART1
U-Timer/
UART 1
UART2
U-Timer/
UART 2
(Continued)
36
MB91350A Series
Address
000078H
Register
+0
+1
ADCS2 [R/W]B, H, W ADCS1 [R/W]B, H, W
X000XX00
000X0000
+2
Block
diagram
+3
ADCT [R/W] H, W
XXXXXXXX_XXXXXXXX
A/D
converter:
Successive
approximation
00007CH
ADTH0 [R] B, H, W
XXXXXXXX
ADTL0 [R] B, H, W
000000XX
ADTH1 [R] B, H, W
XXXXXXXX
ADTL1 [R] B, H, W
000000XX
000080H
ADTH2 [R] B, H, W
XXXXXXXX
ADTL2 [R] B, H, W
000000XX
ADTH3 [R] B, H, W
XXXXXXXX
ADTL3 [R] B, H, W
000000XX
000084H
⎯
000088H
⎯
00008CH
⎯
⎯
⎯
⎯
Reserved
000090H
⎯
⎯
⎯
⎯*1
Reserved
000094H
IBCR [R/W] B, H, W
00000000
IBSR [R] B, H, W
00000000
000098H
DACR2 [R/W] B, H, W DACR1 [R/W] B, H, W DACR0 [R/W] B, H, W
-------0
-------0
-------0
D/A
Converter
DADR2 [R/W] B, H, W DADR1 [R/W] B, H, W DADR0 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
XXXXXXXX
ITMK [R/W] B, H, W
00 - - - - 11 11111111
ITBA [R/W] B, H, W
- - - - - - 00 00000000
ISMK [R/W] B, H, W
01111111
ISBA [R/W] B, H, W
- 0000000
00009CH
⎯
IDAR [R/W] B, H, W
00000000
ICCR [R/W] B, H, W
0 - 011111
IDBL [R/W] B, H, W
-------0
0000A0H
⎯
⎯*1
⎯
⎯*1
0000A4H
⎯
⎯*1
⎯*1
⎯*1
0000A8H
TMRLR [W] H, W
XXXXXXXX XXXXXXXX
TMR [R] H, W
XXXXXXXX XXXXXXXX
⎯
TMCSR [R/W] B, H, W
- - - - 0000 00000000
0000ACH
0000B0H
RCR1 [W] B, H, W
00000000
RCR0 [W] B, H, W
00000000
UDCR1 [R] B, H, W
00000000
0000B4H
CCRH0 [R/W] B, H, W CCRL0 [R/W] B, H, W
00001000
00001000
⎯
0000B8H
CCRH1 [R/W] B, H, W CCRL1 [R/W] B, H, W
00001000
00001000
⎯
I2C
interface
Reserved
Reload
Timer 3
UDCR0 [R] B, H, W
00000000
8/16-bit
CSR0 [R/W] B, H, W Up/Down
Counter
00000000
0, 1
CSR1 [R/W] B, H, W
00000000
0000BCH
⎯
⎯
⎯
⎯
Reserved
0000C0H
SSR [R/W] B, H, W
00001000
SIDR/SODR [R/W]
B, H, W
XXXXXXXX
SCR [R/W] B, H, W
00000100
SMR [R/W] B, H, W
00 - - 0 - - -
UART3
⎯
UTIMC [R/W] B
0 - - 00001
U-Timer/
UART 3
SCR [R/W] B, H, W
00000100
SMR [R/W] B, H, W
00 - - 0 - - -
UART4
0000C4H
0000C8H
UTIM [R] H (UTIMR [W] H)
00000000 00000000
SSR [R/W] B, H, W
00001000
SIDR/SODR [R/W]
B, H, W
XXXXXXXX
(Continued)
37
MB91350A Series
Address
Register
+0
+1
+2
+3
Block
diagram
⎯
UTIMC [R/W] B
0 - - 00001
U-Timer/
UART 4
0000CCH
UTIM [R] H (UTIMR [W] H)
00000000 00000000
0000D0H
EIRR1 [R/W] B, H, W ENIR1 [R/W]B, H, W
00000000
00000000
0000D4H
TCDT [R/W] H, W
00000000 00000000
0000D8H
IPCP1 [R] H, W
XXXXXXXX XXXXXXXX
IPCP0 [R] H, W
XXXXXXXX XXXXXXXX
0000DCH
IPCP3 [R] H, W
XXXXXXXX XXXXXXXX
IPCP2 [R] H, W
XXXXXXXX XXXXXXXX
0000E0H
⎯
0000E4H
OCCP1 [R/W] H, W
XXXXXXXX XXXXXXXX
OCCP0 [R/W] H, W
XXXXXXXX XXXXXXXX
0000E8H
OCCP3 [R/W] H, W
XXXXXXXX XXXXXXXX
OCCP2 [R/W] H, W
XXXXXXXX XXXXXXXX
0000ECH
OCCP5 [R/W] H, W
XXXXXXXX XXXXXXXX
OCCP4 [R/W] H, W
XXXXXXXX XXXXXXXX
0000F0H
OCCP7 [R/W] H, W
XXXXXXXX XXXXXXXX
OCCP6 [R/W] H, W
XXXXXXXX XXXXXXXX
0000F4H
OCS23 [R/W] B, H, W
1110110 00001100
OCS01 [R/W] B, H, W
1110110 00001100
0000F8H
OCS67 [R/W] B, H, W
1110110 00001100
OCS45 [R/W] B, H, W
1110110 00001100
ICS23 [R/W] B, H, W
00000000
ELVR1 [R/W] B, H, W
00000000
TCCS [R/W] B, H, W
00000000
⎯
Ext int
(INT8-15)
16-bit
Free run
Timer
16-bit ICU
ICS01 [R/W] B, H, W
00000000
⎯
16-bit
OCU
*3
0000FCH
⎯
⎯
⎯
⎯
Reserved
000100H
to
000114H
⎯
⎯
⎯
⎯
Reserved
⎯
GCN20 [R/W] B
00000000
PPG
Control 0
000118H
GCN10 [R/W] H
00110010_00010000
00011CH
⎯
⎯
000120H
PTMR0 [R] H, W
11111111_11111111
PCSR0 [W] H, W
XXXXXXXX_XXXXXXXX
000124H
PDUT0 [W] H, W
XXXXXXXX_XXXXXXXX
PCNH0 [R/W] B, H, W PCNL0 [R/W] B, H, W
00000000
00000000
000128H
PTMR1 [R] H, W
11111111_11111111
PCSR1 [W] H, W
XXXXXXXX_XXXXXXXX
00012CH
PDUT1 [W] H, W
XXXXXXXX_XXXXXXXX
PCNH1 [R/W] B, H, W PCNL1 [R/W] B, H, W
00000000
00000000
Reserved
PPG0
PPG1
(Continued)
38
MB91350A Series
Address
Register
+0
+1
+2
+3
000130H
PTMR2 [R] H, W
11111111_11111111
PCSR2 [W] H, W
XXXXXXXX_XXXXXXXX
000134H
PDUT2 [W] H, W
XXXXXXXX_XXXXXXXX
PCNH2 [R/W] B, H, W PCNL2 [R/W] B, H, W
00000000
00000000
000138H
PTMR3 [R] H, W
11111111_11111111
PCSR3 [W] H, W
XXXXXXXX_XXXXXXXX
00013CH
PDUT3 [W] H, W
XXXXXXXX_XXXXXXXX
PCNH3 [R/W] B, H, W PCNL3[R/W] B, H, W
00000000
00000000
000140H
PTMR4 [R] H, W
11111111_11111111
PCSR4 [W] H, W
XXXXXXXX_XXXXXXXX
000144H
PDUT4 [W] H, W
XXXXXXXX_XXXXXXXX
PCNH4 [R/W] B, H, W PCNL4 [R/W] B, H, W
00000000
00000000
000148H
PTMR5 [R] H, W
11111111_11111111
PCSR5 [W] H, W
XXXXXXXX_XXXXXXXX
00014CH
PDUT5 [W] H, W
XXXXXXXX_XXXXXXXX
PCNH5 [R/W] B, H, W PCNL5 [R/W] B, H, W
00000000
00000000
000150H
to
0001FCH
⎯
000200H
DMACA0 [R/W] B, H, W*2
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W] B, H, W*2
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W] B, H, W*2
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W] B, H, W*2
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W] B, H, W*2
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
⎯
Block
diagram
PPG2
PPG3
PPG4
PPG5
Reserved
DMAC
(Continued)
39
MB91350A Series
Address
Register
+0
+1
+2
+3
Block
diagram
00022CH
to
00023CH
⎯
Reserved
000240H
DMACR [R/W] B
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
000244H
to
00027CH
⎯
Reserved
000280H
FRLR [R/W] B, H, W
- - - - - - 01*3
⎯
000284H
to
00038CH
000390H
⎯
⎯
⎯
DRLR [R/W] B, H, W
- - - - - - 01*3
⎯
Reserved
⎯
⎯
000394H
to
0003ECH
⎯
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
D-bus RAM
capacity limit
Reserved
Bit Search
Module
000400H
DDRG[R/W] B
- - 000000
DDRH [R/W] B
- - 000000
DDRI [R/W] B
- - 000000
DDRJ [R/W] B
00000000
000404H
DDRK [R/W] B
00000000
DDRL [R/W] B
- - - - - - 00
DDRM [R/W] B
- - 000000
DDRN [R/W] B
- - 000000
000408H
DDRO [R/W] B
00000000
DDRP [R/W] B
- - - - 0000
⎯
R-bus
Data
Direction
Register
⎯
00040CH
000410H
PFRG [R/W] B
- - 00 - 00 -
PFRH [R/W] B
- - 00 - 00 -
PFRI [R/W] B
- - 00 - 00 -
⎯
000414H
________
PFRL [R/W] B
- - - - - - 00
PFRM [R/W] B
- - 00 - 00 -
PFRN [R/W] B
- - 000000
000418H
PFRO [R/W] B
00000000
PFRP [R/W] B
- - - - 0000
00041CH
F-bus RAM
capacity limit
R-bus
Port Function
Register
⎯
⎯
Reserved
(Continued)
40
MB91350A Series
Address
000420H
Register
+0
+1
+2
+3
PCRG [R/W] B
- - 000000
PCRH [R/W] B
- - 000000
PCRI [R/W] B
- - 000000
⎯
PCRN [R/W] B
- - 000000
⎯
000424H
⎯
⎯
PCRM [R/W] B
- - 000000
000428H
PCRO [R/W] B
00000000
PCRP [R/W] B
- - - - 0000
⎯
00042CH
to
00043CH
⎯
000440H
ICR00 [R/W] B, H, W ICR01 [R/W] B, H, W ICR02 [R/W] B, H, W ICR03 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000444H
ICR04 [R/W] B, H, W ICR05 [R/W] B, H, W ICR06 [R/W] B, H, W ICR07 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000448H
ICR08 [R/W] B, H, W ICR09 [R/W] B, H, W ICR10 [R/W] B, H, W ICR11 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
00044CH
ICR12 [R/W] B, H, W ICR13 [R/W] B, H, W ICR14 [R/W] B, H, W ICR15 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000450H
ICR16 [R/W] B, H, W ICR17 [R/W] B, H, W ICR18 [R/W] B, H, W ICR19 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000454H
ICR20 [R/W] B, H, W ICR21 [R/W] B, H, W ICR22 [R/W] B, H, W ICR23 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000458H
ICR24 [R/W] B, H, W ICR25 [R/W] B, H, W ICR26 [R/W] B, H, W ICR27 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
00045CH
ICR28 [R/W] B, H, W ICR29 [R/W] B, H, W ICR30 [R/W] B, H, W ICR31 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000460H
ICR32 [R/W] B, H, W ICR33 [R/W] B, H, W ICR34 [R/W] B, H, W ICR35 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000464H
ICR36 [R/W] B, H, W ICR37 [R/W] B, H, W ICR38 [R/W] B, H, W ICR39 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000468H
ICR40 [R/W] B, H, W ICR41 [R/W] B, H, W ICR42 [R/W] B, H, W ICR43 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
00046CH
ICR44 [R/W] B, H, W ICR45 [R/W] B, H, W ICR46 [R/W] B, H, W ICR47 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000470H
to
00047CH
⎯
Block
diagram
R-bus
Pull-up
Control
Register
Reserved
000480H
RSRR [R/W] B, H, W STCR [R/W] B, H, W TBCR [R/W] B, H, W
10000000
00110011
00XXXX00
000484H
CLKR [R/W] B, H, W
00000000
WPR [W] B, H, W
XXXXXXXX
000488H
⎯
⎯
Interrupt
Control unit
CTBR [W] B, H, W
XXXXXXXX
Clock
DIVR0 [R/W] B, H, W DIVR1 [R/W] B, H, W
Control unit
00000011
00000000
OSCCR [R/W] B
XXXXXXX0
⎯
(Continued)
41
MB91350A Series
Register
+0
+1
+2
+3
Block
diagram
00048CH
WPCR [R/W] B
00 - - - 000
⎯
⎯
⎯
Clock timer
000490H
OSCR [R/W] B
000 - - XX0
⎯
⎯
⎯
Main oscillation
stabilization
timer
000494H
RSTOP0 [W] B
00000000
RSTOP1 [W] B
00000000
RSTOP2 [W] B
00000000
RSTOP3 [W] B
- - - - - 000
Peripheral stop
control
000498H
⎯
⎯
⎯
⎯
Reserved
Address
00049CH
to
0005FCH
⎯
Reserved
000600H
⎯
⎯
DDR2 [R/W] B
00000000
DDR3 [R/W] B
00000000
000604H
DDR4 [R/W] B
00000000
DDR5 [R/W] B
00000000
DDR6 [R/W] B
00000000
⎯
000608H
DDR8 [R/W] B
- - 000000
DDR9 [R/W] B
- - - 00000
DDRA [R/W] B
- - - - 0000
DDRB [R/W] B
00000000
00060CH
DDRC [R/W] B
- - - - - 000
000610H
⎯
⎯
⎯
⎯
000614H
⎯
⎯
PFR6 [R/W] B
11111111
⎯
000618H
PFR8 [R/W] B
--1--0--
PFR9 [R/W] B
- - - 010 - 1
PFRA [R/W] B
- - - - 1111
PFRB1 [R/W] B
00000000
00061CH
PFRB2 [R/W] B
00 - - - - 00
PFRC [R/W] B
- - - 00000
⎯
⎯
000620H
⎯
⎯
PCR2 [R/W] B
00000000
PCR3 [R/W] B
00000000
000624H
PCR4 [R/W] B
00000000
PCR5 [R/W] B
00000000
PCR6 [R/W] B
00000000
⎯
000628H
PCR8 [R/W] B
--000000
PCR9 [R/W] B
00000000
PCRA [R/W] B
00000000
PCRB [R/W] B
00000000
00062CH
PCRC [R/W] B
-----000
⎯
⎯
⎯
T-unit
Data Direction
Register
⎯
000630H
to
00063CH
⎯
T-unit
Port Function
Register
T-unit
Pull-up Control
Register
Reserved
000640H
ASR0 [R/W] H, W
00000000 00000000
ACR0 [R/W] B, H, W
1111XX00 00000000
000644H
ASR1 [R/W] H, W
00000000 00000000
ACR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W] H, W
00000000 00000000
ACR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
T-unit
(Continued)
42
MB91350A Series
Address
Register
+0
+1
+2
+3
00064CH
ASR3 [R/W] H, W
00000000 00000000
ACR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000650H
ASR4 [R/W] H, W
00000000 00000000
ACR4 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000654H
ASR5 [R/W] H, W
00000000 00000000
ACR5 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000658H
ASR6 [R/W] H, W
00000000 00000000
ACR6 [R/W] B, H, W
XXXXXXXX XXXXXXXX
00065CH
ASR7 [R/W] H, W
00000000 00000000
ACR7 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000660H
AWR0 [R/W] B, H, W
01111111 11111111
AWR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
AWR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000668H
AWR4 [R/W] B, H, W
XXXXXXXX XXXXXXXX
AWR5 [R/W] B, H, W
XXXXXXXX XXXXXXXX
00066CH
AWR6 [R/W] B, H, W
XXXXXXXX XXXXXXXX
AWR7 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000670H
⎯
000674H
⎯
000678H
IOWR0 [R/W] B, H, W IOWR1 [R/W] B, H, W IOWR2 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
XXXXXXXX
T-unit
⎯
⎯
00067CH
000680H
Block
diagram
CSER [R/W] B, H, W
00000001
⎯
000684H
to
000AFCH
⎯
TCR [W] B, H, W
0000XXXX
⎯
Reserved
000B00H
ESTS0 [R/W]
X0000000
ESTS1 [R/W]
XXXXXXXX
ESTS2 [R]
1XXXXXXX
⎯
000B04H
ECTL0 [R/W]
0X000000
ECTL1 [R/W]
00000000
ECTL2 [W]
000X0000
ECTL3 [R/W]
00X00X11
000B08H
ECNT0 [W]
XXXXXXXX
ECNT1 [W]
XXXXXXXX
EUSA [W]
XXX00000
EDTC [W]
0000XXXX
DSU
(Evaluation chip
only)
(Continued)
43
MB91350A Series
Address
Register
+0
+1
+2
+3
000B0CH
EWPT [R]
00000000 00000000
⎯
000B10H
EDTR0 [W]
XXXXXXXX XXXXXXXX
EDTR1 [W]
XXXXXXXX XXXXXXXX
000B14H
to
000B1CH
⎯
000B20H
EIA0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B24H
EIA1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B28H
EIA2 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B2CH
EIA3 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B30H
EIA4 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B34H
EIA5 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B38H
EIA6 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B3CH
EIA7 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B40H
EDTA [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B44H
EDTM [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B48H
EOA0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B4CH
EOA1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B50H
EPCR [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B54H
EPSR [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B58H
EIAM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B5CH
EIAM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B60H
EOAM0/EODM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Block
diagram
DSU
(Evaluation
chip only)
(Continued)
44
MB91350A Series
Address
Register
+0
+1
+2
+3
Block
diagram
000B64H
EOAM1/EODM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B68H
EOD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B6CH
EOD1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B70H
to
000BFCH
⎯
Reserved
000C00H
Register access disallowed
Interrupt
Control unit
000C04H
to
000C14H
Register access disallowed
R-bus test
000C18H
to
000FFCH
⎯
Reserved
001000H
DMASA0 [R/W] W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001004H
DMADA0 [R/W] W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001008H
DMASA1 [R/W] W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
00100CH
DMADA1 [R/W] W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001010H
DMASA2 [R/W] W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001014H
DMADA2 [R/W] W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001018H
DMASA3 [R/W] W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
00101CH
DMADA3 [R/W] W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001020H
DMASA4 [R/W] W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001024H
DMADA4 [R/W] W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001028H
to
001FFCH
⎯
DSU
(Evaluation
chip only)
DMAC
Reserved
(Continued)
45
MB91350A Series
(Continued)
Address
Register
+0
+1
+2
+3
007000H
FLCR [R/W]
0110X000
⎯
⎯
⎯
007004H
FLWC [R/W]
00010011
⎯
⎯
⎯
007008H
⎯
⎯
⎯
⎯
00700CH
⎯
⎯
⎯
⎯
007010H
⎯
⎯
⎯
⎯
007014H
to
0070FFH
⎯
Block
diagram
Flash
memory
Reserved
*1 : Test register access barred
*2 : The lower 16-bit (DTC(15: 0)) of DMACA0 to DMACA4 cannot be accessed in byte.
*3 : The available area of internal RAM is restricted by the function described in 6-209 immediately after a reset is
canceled. When the setting of the available area is updated, the instruction must be followed by at least 1 NOP
instruction.
46
MB91350A Series
■ VECTOR TABLE
Interrupt source
Interrupt
number
Interrupt
level
Offset
TBR default
address
RN
10
16
Reset
0
00
⎯
3FCH
000FFFFCH
⎯
Mode vector
1
01
⎯
3F8H
000FFFF8H
⎯
System reserved
2
02
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04
⎯
3ECH
000FFFECH
⎯
System reserved
5
05
⎯
3E8H
000FFFE8H
⎯
System reserved
6
06
⎯
3E4H
000FFFE4H
⎯
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
⎯
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
⎯
INTE instruction
9
09
⎯
3D8H
000FFFD8H
⎯
Instruction break exception
10
0A
⎯
3D4H
000FFFD4H
⎯
Operand break trap
11
0B
⎯
3D0H
000FFFD0H
⎯
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
⎯
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
⎯
NMI request
15
0F
15 (FH)
fixed15
3C0H
000FFFC0H
⎯
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
6
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
7
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
11
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
⎯
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
⎯
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
⎯
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
⎯
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
⎯
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
8
Reload timer 1
25
19
ICR09
398H
000FFF98H
9
Reload timer 2
26
1A
ICR10
394H
000FFF94H
10
UART(Reception completed)
27
1B
ICR11
390H
000FFF90H
0
UART(Reception completed)
28
1C
ICR12
38CH
000FFF8CH
1
UART(Reception completed)
29
1D
ICR13
388H
000FFF88H
2
UART0 (RX completed)
30
1E
ICR14
384H
000FFF84H
3
UART1 (RX completed)
31
1F
ICR15
380H
000FFF80H
4
UART2 (RX completed)
32
20
ICR16
37CH
000FFF7CH
5
(Continued)
47
MB91350A Series
Interrupt source
Interrupt
number
Interrupt
level
Offset
TBR default
address
RN
10
16
DMAC0 (end, error)
33
21
ICR17
378H
000FFF78H
⎯
DMAC1 (end, error)
34
22
ICR18
374H
000FFF74H
⎯
DMAC2 (end, error)
35
23
ICR19
370H
000FFF70H
⎯
DMAC3 (end, error)
36
24
ICR20
36CH
000FFF6CH
⎯
DMAC4 (end, error)
37
25
ICR21
368H
000FFF68H
⎯
A/D
38
26
ICR22
364H
000FFF64H
15
I2C
39
27
ICR23
360H
000FFF60H
⎯
UART4 (Reception completed)
40
28
ICR24
35CH
000FFF5CH
⎯
SIO 5
41
29
ICR25
358H
000FFF58H
12
SIO 6
42
2A
ICR26
354H
000FFF54H
13
SIO 7
43
2B
ICR27
350H
000FFF50H
14
UART3 (Reception completed)
44
2C
ICR28
34CH
000FFF4CH
⎯
UART3 (RX completed)
45
2D
ICR29
348H
000FFF48H
⎯
Reload timer 3/main oscillation stabilization
wait timer
46
2E
ICR30
344H
000FFF44H
⎯
Timebase timer overflow
47
2F
ICR31
340H
000FFF40H
⎯
External interrupt: FPINT(8-15)
48
30
ICR32
33CH
000FFF3CH
⎯
Clock counter
49
31
ICR33
338H
000FFF38H
⎯
U/D Counter0
50
32
ICR34
334H
000FFF34H
⎯
U/D Counter1
51
33
ICR35
330H
000FFF30H
⎯
PPG 0/1
52
34
ICR36
32CH
000FFF2CH
⎯
PPG 2/3
53
35
ICR37
328H
000FFF28H
⎯
PPG 4/5
54
36
ICR38
324H
000FFF24H
⎯
16-bit free-run timer
55
37
ICR39
320H
000FFF20H
⎯
ICU2/3 (capture)
56
38
ICR40
31CH
000FFF1CH
⎯
ICU1 (capture)/UART4 (transmission
complete)
57
39
ICR41
318H
000FFF18H
⎯
ICU0 (capture)
58
3A
ICR42
314H
000FFF14H
⎯
OCU0/1 (match)
59
3B
ICR43
310H
000FFF10H
⎯
OCU2/3 (match)
60
3C
ICR44
30CH
000FFF0CH
⎯
OCU4/5 (match)
61
3D
ICR45
308H
000FFF08H
⎯
OCU6/7 (match)
62
3E
ICR46
304H
000FFF04H
⎯
Interrupt delay source bit
63
3F
ICR47
300H
000FFF00H
⎯
System reserved (Used by REALOS)
64
40
⎯
2FCH
000FFEFCH
⎯
System reserved (Used by REALOS)
65
41
⎯
2F8H
000FFEF8H
⎯
(Continued)
48
MB91350A Series
(Continued)
Interrupt source
Interrupt
number
Interrupt
level
Offset
TBR default
address
RN
10
16
System reserved
66
42
⎯
2F4H
000FFEF4H
⎯
System reserved
67
43
⎯
2F0H
000FFEF0H
⎯
System reserved
68
44
⎯
2ECH
000FFEECH
⎯
System reserved
69
45
⎯
2E8H
000FFEE8H
⎯
System reserved
70
46
⎯
2E4H
000FFEE4H
⎯
System reserved
71
47
⎯
2E0H
000FFEE0H
⎯
System reserved
72
48
⎯
2DCH
000FFEDCH
⎯
System reserved
73
49
⎯
2D8H
000FFED8H
⎯
System reserved
74
4A
⎯
2D4H
000FFED4H
⎯
System reserved
75
4B
⎯
2D0H
000FFED0H
⎯
System reserved
76
4C
⎯
2CCH
000FFECCH
⎯
System reserved
77
4D
⎯
2C8H
000FFEC8H
⎯
System reserved
78
4E
⎯
2C4H
000FFEC4H
⎯
System reserved
79
4F
⎯
2C0H
000FFEC0H
⎯
Used by INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
⎯
49
MB91350A Series
■ PERIPHERAL RESOURCES
1. Interrupt controller
(1)Description
The interrupt controller manages interrupt reception and arbitration.
• Hardware configuration
This module consists of the following components:
• ICR register
• Interrupt priority determination circuit
• Interrupt level and interrupt number (vector) generator
• HOLD request cancellation request generator
• Main function
This module has the following major functions:
• Detect NMI and interrupt requests
• Prioritize interrupts (according to level and number)
• Notify interrupt level of selected interrupt request (to CPU)
• Notify interrupt number of selected interrupt request (to CPU)
• Request (to the CPU) to return from stop mode in response to an NMI or interrupt request with interrupt level
other than “11111”
• Hold request cancellation request issued to the bus master
(2)Register list
ICR register
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
7
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
6
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
(Continued)
50
MB91350A Series
(Continued)
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
7
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
6
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
ICR4
3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
Hold request cancel request resister (HRCL)
HRCL
7
MHALT1
6
⎯
5
⎯
4
LVL4
3
LVL3
2
LVL2
1
LVL1
0
LVL0
51
MB91350A Series
(3)Block diagram
WAKEUP ("1"
UNMI
when LEVEL ≠ 11111)
Determine order of priority
LEVEL4 to LEVEL0
5
NMI
NMI
LEVEL determination
RI00
ICR00
VECTOR
determination
R-bus
52
6
LEVEL,
VECTOR
Generation
HLDREQ
Cancel
NMI
request
MHALTI
VCT5 to VCT0
MB91350A Series
2. External interrupt/NMI control
(1)Description
The external interrupt control unit is the block that controls external interrupt requests input to NMI and INT0 to
INT15.
The level can be selected from “H”, “L”, rising edge, or falling edge (except for NMI).
(2)Register list
External interrupt enable register (ENIR)
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
External interrupt request register (EIRR)
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Request level setting register (ELVR)
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
The above registers (for 8 channels) are available in two sets; there are a total of 16 channels.
(3)blockdiagram
R-bus
8
Interrupt
request
17
8
16
Interrupt enable register
Gate
Request F/F
Edge detection
circuit
17
INT0 to INT15
NMI
Interrupt source register
Interrupt level setting register
53
MB91350A Series
3. REALOS-related Hardware
REALOS-related hardware is used by the real-time OS. Therefore, REALOS-related hardware cannot be used
by user programs when REALOS is used.
• Delay interrupt module
(1)Description
The delayed interrupt module generates a task switching interrupt.
This module enables software to issue or cancel an interrupt request to the CPU.
(2)Register list
Delayed Interrupt Control Register (DICR)
7
⎯
6
⎯
5
⎯
4
⎯
3
⎯
2
⎯
(3)Block diagram
R-bus
DLYI
Interrupt request
54
1
⎯
0
DLY1
MB91350A Series
• Bit Search Module
(1)Description
The bit search module searches data written to an input register for “0”, “1”, or a change point and returns the
detected bit position.
(2)Register list
31
0
0 detection data register (BSD0)
1 detection data register (BSD1)
Data register for transition detection (BSDC)
Detection result register (BSRR)
(3)Block diagram
D-bus
Input latch
Address decoder
Detection
mode
Creating 1 detection data
Bit search circuit
Search results
55
MB91350A Series
4. 8/16-bit up/down counter
(1)Description
This block is the up/down counter consisting of 6 event input pins, an 8/16-bit up/down counter, an 8-bit reload/
compare register, and their control circuit.
The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 2 channels of 8/16-bit up/down
counter in this block.
This module has the following features.
• 8-bit count register enabling counting from (0)d to (255)d (enabling counting from (0)d to (65535)d in "16-bit
x 1 operation mode" ).
• Four different count modes available with selectable count clocks
Count mode
Timer mode
Up/down counter mode
Phase difference count mode (2 multiplication)
Phase difference count mode (4 multiplication)
• Capable of selecting a count clock signal in timer mode, from among the inputs from two internal clocks and
an internal circuit
Count clock
80 ns (12.5 MHz : 2-frequency division)
(When operating at 25 MHz )
320 ns (3.125 Hz : 8-frequency division)
• Capable of selecting the detection edge of the external pin input signal in up/down counter mode
Detection edge
Falling Edge detection
Rising Edge detection
Detection at rising edge, falling edge, or both edges
Edge detection disabled
• Phase difference count mode suitable for counting for an encoder such as a motor, capable of easily counting
the rotation angle and the number of revolutions at high precision by inputting the phase-A, phase-B, and
phase-Z outputs of the encoder
• ZIN pin available for two functions selectable (valid in all modes)
ZIN Pin
Counter clear function
Gate function
• Compare and reload functions available not only separately but also in combination for up/down counting at
an arbitrary width
Compare/reload function
Compare function (comparison interrupt request output)
Compare function (comparison interrupt request output and counter clear)
Reload function (underflow interrupt request output and reload)
Compare/reload function(Comparison interrupt request output and counter
clear; underflow interrupt request output and reload)
Compare/reload disabled
• Count direction flag used to identify the preceding count direction
• Capable of controlling the independent generations of interrupts at a compare match, reload (underflow),
overflow, or at a count direction change
56
MB91350A Series
(2)Register list
• Up/down count resister (UDCR)
Up/down count resister ch0 (UDCR0)
7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
Up/down count resister ch1 (UDCR1)
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D09
D08
7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
• Reload compare resister (RCR)
Reload compare resister ch0 (RCR0)
Reload compare resister ch1 (RCR1)
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D09
D08
• Counter status register (CSR)
Counter status register ch(0, 1) (CSR0, 1)
7
6
5
4
3
2
1
0
CST
CIT
UDI
CM
OVF
UD
UD
UD
• Counter control resister (CCRL)
Counter control resister ch(0, 1) (CCRL0, 1)
7
6
5
4
3
2
1
0
Reserved
CTU
UC
RLD
UD
CGS
CGE
CGE
• Counter control resister (CCRH)
Counter control resister ch0 (CCRH0)
15
14
13
12
11
10
9
8
M16
CDC
CFI
CLK
CM
CM
CES
CES
• Counter control resister ch1 (CCRH1)
15
14
13
12
11
10
9
8
Reserved
CDC
CFI
CLK
CM
CM
CES
CES
57
MB91350A Series
(3)Block diagram
Data bus
8 bit
CGE
ZIN0, ZIN1
CGE
RCR0(Reload
compare register ch0
CGS
Edge/level detection
CTU
Reload
control
UC
RLD
To ch1
M16
Carry
Counter clear
UD
8 bit
CES
CES
CM
CM
UDCR0(up/down
counter register ch0
CM
UD
AIN0, AIN1
BIN0, BIN1
Up/down
count
clock
select
Count
Clock
UDI
CST
UD
UD
CDC
Prescaler
CIT
CLK
CFI
Interrupt output
58
OVF
MB91350A Series
5. 16-bit Reload Timer
(1)Description
The 16-bit timer consists of a 16-bit down counter, 16-bit reload register, internal clock, clock generation prescaler,
and control register.
The clock source can be selected from among three internal clocks (prepared by frequency dividing the machine
clock by 2/8/32, and also by 64/128 only for ch3) and an external event.
The interrupt can be used to initiate DMA transfer.
The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 4 channels of this timer.
(2)Register list
Control status register (TMCSR)
15
14
⎯
⎯
13
Reserved
12
11
10
CSL2
CSL1
CSL0
9
8
Reserved Reserved
(ch3 only)
7
6
5
4
3
2
1
0
Reserved
⎯
OUTL
RELD
INTE
UF
CNTE
TRG
16-bit timer register(TMR)
15
0
16-bit reload register(TMRLR)
15
0
59
MB91350A Series
(3)Block diagram
16-bit reload register (TMRLR)
16
7
Reload
16
16-bit timer register (TMR) UF
RELD
OUTL
Count enable
OUT
CTL.
INTE
UF
R
|
b
u
s
CSL2
CNTE
CSL1
Clock selector
TRG
CSL0
External timer output
(TOT0 to TOT3)
EXCK
3
φ
21
φ
2
φ
3
2
5
φ
φ
26
27
(ch3 only)
Machine clock input
60
Re-trigger
IRQ
IN CTL.
Prescaler clear
TOE0 to 3
Bit in PFRP
MB91350A Series
6. PPG (Programable Pulse Generator)
The PPG can efficiently output highly precise PWM waveforms.
The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 6 channels of PPG timer.
(1)Description
Each channel consists of a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare
register with duty ratio setting buffer, and pin control unit.
The count clocks for the 16-bit down counter can be selected from the following 4 types :(peripheral clock φ, φ/
4, φ/16, φ/64)
The counter is initialized to "FFFFH" at a reset or counter borrow.
PPG outputs (PPG0 to PPG5) are provided for each channel.
(2)Register list
15
0
General control register 10 (GCN10)
General control register 20 (GCN20)
Timer register (PTMR0 to 5)
Cycle setting register (PCSR0 to 5)
Duty setting register (PDUT0)
(3)Block diagram (overall configuration for 1 channel)
16-bit reload timer ch0
16-bit reload timer ch1
General D/A control
ICR register 10
(resource select)
TRG input
PPG timer ch0
PPG0
TRG input
PPG timer ch1
PPG1
TRG input
PPG timer ch2
PPG2
TRG input
PPG timer ch3
PPG3
External TRG4
TRG input
PPG timer ch4
PPG4
External TRG5
TRG input
PPG timer ch5
PPG5
General D/A control
ICR register 20
4
External TRG0 to
TRG3
61
MB91350A Series
7. U-Timer (16-bit timer for UART baud rate generation)
(1) Description
The U-Timer is a 16-bit timer for generating the baud rate for the UART. An arbitrary baud rate can be set
depending on the combination of the chip operating frequency and U-Timer reload value.
The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 5 channels of this timer.
(2) Register list
15
8 7
0
U-Timer Register (UTIM)
Reload Register (UTIMR)
U-Timer Control Register (UTIMC)
(3) Block diagram
15
0
UTIMR (reload register)
load
15
0
UTIM (U-timer)
clock
φ
(Peripheral clock)
underflow
control
f.f.
62
to UART
MB91350A Series
8. UART
(1) Description
The UART is a serial I/O port for asynchronous (start-stop) or CLK synchronous communication. This module
has the features listed below. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 5
channels of UART.
•
•
•
•
•
•
•
•
•
Full duplex double buffer
Asynchronous (start-stop synchronized) or CLK synchronized transmission
Supports multi-processor mode
Completely programmable baud rate.
Arbitrary baud rate set by built-in timer (See the section for "U-Timer”.)
Variable baud rate can be input from an external clock.
Error detection functions(parity, framing, overrun)
Transmission signal format is NRZ
UART Ch0 to Ch2 can start DMA transfer using interrupts (Ch3 and Ch4 cannot start DMA transfer).
Capable of clearing DMAC interrupt source by writing to DRCL register
(2)Register list
Serial input register/serial output register (SIDR/SODR)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Serial status register(SSR)
7
6
5
4
3
2
1
0
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
7
6
5
4
3
2
1
0
MD1
MD0
⎯
⎯
CS0
⎯
⎯
⎯
7
6
5
4
3
2
1
0
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Serial mode register
Serial control register(SCR)
DECL register (DRCL)
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
63
MB91350A Series
(3) Block diagram
Control signal
RX interrupt
(to CPU)
SCK (clock)
Transmission clock
From U-Timer
Clock
selection
circuit
External clock
SCK
SI (Receive data)
TX interrupt
(to CPU)
Reception clock
Reception control
circuit
Transmission
control circuit
Start bit
detection circuit
Transmission
start circuit
Received bit
Counter
Sending bit
Counter
Received parity
Counter
Sending parity
Counter
SO (Send data)
Receive status
decision circuit
RX shifter
TX shifter
RX
complete
Start
transmission
SIDR
SODR
For DMA
received error generating
signal (to DMAC)
R - bus
MD1
MD0
SMR
Register
CS0
SCR
Register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
Register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control signal
64
MB91350A Series
9. Extended I/O Serial Interface (SIO)
(1) Description
This block is a serial I/O interface that allows data transfer using clock synchronization. It is composition of a
single 8-bit × 1 channel.
LSB-first or MSB-first transfer mode can be selected for data transfer.
The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 3 channels of this SIO.
The serial I/O interface operates in 2 modes:
• Internal shift clock mode: Transfer data in synchronization with the internal clock.
• External shift clock mode: Transfer data in synchronization with the clock supplied via the external pin (SCK).
By manipulating the general-purpose port sharing the external pin (SCK) in this
mode, data can also be transferred by a CPU instruction.
(2) Register list
Serial mode control status register (SMCS)
15
14
13
12
11
10
9
8
SMD2
SMD1
SMD0
SIE
SIR
BUSY
STOP
STRT
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
MODE
BDS
⎯
⎯
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
TST1
TST0
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
SIO test resister(SES)
SDR (Serial Data Register)
SIO prescaler control register (CDCR)
15
14
13
12
11
10
9
8
MD
⎯
⎯
⎯
DIV3
DIV2
DIV1
DIV0
DMAC interrupt source clear register (SRCL)
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
65
MB91350A Series
(3)Block diagram
Initial Value
Internal data bus
(MSB fast) D0 to D7
(MSB fast) D0 to D7
Select transmitting direction
SI5 to SI7
Read
write
SDR (Serial Data Register)
SO5 to SO7
SCK5 to SCK7
Control circuit
Shift clock counter
Internal clock
2
1
0
SMD2 SMD1 SMD0
SIE
SIR
BUSY STOP STRT MODE BDS
Interrupt
request
Internal data bus
66
SCE
PFR
Register
MB91350A Series
10. 16-bit free-run timer
(1)Description
The 16-bit free-running timer consists of a 16-bit up counter, control register, and status register. The count
values of this timer are used as the base timer for the output compares and input capture modules.
• Four count clock frequencies are available.
• An interrupt can be generated at a counter overflow.
• The counter can be initialized upon a match with compare register 0 of the output compare unit, depending
on the mode.
(2)Register list
Timer data register (upper) (TCDT)
15
14
13
12
11
10
9
8
T15
T14
T13
T12
T11
T10
T9
T8
Timer data register (lower) (TCDT)
7
6
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
Timer control status register (lower) (TCCS)
7
6
5
4
3
2
1
0
ECLK
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
(3)Block diagram
Interrupt
ECLK
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
Divider
φ
FRCK
R-bus
Clock
select
Timer data register
(TCDT)
Clock
to internal circuit (T15 to T00)
Comparator 0
67
MB91350A Series
11. Input Capture
(1) Description
This module detects a rising or falling edge or both edges of an external input signal and stores the 16-bit freerunning timer value in a register.
This module stores the 16-bit free-running timer value in a register. In addition, the module can generate an
interrupt upon detection of an edge.
The input capture module consists of input capture data registers and a control register.
Each input capture unit has a corresponding external input pin.
• The detection edge of an external input can be selected from among 3 types.
Rising edge
Falling edge
Both edges
• An interrupt can be generated upon detection of a valid edge of an external input.
(2) Register list
Input capture data register (upper) (IPCP)
15
14
13
12
11
10
9
8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
Input capture data register (lower) (IPCP)
7
6
5
4
3
2
1
0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
Capture control register (ICS23)
7
6
5
4
3
2
1
0
ICP3
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
Capture control register (ICS01)
68
7
6
5
4
3
2
1
0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
MB91350A Series
(3) Block diagram
16-bit timer counter value
(T15 to T00)
Input capture data register
ch (0, 2)
R-bus
16-bit timer counter value
(T15 to T00)
Input capture data register
ch (1, 3)
IN0, IN2
Input pin
Edge
detection
EG11
EG10
EG01
EG00
EG31
EG30
EG21
EG20
IN1, IN3
Input pin
Edge
detection
ICP1
ICP0
ICE1
ICE0
ICP3
ICP2
ICE3
ICE2
Interrupt
Interrupt
69
MB91350A Series
12. Output Compare
(1) Description
The output compare module consists of 16-bit compare registers, compare output latch, and control register.
When the 16-bit free-running timer value matches the compare register value, the output level is inverted and
an interrupt is issued.
The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 8 channels of this block.
This module has the features listed below.
• Capable of using the 8 compare registers independently. Output pins and interrupt flags corresponding to the
compare registers
• A pair of compare registers can be used to control output pins. Using tow compare registers to invert output pins
• Capable of setting the initial value for each output pin.
• Interrupts can be generated upon a compare match.
• The ch0 compare register is used as the compare clear register for the 16-bit free-running timer.
(2)Register list
Output compare register(upper) (OCCP)
15
14
13
12
11
10
9
8
C15
C14
C13
C12
C11
C10
C09
C08
Output compare register(lower) (OCCP)
7
6
5
4
3
2
1
0
C07
C06
C05
C04
C03
C02
C01
C00
Output control register(upper) (OCS)
15
14
13
12
11
10
9
8
⎯
⎯
⎯
CMOD
⎯
⎯
OTD1
OTD0
Output control register(lower) (OCS)
70
7
6
5
4
3
2
1
0
ICP1
ICP0
ICE1
ICE0
⎯
⎯
CST1
CST0
MB91350A Series
(3) Block diagram
(Only ch0 is used as a free running timer
clear register.)
OTD1
OTD0
Output compare
register
Compare
Output latch
Compare circuit
R-bus
Output compare
register
Compare
Output latch
OTE1, OTE3,
OTE5, OTE7
Output
CST0
ICP1
16-bit free-run timer
Output
OTE0 and OTE7 exist in PFRO.
There is in PFRO.
CMOD
Compare circuit
CST1
OTE0, OTE2,
OTE4, OTE6
ICP0
ICE1
ICE0
Interrupt output
Interrupt output
71
MB91350A Series
13. I2C Interface
(1) Description
The I2C interface is a serial I/O port supporting the Inter-IC bus, operating as a master/slave device on the I2C
bus. It has the following features
• Master/slave sending and receiving
• Arbitration function
• Clock sync function
• Slave address and general call address detection function
• Ditecting function of transmitting direction
• Repeated start condition generation and detection function
• Bus error detection function
• 10-bit/7-bit slave address
• Slave address receive acknowledge control when in master mode
• Support for composite slave addresses
• Capable of interruption when a transmission or bus error occurs
• Standard mode (Max 100K bps)/High speed mode (Max 400K bps) supported
72
MB91350A Series
(2)Register list
Bus control register(IBCR)
15
BER
14
BEIE
13
SCC
12
MSS
11
10
9
ACK GCAA INTE
8
INT
6
RSC
5
AL
4
LRB
3
TRX
2
AAS
1
GCA
0
ADT
Bus status register(IBSR)
7
BB
10-bit slave address resister (ITBA)
15
⎯
14
⎯
13
⎯
12
⎯
11
⎯
10
⎯
9
TA9
8
TA8
7
TA7
6
TA6
5
TA5
4
TA4
3
TA3
2
TA2
1
TA1
0
TA0
10-bit slave address mask resister(ITMK)
15
ENTB
14
RAL
13
⎯
12
⎯
11
⎯
10
⎯
9
TM9
8
TM8
7
6
5
4
3
2
1
0
TM7
TM6
TM5
TM4
TM3
TM2
TM1
TM0
5
SA5
4
SA4
3
SA3
2
SA2
1
SA1
0
SA0
13
SM5
12
SM4
11
SM3
10
SM2
9
SM1
8
SM0
7-bit slave address resister (ISBA)
7
⎯
6
SA6
7-bit slave address mask resister (ISMK)
15
14
ENSB SM6
Data register (IDAR)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
12
11
10
9
8
TEST
⎯
EN
CS4
CS3
CS2
CS1
CS0
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DBL
Clock control register (ICCR)
Clock disable register (IDBL)
73
MB91350A Series
(3) Block diagram
ICCR
Operation enable
EN
R-bus
IDBL
Clock enable
DBL
CLKP
ICCR
Clock divide 2
CS4
CS3
2 3 4 5
Sync
32
Generating shift clock
CS2
CS1
Clock selector2 (1/12)
CS0
IBSR
Shift clock edge
changing timing
Bus busy
BB
Start
RSC
LRB
TRX
Last Bit
Sending/
receiving
Start stop condition
detection
Error
First Byte
ADT
AL
Arbitration lost detection
IBCR
SCLI
SCLO
BER
BEIE
Interrupt request
SDA
SDAO
IRQ
INTE
INT
End
IBCR
SCC
MSS
ACK
GCAA
Start
Master
ACK enable
Start stop condition
generation
ACK enable
IDAR
IBSR
AAS
Slave
Global call
GCA
Slave address
compare
ISMK
FNSB
ITMK
ENTB
RAL
ITBA
74
ITMK
ISBA
ISMK
MB91350A Series
14. A/D Converter
(1) Description
The A/D converter converts the analog input voltage into a digital value. It has the following features:
• Conversion time: 1.48 µs minimum per channel
• Employing serial/parallel conversion type for sample & hold circuit
• 10-bit resolution (switchable between 8 and 10 bits)
• Program selection of the analog input from among 12 channels
• Conversion mode
Single conversion mode : Convert 1 selected channel
Scan conversion mode : Scan up to 4 channels.
• Converted data is stored in the data buffer.
• An interrupt request to the CPU can be generated upon completion of A/D conversion. The interrupt can be
used to start DMA transfer.
• The startup source can be selected from among software, external trigger (falling edge), and reload timer ch2
(rising edge).
(2) Register list
8 7
15
Control status register (ADCS2/ADSC1)
0
ADCS2
ADCS1
Converted data register 0 (ADTH0/ADTL0)
ADTH0
ADTL0
Converted data register 1 (ADTH1/ADTL1)
ADTH1
ADTL1
Converted data register 2 (ADTH2/ADTL2)
ADTH2
ADTL2
Converted data register 3 (ADTH3/ADTL3)
ADTH3
ADTL3
Conversion time setting resister (ADCT)
75
MB91350A Series
(3) Block diagram
Analog input
AVCC, AVRH, AVSS/AVRL
M
P
X
ADT0
S/H
10 bit
A/D
Converter
M
P
X
R-bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
ADT1
ADT2
ADT3
Control logic
Interrupt
16-bit reload timer ch2
External input
76
MB91350A Series
15. 8-bit D/A Converter
(1) Description
This block contains 2 channels of 8-bit D/A converters. The D/A converter register can be used to control the
independent output of each channel. The block has the following features.
• Power saving function
• 3.3 V Interface
(2) Register list
D/A data register 0 to 2(DADR0 to DADR2)
7
6
5
4
3
2
1
0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
D/A control register 0 to 2 (DACR0 to DACR2)
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DAE
(3) Block diagram
R-bus
D/A control
D/A
DAE0
D/A
DAE1
PD
STOP
D/A
DAE2
PD
STOP
PD
STOP
D/A
converter
D/A
converter
D/A
converter
D/A output 0
D/A output 1
D/A output 2
77
MB91350A Series
16. DMAC (DMA Controller)
(1) Description
This module realize direct memory access (DMA) transfer with the FR family device.
DMA transfer controlled by this module enables many types of data transfer to be performed at high speed
without CPU intervention, thereby improving system performance.
• Hardware configuration
This model consists mainly of the following components:
• Independent DMA channels × 5 channels
• 5 channels independent access control circuits
• 32-bit address register (Supports reloading: 2 per channel)
• 16-bit transfer count register (Supports reloading: 1 per channel)
• 4-bit block count register (1 per channel)
• External transfer request input pins: DREQ0, DREQ1, DREQ2 (ch0, ch1, ch2 only)
• External transfer request acceptance output pins: DACK0, DACK1, DACK2 (ch0, ch1,ch2 only)
• DMA end output pins: DEOP0, DEOP1, DEOP2 (ch0, ch1, ch2 only)
• (ch3 only) fly-by transfer (memory to I/O, I/O to memory)
• 2-cycle transfer
• Main function
This module has the following major functions for data transfer:
• Supports independent data transfer for multiple channels (5 channels)
(1) Priority order (ch0 > ch1 > ch2 > ch3 > ch4)
(2) Order can be reversed for ch0 and ch1
(3) DMAC activation triggers
• External dedicated pin input (edge detection/level detection: ch0 to ch2 only)
• Internal peripheral request (Interrupt request sharing, including external interrupts)
• Software request (register write)
(4) Transmission mode
• Demand transfer, burst transfer, step transfer, or block transfer
• Addressing mode: 32-bit full addressing (increment, decrement, or fixed)
(address increment can be in the range - 255 to + 255)
• Data length: Byte, halfword, or word
• Single-shot or reload operation selectable
78
MB91350A Series
(2) Register Description
31
Ch0 control/status
16 15
0
register A (DMACA0)
register B (DMACB0)
Ch1 control/status
register A (DMACA1)
register B (DMACB1)
Ch2 control/status
register A (DMACA2)
register B (DMACB2)
Ch3 control/status
register A (DMACA3)
register B (DMACB3)
Ch4 control/status
register A (DMACA4)
register B (DMACB4)
Overall control register
(DMACR)
Ch0 transfer source address register
(DMASA0)
(DMADA0)
Ch1 transfer source address register
(DMASA1)
(DMADA1)
Ch2 transfer source address register
(DMASA2)
(DMADA2)
Ch3 transfer source address register
(DMASA3)
(DMADA3)
Ch4 transfer source address register
(DMASA4)
(DMADA4)
79
MB91350A Series
(3) Block diagram
Counter
DMA transfer request
to bus controller
DMA start
source select
circuit & request
acceptance
control
Selector
Write
back
Buffer
DTC two-stage register DTCR
Peripheral start request/
Stop input
External pin start
request/stop input
Counter
DSS [3:0]
ERIR, EDIR
Status
transition
circuit
Clear peripheral interrupt
TYPE, MOD, WS
DDNO register
Selector
DSAD two-stage register
SADM, SASZ [7:0] SADR
Write back
DDAD two-stage register
DADM, DASZ [7:0] DADR
Write back
5-channel DMAC block diagram
80
Bus control block
Selector
BLK register
To interrupt controller IRQ
[4:0]
Selector
DMA control
Selector
Address
Counter buffer
Access
Counter buffer
bus
controller
Read/write
control
DDNO
Address counter
To
Bus control block
Read
Write
Priority
circuit
X-bus
Buffer
MCLREQ
MB91350A Series
■ ELECTRICAL CHARACTERISTICS
1. Abusolute Maximum Rating
Parameter
Rating
Symbol
Min
Max
Unit
Remarks
VCC
VSS − 0.5
VSS + 4.0
V
*2
1
Analog power supply voltage*
DAVC
VSS − 0.5
VSS + 4.0
V
*3
Analog power supply voltage*1
AVCC
VSS − 0.5
VSS + 4.0
V
*3
Analog reference voltage*1
AVRH
VSS − 0.5
VSS + 4.0
V
*3
VI
VSS − 0.5
VCC + 0.5
V
*8
Input voltage (Nch open-drain) *
VIND
VSS − 0.5
VSS + 5.5
V
*8
Analog pin input voltage*1
VIA
VSS − 0.5
AVCC + 0.5
V
*8
Output voltage*1
VO
VSS − 0.5
VCC + 0.5
V
ICLAMP
− 2.0
+ 2.0
mA
*7
Σ|ICLAMP|
⎯
20
mA
*7
“L” level maximum output current
IOL
⎯
10
mA
*4
“H” level maximum output current
(Nch open-drain)
IOLND
⎯
20
mA
“L” level average output current
IOLAV
⎯
8
mA
“H” level average output current
(Nch open-drain)
IOLAVND
⎯
15
mA
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*6
IOH
⎯
− 10
mA
*4
“H” level average output current
IOHAV
⎯
−4
mA
*5
“H” level total maximum output
current
ΣIOH
⎯
− 50
mA
ΣIOHAV
⎯
− 20
mA
Power consumption
PD
⎯
850
mW
Operating temperature
Ta
− 40
+ 85
°C
TSTG
⎯
+ 125
°C
Power supply voltage*1
Input voltage*
1
1
Maximum clamp current
Total maximum clamp current
“L” level total maximum output
current
“L” level total average output
current
“H” level maximum output current
“H” level total average output
current
Storage temperature
*5
*6
*1 : The parameter is based on VSS = DAVS = AVSS = 0 V.
*2 : VCC must not be lower than VSS - 0.3 V.
*3 : Be careful not to exceed "VCC + 0.3 V”, for example, when the power is turned on.
*4 : The maximum output current is the peak value for a single pin.
*5 : The average output current is the average current for a single pin over a period of 100 ms.
*6 : The total average output current is the average current for all pins over a period of 100 ms.
81
MB91350A Series
*7 : • Relevant pins: Port2, 3, 4, 5, 6, 8, 9, A, B, C, G, H, I, J, K, M, N, O, P, and AN (A/D input)
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The + B signal should always be applied a limiting resistance placed between the + B signal and
the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that, when the microcontroller drive current is low as in low power consumption mode, the + B input
potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices.
• Note that, if the + B input exists when the microcontroller is off (not fixed at 0 V), power is supplied through
the pin, possibly causing the microcontroller to operate imperfectly.
• Note that, if the + B input exists when the power supply is turned on, power is supplied through the pin,
possibly resulting in a power-supply voltage at which a power-on reset does not work.
• Be careful not to let the + B input pin open.
• Note that the analog I/O pins (such as the LCD drive and comparator input pins) other than the A/D input pin
cannot input + B.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
Vcc
+ B input (0 V to 16 V)
Pch
Limiting
resistance
Nch
R
*8: VI should not exceed the specified ratings. However, if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
82
MB91350A Series
2. Recommended Operating Conditions
(VSS = DAVS = AVSS = 0 V)
Parameter
Power supply voltage
Analog power supply voltage
Analog reference voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min
Max
VCC
3.0
3.6
V
At normal operating
VCC
3.0
3.6
V
hold RAM status at stop
DAVC
VSS − 0.3
VSS + 3.6
AVCC
VSS − 0.3
VSS + 3.6
AVRH
AVSS
AVCC
V
Ta
− 40
+ 85
°C
V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
83
MB91350A Series
3. DC Characteristics
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
“H” level
input voltage
“L” level
input voltage
"H" level
output voltage
“L” level
output voltage
Input leak
current
(High-Z
output Leakage current)
Pull-up
resistance
Symbol
Pin
Conditions
VIH
Port 2, 3, 4,
5, 6, 9, A, B,
C
Value
Unit
Remarks
Min
Typ
Max
⎯
VCC × 0.65
⎯
VCC − 0.3
V
VIHS
Port 8, G, H,
I, M, N, O, P,
MD0, MD1,
MD2, INIT,
NMI
⎯
VCC × 0.8
⎯
VCC − 0.3
V
Hysteresis
input
VIHST
Port J, K, L
⎯
VCC × 0.8
⎯
5.25
V
Hysteresis input
with stand
voltage of 5 V
VIL
Port 2, 3, 4,
5, 6, 9, A, B,
C
⎯
VSS
⎯
VCC × 0.25
V
VILS
Port 8, G, H,
I, M, N, O, P,
MD0, MD1,
MD2, INIT,
NMI
⎯
VSS
⎯
VCC × 0.2
V
Hysteresis input
VILST
Port J, K, L
⎯
VSS
⎯
VCC × 0.2
V
Hysteresis input
with stand
voltage of 5 V
VCC − 0.5
⎯
VCC
V
VSS
⎯
0.4
V
VCC = 3.0 V
IOL = 15.0 mA
VSS
⎯
0.4
V
VCC = 3.6 V
0<VI<VCC
−5
⎯
+5
µA
setting pin VCC = 3.6 V
INIT, Pull up VI = 0.45 V
25
50
200
kΩ
VOH
Port 2, 3, 4,
5, 6, 8, 9, A,
VCC = 3.0 V
B, C, G, H, I,
IOH = − 4.0 mA
J, K, M, N,
O, P
VOL1
Port 2, 3, 4,
5, 6, 8, 9, A,
VCC = 3.0 V
B, C, G, H, I,
IOL = 4.0 mA
J, K, M, N,
O, P
VOL2
Port L
ILI
All input pin
RUP
Nch open-drain
(Continued)
84
MB91350A Series
(Continued)
Parameter
Power
supply
current
Input
capacitance
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Symbol
Pin
Conditions
Value
Min
Typ
Max
Unit
Remarks
ICC
fC = 12.5 MHz
VCC = 3.3 V
⎯
160
220
Multiply by 4
CLKB : 50 MHz
mA CLKT : 25 MHz
When operating at
25 MHz
ICCS
fC = 12.5 MHz
VCC = 3.3 V
⎯
100
140
Sleep
mA When operating at
25 MHz
ICCH
Ta = + 25 °C
VCC = 3.3 V
⎯
1
100
µA
VCC
at stop
ICCL
Ta = + 25 °C
fC = 32.768 kHz
VCC = 3.3 V
⎯
0.3
3.0
Sub RUN
CLKB : 32.768 kHz
mA CLKT : 32.768 kHz
When operating at
32.768 kHz
ICCLS
Ta = + 25 °C
fC = 32.768 kHz
VCC = 3.3 V
⎯
0.2
2.0
Sub sleep
mA When operating at
32.768 kHz
ICCT
Ta = + 25 °C
fC = 32.768 kHz
VCC = 3.3 V
⎯
5
120
µA
⎯
⎯
5
15
pF
CIH
Other than
VCC, VSS,
AVCC, AVSS,
DAVC, DAVS
at watch mode
operating
(Main Off, STOP)
85
MB91350A Series
4. AC Characteristics
(1) Clock timing
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Symbol
Pin
fC
X0
X1
Clock cycle time
tC
X0
X1
Clock
frequency
fC
X0
X1
Parameter
Clock
frequency
fCP
Internal operating
clock frequency
fCPP
⎯
fCPT
tCP
Internal operating
clock cycle time
tCPP
⎯
tCPT
Conditions
Unit
Remarks
Min
Typ
Max
10
⎯
12.5
MHz
80
⎯
100
ns
⎯
10
⎯
25
Main self-oscillation
MHz (frequency-halved
input)
When a minimum
value of 12.5 MHz
is input as the X0
clock frequency
and × 4 multiplication is set for the
PLL of the oscillator
circuit
2.94*
⎯
50
MHz CPU
2.94*
⎯
25
MHz Peripheral
2.94*
⎯
25
MHz External bus
20
⎯
340*
ns
CPU
40
⎯
340*
ns
Peripheral
40
⎯
340*
ns
External bus
⎯
fC
X0A
X1A
⎯
30
32.768
35
kHz
Clock cycle time
tC
X0A
X1A
⎯
28.6
30.51
33.3
µs
Input clock palse
width
⎯
X0
X1
PWH/tc
PWL/tc
40
⎯
60
%
Internal operating
clock frequency
fCP,
fCPP,
fCPT
⎯
2*
⎯
32
kHz
Internal operating
clock cycle time
tCP,
tCPP,
tCPT
⎯
When a standard
value of 32.768 kHz
is input as the X0A
clock frequency
30.51
⎯
500*
µs
Clock
frequency
* : The values assume a gear cycle of 1/16.
86
Value
Main PLL
(When operating at
max internal frequency
(50 MHz) = 12.5 MHz
self-oscillation with × 4
PLL)
SUB
self-oscillation
MB91350A Series
• Conditions for measuring the clock timing ratings
tC
0.8 VCC
0.2 VCC
Output pin
C = 50 pF
PWL
PWH
tCR
tCF
• Operation Assurance Range
VCC (V)
Power supply
Operation Assurance Range (Ta = − 40°C to + 85°C)
fCPP is represented by the shaded area.
3.6
3.0
0 2.94
25
50
fCP, fCPP
(MHz)
Internal clock
87
MB91350A Series
• External/internal clock setting range
Oscillation input clock fC = 12.5 MHz
(MHz)
fCP
50
Internal clock
CPU (CLKB) :
Peripheral
External bus(CLKT) :
fCPP,
fCPT
25
12.5
CPU :
4:4
2:2
1:2
Notes : • When the PLL is used, the external clock input must fall between 10.0 and 12.5 MHz.
• Set the PLL oscillation stabilization wait time longer than 454.5 µs. The internal clock gear setting should
not exceed the relevant value in the table in “(1) Clock timing ratings”.
88
MB91350A Series
(2)Clock output timing
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Conditions
Symbol
Pin
Cycle time
tCYC
MCLK,
SYSCLK
SYSCLK ↑→ SYSCLK ↓
tCHCL
MCLK,
SYSCLK
SYSCLK ↓→ SYSCLK ↑
tCLCH
MCLK,
SYSCLK
⎯
Value
Unit
Remarks
Min
Max
tCPT
⎯
ns
*1
tCYC − 5
tCYC + 5
ns
*2
tCYC − 5
tCYC + 5
ns
*3
*1 : tCYC is the frequency of one clock cycle after gearing.
*2 : The following ratings are for the gear ratio set to × 1. For the ratings when the gear ratio is set to between 1/2,
1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation.
(1 / 2 × 1 / n ) × tCYC − 10
*3 : The following rating are for the gear ratio set to × 1.
Note : tCPT indicates the internal operating clock cycle time. See “(1) Clock timing”.
In the following AC ratings, MCLK is equivalent to SYSCLK.
tCYC
tCHCL
MCLK
SYSCLK
tCLCH
VOH
VOH
VOL
(3) Reset and hardware standby ratings
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
INIT input time
(at power-on)
INIT input time
(other than at power-on)
Symbol
tINTL
Pin
INIT
Conditions
Value
Min
Max
tC × 10
⎯
Unit
Remarks
ns
⎯
tC × 10
ns
Note : tC indicates the clock cycle time. See “(1) Clock timing”.
tINTL
INIT
0.2 VCC
89
MB91350A Series
(4) Normal bus access read/write operation
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
CS0 to CS3 setup
CS0 to CS3 hold
Symbol
tCSLCH
tCSDLCH
Pin
Conditions
AWRxL*3 : W02 = 0
MCLK,
AWR0L : W02 = 1
CS0 to CS3
tCHCSH
Value
Unit
Min
Max
3
⎯
ns
−3
⎯
ns
3
tCYC/2 + 6
ns
3
⎯
ns
3
⎯
ns
tASCH
MCLK,
A23 to A00
tASWL
WR0, WR1,
A23 to A00
tASRL
RD,
A23 to A00
3
⎯
ns
tCHAX
MCLK,
A23 to A00
3
tCYC/2 + 6
ns
tWHAX
WR0, WR1,
A23 to A00
3
⎯
ns
tRHAX
RD,
A23 to A00
3
⎯
ns
Valid address →
Valid data input time
tAVDV
A23 to A00,
D31 to D16
⎯
3 / 2 × tCYC − 15
ns
WR0, WR1 delay time
tCHWL
⎯
6
ns
WR0, WR1 delay time
tCHWH
MCLK,
WR0, WR1
⎯
6
ns
WR0, WR1 minimum
pulse width
tWLWH
WR0, WR1
tCYC − 5
⎯
ns
Data setup → WRx ↑
tDSWH
tCYC
⎯
ns
WRx ↑ → Data hold time
tWHDX
WR0, WR1,
D31 to D16
3
⎯
ns
RD delay time
tCHRL
⎯
6
ns
RD delay time
tCHRH
⎯
6
ns
RD ↓ →
Valid data input time
tRLDV
⎯
tCYC − 10
ns
Data setup →RD ↑ Time
tDSRH
10
⎯
ns
RD ↓ → Data hold time
tRHDX
0
⎯
ns
RD minimum pulse width
tRLRH
RD
tCYC − 5
⎯
ns
AS setup
tASLCH
3
⎯
ns
AS hold
tCHASH
MCLK,
AS
3
tCYC/2 + 6
ns
Address setup
Address hold
⎯
⎯
MCLK,
RD
RD,
D31 to D16
Remarks
*1
*2
*1
*1 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC × the number of
cycles added for the delay) to this rating.
*2 : The following ratings are for the gear ratio set to × 1. For the ratings when the gear ratio is set to between 1/2 to
1/16, substitute 1/2 to 1/16 for n in the following equation.
Calculation expression: 3/(2n) × tCYC − 15
*3 : AWRxL : Area Wait Register
Note : tCYC indicates the cycle time. See “(2) Clock output timing”.
90
MB91350A Series
tCYC
BA1
MCLK
VOH
VOH
VOH
tASLCH
VOH
tCHASH
VOH
AS
(LBA)
VOL
tCSLCH
CS0 to CS3
tCHCSH
VOH
VOL
tASCH
A23 to A00
tCHAX
VOH
VOL
VOH
VOL
tCHRH
tCHRL
tRLRH
RD
VOH
VOL
tASRL
tRHAX
tRHDX
tRLDV
tDSRH
tAVDV
D31 to D16
VOH
VOL
tCHWL
VOH
VOL
tCHWH
tWLWH
VOH
WR0, WR1
tASWL
VOL
tWHAX
tDSWH
D31 to D16
VOH
VOL
write
tWHDX
VOH
VOL
91
MB91350A Series
(5) Multiplex bus access read/write operation
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
AD15 to AD0 Address
AUDI setup time
→ MCLK ↑
tASCH
MCLK ↑ →
AD15 to AD0 Address
AUDI Hold Time
tCHAX
AD15 to AD0 Address
AUDI setup time → AS ↑
tASASH
AS ↑ →
AD15 to AD0 Address
AUDI Hold Time
tASHAX
Pin
Conditions
Value
Unit
Min
Max
3
⎯
ns
3
tCYC/2 + 6
ns
12
⎯
ns
tCYC − 3
tCYC + 3
ns
Remarks
MCLK,
D31 to D16
⎯
AS,
D31 to D16
Notes : • This rating is not guaranteed when the CS→RD/WR, and setup delay setting by AWR: bit 1 is “0”.
• Beside This rating, normal bus interface ratings are applicable.
• tCYC indicates the cycle time. See “(2) Clock output timing”.
tCYC
BA1
MCLK
VOH
VOH
VOH
VOH
VOH
AS
VOL
tASASH
tASCH
D31 to D16
92
VOH
VOL
tASHAX
tCHAX
VOH
VOL
MB91350A Series
(6) Ready input timings
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to +85°C)
Parameter
Symbol
Pin
Conditions
RDY setup time →
MCLK ↓
tRDYS
MCLK,
RDY
MCLK ↑ →
RDY hold time
tRDYH
MCLK,
RDY
Value
Unit
Min
Max
⎯
15
⎯
ns
⎯
0
⎯
ns
Remarks
tCYC
VOH
MCLK
VOH
VOL
VOL
tRDYS
tRDYS
tRDYH
tRDYH
RDY
with wait
VOH
VOL
VOH
VOL
RDY
without wait
VOH
VOH
VOL
VOL
93
MB91350A Series
(7) Hold timing
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
BRQ setup time
→ MCLK ↑
tBRQS
MCLK ↑ → BRQ
AUDI Hold Time
tBRQH
BGRNT delay time
tCHBGL
BGRNT delay time
tCHBGH
Pin floating →
BGRNT ↓ time
tXZBGL
BGRNT ↑ →
Pin valid time
tBGHXV
Pin
Conditions
MCLK,
BRQ
Value
Unit
Min
Max
15
⎯
ns
0
⎯
ns
tCYC/2 − 6
tCYC/2 + 6
ns
tCYC/2 − 6
tCYC/2 + 6
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
⎯
MCLK,
BGRNT
⎯
BGRNT,
D31 to D16,
A23 to A00,
CS3 to CS0*
* : These are applied to only the case that SREN bit of area select register (ACR) is set to “1”.
Notes : • It takes 1 cycle or more from when BRQ is captured until BGRNT changes.
• tCYC indicates the cycle time. See “(2) Clock output timing”.
tCYC
VOH
MCLK
VOH
VOH
VOH
tBRQS
tBRQH
VOL
BRQ
VOH
tCHBGH
tCHBGL
BGRNT
VOH
VOL
tXZBGL
D31 to D16,
A23 to A00,
CS3 to CS0 *
tBGHXV
High-Z
* : These are applied to only the case that SREN bit of area select register (ACR) is set to “1”.
94
Remarks
MB91350A Series
(8) UART, SIO timing
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
Pin
Conditions
Serial clock cycle time
tSCYC
SCK0 to SCK7
SCK ↓ →
BGRNT delay time
tSLOV
Valid SI → SCK ↑
tIVSH
SCK ↑ → valid SIN hold
time
tSHIX
Serial clock H Pulse Width
Value
Unit
Min
Max
8 tCPP
⎯
ns
− 80
+ 80
ns
100
⎯
ns
SCK0 to SCK7,
SI0 to SI7
60
⎯
ns
tSHSL
SCK0 to SCK7
4 tCPP
⎯
ns
Serial clock L Pulse Width
tSLSH
SCK0 to SCK7
4 tCPP
⎯
ns
SCK ↓ → SO delay time
tSLOV
⎯
150
ns
Valid SI → SCK ↑
tIVSH
60
⎯
ns
SCK ↑ → valid SI hold
time
tSHIX
60
⎯
ns
SCK0 to SCK7,
SO0 to SO7 Internal shift
SCK0 to SCK7, clock
mode
SI0 to SI7
SCK0 to SCK7,
External
SO0 to SO7
shift clock
SCK0 to SCK7, mode
SI0 to SI7
SCK0 to SCK7,
SI0 to SI7
Remarks
Notes : • Above rating is for CLK synchronous mode.
• tCPP indicates the peripheral clock cycle time. See “(1) Clock timing”.
• Internal shift clock mode
tSCYC
SCK0 to SCK7
VOH
VOL
VOL
tSLOV
VOH
VOL
SO0 to SO7
tIVSH
tSHIX
VOH
VOL
VOH
VOL
SI0 to SI7
• External shift clock mode
tSLSH
tSHSL
VOH
SCK0 to SCK7
VOL
VOL
VOL
tSLOV
SO0 to SO7
VOH
VOL
tIVSH
SI0 to SI7
VOH
VOL
tSHIX
VOH
VOL
95
MB91350A Series
(9) Free-run timer clock, PPG timer input timing
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
Pin
Conditions
tTIWH
tTIWL
FRCK,
TRG0 to TRG5,
AIN0 to AIN1,
BIN0 to BIN1,
ZIN0 to ZIN1
⎯
Input pulse width
Value
Min
Max
2 tCPP
⎯
Unit
Remarks
ns
Note : tCPP indicates the peripheral clock cycle time. See “(1) Clock timing”.
tTIWL
tTIWH
(10) Trigger input timing
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
Pin
Conditions
A/D activation trigger input
time
tATGX
ATG
tINP
IN0 to IN3
input capture
input trigger
Value
Max
⎯
5 tCPP
⎯
ns
⎯
5 tCPP
⎯
ns
Note : tCPP indicates the peripheral clock cycle time. See “(1) Clock timing”.
tATGX, tINP
ATG,
IN0 to IN3
96
Unit
Min
Remarks
MB91350A Series
(11)DMA controller timing
• For edge detection (block/step transfer mode,burst transfer mode)
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
Pin
Conditions
DREQ Input pulse width
tDRWL
DREQ 0 to DREQ2
DREQ Input pulse width
tDSWH
DSTP 0 to DSTP2
⎯
Value
Unit Remarks
Min
Max
2 tCYC*
⎯
ns
2 tCYC*
⎯
ns
* : tCYC becomes tCP when fCPT is greater than fCP.
• For level detection (demand transfer mode)
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Value
Conditions
Symbol
Pin
DREQ setup time
tDRS
MCLK, DREQ 0 to DREQ2
DREQ Hold Time
tDRH
MCLK, DREQ 0 to DREQ2
DSTP setup time
tDSTPS
MCLK, DSTP 0 to DSTP2
DSTP Hold Time
tDSTPH
MCLK,DSTP 0 to DSTP2
⎯
Unit Remarks
Min
Max
15
⎯
ns
0.0
⎯
ns
15
⎯
ns
0.0
⎯
ns
• Common operation mode
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
Pin
AWRxL* :
W02 = 0
tDALCH
DACK delay time
DEOP delay time
tDADLCH
MCLK,
DACK 0 to
DACK2
AWR0L :
W02 = 1
tCHDAH
⎯
tDELCH
AWR0L :
W02 = 0
tDEDLCH
MCLK,
DEOP 0 to
DEOP2
tCHIRL
tCHIRH
tCHIWL
AWRxL* :
W02 = 1
⎯
tCHDEH
IORD delay time
Conditions
MCLK,
IORD
Value
Unit
Max
3
⎯
ns
CS timing
⎯
6
ns
FR30 compatible
−3
⎯
ns
CS timing
⎯
6
ns
FR30 compatible
⎯
tCYC/2 + 6
ns
CS timing
⎯
6
ns
FR30 compatible
3
⎯
ns
CS timing
⎯
6
ns
FR30 compatible
−3
⎯
ns
CS timing
⎯
6
ns
FR30 compatible
⎯
tCYC/2 + 6
ns
CS timing
⎯
6
ns
FR30 compatible
⎯
6
ns
⎯
6
ns
⎯
6
ns
⎯
6
ns
tCHIWH
MCLK,
IOWR
IORD minimum pulse width
tIRLIRH
IORD
12
⎯
ns
IOWR minimum pulse width
tIWLIWH
IOWR
12
⎯
ns
IOWR delay time
⎯
Remarks
Min
* : AWRxL: Area Wait Register.
Note : tCYC indicates the cycle time. See “(2) Clock output timing”.
97
MB91350A Series
tCYC
VOH
MCLK
VOH
VOL
VOL
VOL
tDRWL
tDRS
tDRH
VOH
DREQ0 to DREQ2
VOL
tDSWH
tDSTPS
tDSTPH
VOH
DSTP0 to DSTP2
VOL
tCHIRL
tCHIRH
tIRLIRH
VOH
IORD
VOL
tCHIWL
tCHIWH
tIWLIWH
VOH
IOWR
VOL
RD,
WRn
VOL
Chip select
timing
DACK0 to DACK2
VOH
tDALCH
tDADLCH
tCHDAH
VOH
VOL
tDELCH
tDEDLCH
DEOP0 to DEOP2
FR30 compatible
timing
tCHDEH
VOH
VOL
tDALCH
tDADLCH
tCHDAH
VOH
DACK0 to DACK2
VOL
tDELCH
tDEDLCH
tCHDEH
VOH
DEOP0 to DEOP2
98
VOL
MB91350A Series
(12) I2C Timing
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
Condition
Standard-mode
Fast-mode*4
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” width of the SCL clock
tHIGH
4.0
⎯
0.6
⎯
µs
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
4.7
⎯
0.6
⎯
µs
Data hold time
SCL↓→SDA↓↑
tHDDAT
0
3.45*2
0
0.9*3
µs
Data set-up time
SDA↓↑→SCL↑
tSUDAT
250
⎯
100
⎯
ns
Set-up time for STOP condition
SCL↑→SDA↑
tSUSTO
4.0
⎯
0.6
⎯
µs
tBUS
4.7
⎯
1.3
⎯
µs
SCL clock frequency*4
Hold time (repeated) START condition
SDA↓→SCL↓
Bus free time between a STOP and START
condition
R = 1.0 kΩ,
C = 50 pF*1
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA
tHDSTA
tSUDAT
tLOW
tBUS
SCL
tHIGH
tHDSTA
tHDDAT
tSUSTA
tSUSTO
99
MB91350A Series
5. Electrical Characteristics for the A/D Converter
(VCC = AVCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, AVRH = 3.0 V to 3.6 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
Pin
⎯
Value
Unit
Remarks
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
− 5.0
⎯
+ 5.0
LSB
⎯
⎯
− 3.5
⎯
+ 3.5
LSB
⎯
⎯
− 2.5
⎯
+ 2.5
LSB
⎯
AN11
to AN0
AVRL − 2.0
AVRL + 1.0
AVRL + 6.0
LSB
Full-transition voltage*1
⎯
AN11
AVRH − 5.5
to AN0
AVRH + 1.5
AVRH + 3.0
LSB
Conversion time
⎯
1.48*2
⎯
300
µs
Analog power supply current
(analog + digital)
IA
⎯
8
⎯
mA
⎯
⎯
5
µA
At stop
⎯
470
⎯
µA
AVRH = 3.0 V,
AVRL = 0.0 V
⎯
⎯
10
µA
At stop
Resolution
Total error*
1
Nonlinear error*
1
Differential linear error*1
Zero transition voltage*
1
IAH
⎯
AVCC
Reference power supply
current
(between AVRH and AVRL)
IRH
Analog input capacitance
⎯
AN11
to AN0
⎯
40
⎯
pF
Interchannel disparity
⎯
AN11
to AN0
⎯
⎯
4
LSB
IR
AVRH
AVcc = 3.3 V,
AVRH = 3.3 V
*1: Measured in the CPU sleep state
*2: When the peripheral resource clock frequency is 25.0 MHz, set the Conversion Time Setting Register (ADCT)
to a value equal to or greater than 5334H.
Set each bit as follow :
Sampling time
: SAMP3 to SAMP0 ≥ 5H
Conversion time a : CV03 to CV0 ≥ 3H
Conversion time b : CV13 to CV0 ≥ 3H
Conversion time c : CV23 to CV0 ≥ 4H
100
MB91350A Series
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Comparator
Analog input
C
During Sampling : ON
R
0.18 kΩ (Max)
0.18 kΩ (Max)
0.18 kΩ (Max)
MB91355A
MB91F355A
MB91F356B
Note : The values are reference values.
C
63.0 pF (Max)
39.0 pF (Max)
39.0 pF (Max)
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
MB91F355A/MB91F356B
100
90
80
70
60
50
40
30
20
10
0
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
MB91355A
0
5
10
15
20
25
30
35
MB91F355A/MB91F356B
20
18
16
14
12
10
8
6
4
2
0
MB91355A
0
Minimum sampling time [µs]
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As |AVRH-AVSS| becomes smaller, values of relative errors grow larger.
101
MB91350A Series
Definition of A/D Converter Terms
• Resolution
Analog variation that is recognized by an A/D converter.
• Linearity error
Zero transition point ( "0000000000” - “0000000001”) and full-scale transition point
Difference between the line connected (“1111111110” - “1111111111”) and actual conversion characteristics.
• Differential linear error
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Linearity error
Differential linear error
Actual conversion
characteristic
3FFH
Actual conversion
characteristic
N+1
3FEH
{1 LSB' (N − 1) + VOT}
VFST
(measurement value)
004H
VNT
003H
(measurement value)
Actual conversion
characteristic
Ideal characteristics
002H
Digital output
Digital output
3FDH
Ideal characteristics
N
(measurement
value)
VNT
(measurement value)
N−2
001H
VOT (measurement value)
AVSS
V(N+1)T
N−1
Actual conversion characteristic
AVRH
AVSS
AVRH
Analog input
Analog input
Linear error in digital output N = VNT − {1 LSB’ × (N − 1) + {VOT} [LSB]
1 LSB’
Differential linear error in digital output N =
1 LSB =
VFST − VOT
1022
V (N + 1) T − VNT
1 LSB’
− 1 [LSB]
[V]
VOT: A voltage at which digital output transitions from (000)H to (001)H.
VFST: A voltage at which digital output transitions from (3FE)H to (3FF)H.
VNT: A voltage at which digital output transitions from (N - 1) to N.
102
MB91350A Series
• Total error
This error indicates the difference between actual and ideal values, including the zero transition error/full-scale
transition error/linearity error.
Total error
3FFH
Actual conversion
characteristic
3FEH
1.5 LSB'
Digital output
3FDH
{1 LSB' (N − 1) + 0.5 LSB'}
004H
VNT
(measurement
value)
003H
Actual
characteristics
002H
Ideal characteristics
001H
0.5 LSB'
AVSS
AVRH
Analog input
1LS’ (Ideal value) 1 =
AVRH − AVSS
1024
Total error of digital output N =
[V]
VNT − {1 LSB’ × (N − 1) × {0.5 LSB’}
1 LSB’
VNT: A voltage at which digital output transitions from (N + 1) to (N).
VOT’(Ideal value) = AVSS + {0.5 LSB’ [V]
VFST’(Ideal value) = AVRH − 1.5 LSB’ [V]
103
MB91350A Series
6. Electrical Characteristics for the D/A Converter
(VCC = DAVC = 3.0 V = 3.6 V, VSS = DAVS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
Pin
Resolution
⎯
Nonlinear error
Differential linear error
Convertion speed
Output high impedance
Unit
Remarks
Min
Typ
Max
⎯
⎯
⎯
8
bit
⎯
⎯
− 2.0
⎯
+ 2.0
LSB
When the output is unloaded
⎯
⎯
− 1.0
⎯
+ 1.0
LSB
When the output is unloaded
⎯
⎯
⎯
0.6
⎯
µs
When load capacitance (CL) = 20 pF
⎯
⎯
⎯
3.0
⎯
µs
When load capacitance (CL) = 100 pF
⎯
DA0 to
DA2
2.0
2.9
3.8
kΩ
⎯
40
⎯
µA
10 µs conversion when the output is
unloaded
⎯
⎯
460*
µA
Input digital code
When fixed at 7AH or 85H
⎯
0.1
⎯
µA
At power-down
⎯
Analog current
Value
IADA
IADAH
DAVC
* : This D/A converter varies in current consumption depending on each input digital code.
This rating indicates the current consumption when the digital code that maximizes current consumption is input.
104
MB91350A Series
■ FLASH MEMORY WRITE/ERASE CHARACTERISTICS
Parameter
Condition
Flash data retention
time
Remarks
Typ
Max
⎯
1
15
s
Excludes 00H programming
prior erasure.
⎯
8
⎯
s
Excludes 00H programming
prior erasure.
⎯
16
3,600
µs
Excludes system-level
overhead.
⎯
⎯
10,000
⎯
cycle
Average
Ta = +85°C
20
⎯
⎯
year
Ta = +25 °C,
VCC = 3.3 V
Half word (16-bit
width) writing time
Write/erase cycle
Unit
Min
Sector erase time
Chip erase time
Value
*
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85°C).
105
MB91350A Series
■ EXAMPLE CHARACTERISTICS
(1) “H” level output voltage
(2) “L” level output voltage
VOH - VCC
500
VOL1 [mV]
VOH [V]
4
VOL1 - VCC
Ta = +25 °C
3
2
1
2.7
3.0
3.3
3.6
400
300
200
100
0
2.7
0
3.9
3.0
VCC [V]
ILI - VCC
Ta = +25 °C
400
300
200
100
0
2.7
3.0
3.3
3.6
3.9
(4) Input leak current
ILI [µA]
VOL2 [mV]
500
3.3
VCC [V]
(3) “L” level output voltage (Nch open-drain)
VOL2 - VCC
Ta = +25 °C
3.6
3.9
VCC [V]
6
4
2
0
−2
−4
−6
2.7
3.0
3.3
Ta = +25 °C
3.6
3.9
VCC [V]
(5) Pull-up resistance
RUP - VCC
RUP [kΩ]
200
Ta = +25 °C
160
120
80
40
0
2.7
3.0
3.3
3.6
3.9
VCC [V]
(Continued)
106
MB91350A Series
(6) Power supply current
(7) Power supply current
ICC - fC
Ta = +25 °C, fCP = 50 MHz,
fCCP = fCPT = 25 MHz
300
250
200
150
100
50
0
2.7
ICC [mA]
ICC [mA]
ICC - VCC
Ta = +25 °C, VCC = 3.3 V,
fCP = 4 × fC (multiplied by 4)
300
250
200
150
100
50
0
3.0
3.3
3.6
3.9
1
10
VCC [V]
(8) Power supply current at sleep
(9) Power supply current at sleep
ICCS - fC
Ta = +25 °C, fCP = 50 MHz,
fCCP = fCPT = 25 MHz
50
0
2.7
ICCS [mA]
ICCS [mA]
ICCS - VCC
300
250
200
150
100
Ta = +25 °C, VCC = 3.3 V,
fCP = 4 × fC (multiplied by 4)
300
250
200
150
100
50
0
3.0
3.3
3.6
3.9
1
10
VCC [V]
(11) Sub RUN power supply current
ICCL - VCC
Ta = +25 °C, fCP = 32 kHz,
fCCP = fCPT = 32 kHz
Ta = +25 °C
500
400
20
0
−20
2.7
ICCL [µA]
ICCH [µA]
ICCH - VCC
100
80
60
40
100
fC [MHz]
(10) Power supply current at stop
3.0
3.3
3.6
300
200
100
0
2.7
3.9
3.0
VCC [V]
ICCT [µA]
400
300
200
100
0
3.0
3.3
VCC [V]
3.9
ICCT - VCC
Ta = +25 °C, fCP = 32 kHz,
fCCP = fCPT = 32 kHz
2.7
3.6
(13) Watch mode power supply current
ICCLS - VCC
500
3.3
VCC [V]
(12) Sub sleep power supply current
ICCLS [µA]
100
fC [MHz]
3.6
3.9
100
80
60
40
20
0
−20
2.7
Ta = +25 °C, fCP = 32 kHz,
fCCP = fCPT = 32 kHz
3.0
3.3
3.6
3.9
VCC [V]
(Continued)
107
MB91350A Series
(Continued)
(14) A/D converter power supply current
IA - VCC
IR - VCC
Ta = +25 °C
1000
8
800
6
600
IR [µA]
IA [mA]
10
(15) A/D converter reference power supply voltage
4
2
0
2.7
3.0
3.3
3.6
400
200
0
2.7
3.9
3.0
VCC [V]
IRH - VCC
Ta = +25 °C
10
20
0
2.7
Ta = +25 °C
10
0
3.0
3.3
3.6
2.7
3.9
3.0
VCC [V]
IADA - VCC
500
3.3
3.6
3.9
VCC [V]
(18) D/A converter power supply current
< per 1 channel >
(19) D/A converter power supply current at power down
IADAH - VCC
Ta = +25 °C
20
IADAH [µA]
400
IADA [µA]
3.9
−10
−10
300
200
100
Ta = +25 °C
10
0
−10
0
2.7
3.0
3.3
VCC [V]
108
3.6
(17) A/D converter reference power supply current at stop
IRH [µA]
IAH [µA]
20
3.3
VCC [V]
(16) A/D converter power supply current at stop
IAH - VCC
Ta = +25 °C
3.6
3.9
2.7
3.0
3.3
VCC [V]
3.6
3.9
MB91350A Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB91F355APMT-002
176-pin plastic LQFP
(FPT-176P-M02)
Lead-free Package
MB91F356BPMT
176-pin plastic LQFP
(FPT-176P-M02)
Lead-free Package
MB91355APMT
176-pin plastic LQFP
(FPT-176P-M02)
Lead-free Package
MB91354APMT
176-pin plastic LQFP
(FPT-176P-M02)
Lead-free Package
109
MB91350A Series
■ PACKAGE DIMENSION
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25 (.010) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
176-pin plastic LQFP
(FPT-176P-M02)
26.00±0.20(1.024±.008)SQ
* 24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0˚~8˚
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
45
"A"
LEAD No.
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
2003 FUJITSU LIMITED F176006S-c-4-6
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
110
MB91350A Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0505
© 2005 FUJITSU LIMITED Printed in Japan