CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the outputs to the clock input • Conforms to the DDRI specification • Spread Aware for electromagnetic interference (EMI) reduction • 48-pin SSOP package Block Diagram This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential outputs levels. This device is a zero delay buffer that distributes a clock input (CLKIN) to ten differential pairs of clock outputs (YT[0:9], YC[0:9]) and one feedback clock output (FBOUT). The clock outputs are individually controlled by the serial inputs SCLK and SDATA. The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for the test purposes. The PLL in this device uses the input clock (CLKIN) and the feedback clock (FBIN) to provide high-performance, low-skew, low-jitter output differential clocks. Pin Configuration YT0 YC0 YT1 YC1 YT2 YC2 SCLK SDATA YT3 YC3 Serial Interface Logic YT4 YC4 YT5 YC5 YT6 YC6 CLKIN YT7 YC7 PLL YT8 YC8 FBIN YT9 YC9 AVDD FBOUT Cypress Semiconductor Corporation Document #: 38-07370 Rev. *B • VSS YC0 YT0 VDDQ YT1 YC1 VSS VSS YC2 YT2 VDD SCLK CLKIN NC VDDI AVDD AVSS VSS YC3 YT3 VDDQ YT4 YC4 VSS 3901 North First Street • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CY28351 10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS YC5 YT5 VDDQ YT6 YC6 VSS VSS YC7 YT7 VDDQ SDATA NC FBIN VDDQ FBOUT NC VSS YC8 YT8 VDDQ YT9 YC9 VSS San Jose, CA 95134 • 408-943-2600 Revised May 23, 2003 CY28351 Pin Description[1] Pin Number Pin Name I/O Pin Description Electrical Characteristics 13 CLKIN I Clock Input. Input 35 FBIN I Feedback Clock Input. Connect to FBOUT for accessing the PLL. Input 3, 5, 10, 20, 22 46, 44, 39, 29, 27 YT(0:9) O Clock Outputs. Differential Outputs 2, 6, 9, 19, 23 47, 43, 40, 30, 26 YC(0:9) O Clock Outputs. 33 FBOUT O Feedback Clock Output. Connect to FBIN for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 12 SCLK I Serial Clock Input. Clocks data at SDATA into the Data Input for the two-line serial internal register. bus 37 SDATA I/O Output Serial Data Input. Input data is clocked to the Data Input and Output for the internal register to enable/disable individual outputs. two-line serial bus This provides flexibility in power management. 11 VDD 2.5V Power Supply for Logic. 2.5V Nominal 4, 21, 28, 34, 38, 45 VDDQ 2.5V Power Supply for Output Clock Buffers. 2.5V Nominal 16 AVDD 2.5V Power Supply for PLL. 2.5V Nominal 15 VDDI 2.5V Power Supply for Two-line Serial Interface. 2.5V Nominal 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 VSS Common Ground. 0.0V Ground 17 AVSS Analog Ground. 0.0V Analog Ground 14, 32,36 NC – Not Connected. Zero Delay Buffer When used as a zero delay buffer, the CY28351 will likely be in a nested clock tree application. For these applications the CY28351 offers a clock input as a PLL reference. The CY28351 then can lock onto the reference and translate with near zero delay to low skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. When VDDA is strapped LOW, the PLL is turned off and bypassed for test purposes. Function Table Input VDDA Outputs CLKIN YT(0:9)[2] YC(0:9)[2] FBOUT PLL GND L L H L BYPASSED/OFF GND H H L H BYPASSED/OFF 2.5V L L H L On 2.5V H H L H On 2.5V < 20 MHz Hi-Z Hi-Z Hi-Z Off Notes: 1. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. 2. Each output pair can be three-stated via the two-line serial interface. Document #: 38-07370 Rev. *B Page 2 of 8 CY28351 Power Management Serial Control Registers The individual output enable/disable control of the CY28351 allows the user to implement unique power management schemes into the design. Outputs are three-stated when disabled through the two-line interface as individual bits are set LOW in Byte0 and Byte1 registers. The feedback output (FBOUT) cannot be disabled via two line serial bus. The enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. Following the acknowledge of the Address Byte, two additional bytes must be sent: • Command Code byte • Byte Count byte. Byte0: Output Register 1 (1 = Enable, 0 = Disable) Bit @Pup Pin# Description 7 1 3, 2 YT0, YC0 6 1 5, 6 YT1, YC1 5 1 10, 9 YT2, YC2 4 1 20, 19 YT3, YC3 3 1 22, 23 YT4, YC4 2 1 46, 47 YT5, YC5 1 1 44, 43 YT6, YC6 0 1 39, 40 YT7, YC7 Byte1: Output Register 2 (1 = Enable, 0 = Disable) Bit @Pup Pin# 7 1 29, 30 YT8, YC8 Description 6 1 27, 26 YT9, YC9 5 0 – Reserved 4 0 – Reserved 3 0 – Reserved 2 0 – Reserved 1 0 – Reserved 0 0 – Reserved Byte2: Test Register 3 Bit @Pup Pin# 7 1 – 0 = PLL leakage test, 1 = disable test 6 1 – Reserved 5 1 – Reserved 4 1 – Reserved 3 1 – Reserved 2 1 – Reserved 1 1 – Reserved 0 1 – Reserved Document #: 38-07370 Rev. *B Description Page 3 of 8 CY28351 Maximum Ratings[3] Input Voltage Relative to VSS:.............................. VSS – 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: .................................–65°C to +150°C Operating Temperature: .................................... 0°C to +70°C Maximum Power Supply: ................................................3.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range: VSS < (VIN or VOUT) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters VDD = VDDA = VDDQ = VDDI = 2.5V + 5%, TA = 0°C to +70°C[4] Parameter Description VIL Input Low Voltage Condition SDATA , SCLK Min. VIH VIL Input High Voltage Input Voltage Low SDATA , SCLK CLKIN, FBIN 2.2 VIH IIN Input Voltage High Input Current CLKIN, FBIN VIN = 0V or VIN = VDDQ, CLKT, FBIN 2.1 –10 IOL IOH Output Low Current Output High Current VDDQ = 2.375V, VOUT = 1.2V VDDQ = 2.375V, VOUT= 1V 26 –18 VOL VOH Output Low Voltage Output High Voltage VDDQ = 2.375V, IOL = 12 mA VDDQ = 2.375V, IOH = –12 mA 1.7 VOUT VOC Output Voltage Swing[5] Output Crossing Voltage[6] IOZ High-Impedance Output Current VO = GND or VO = VDDQ IDDQ IDSTAT Dynamic Supply Current[7] Static Supply Current All VDDQ and VDDI, FO = 170 MHz IDD CIN PLL Supply Current Input Pin Capacitance VDDA only Typ. Max. 1.0 Unit V 0.4 V V 10 V µA 35 –32 mA mA 0.6 V V 1.1 VDDQ – 0.4 (VDDQ/2) VDDQ/2 (VDDQ/2) – 0.2 + 0.2 –10 10 V V µA 235 300 1 mA mA 9 4 12 6 mA pF AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to + 70°C[8,9] Parameter Description fCLK tDC Operating Clock Frequency Input Clock Duty Cycle tLOCK Tr/Tf Maximum PLL lock Time Output Clocks Slew Rate tpZL, tpZH tpLZ, tpHZ Output Enable Time (all outputs)[10] Output Disable Time (all outputs)[10] tCCJ tjit(h-per) Cycle to Cycle Jitter[12] Half-period jitter[12] tPLH tPHL LOW-to-HIGH Propagation Delay, CLKIN to YT HIGH-to-LOW Propagation Delay, CLKIN to YT tSKEW tPHASE Any Output to Any Output Skew[11] Phase Error[11] tPHASEJ Phase Error Jitter Condition 20% to 80% of VOD Min. Typ. Max. Unit 60 40 200 MHz 60 % 1 100 µs 2.5 V/ns 3 3 f > 66 MHz f > 66 MHz –100 –100 100 100 ps ps 6 6 ns ns –150 100 150 ps ps –50 50 ps 1.5 1.5 f > 66 MHz ns ns 3.5 3.5 Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. unused inputs must be held HIGH or LOW to prevent them from floating. 5. For load conditions, see Figure 7. 6. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7. 7. All outputs switching loaded with 16 pF in 60Ω environment. See Figure 7. 8. Parameters are guaranteed by design and characterization. Not 100% tested in production 9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down spread of –0.5%. 10. Refers to transition of non-inverting output. 11. All differential input and output terminals are terminated with 120Ω/16 pF, as shown in Figure 7. 12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. Document #: 38-07370 Rev. *B Page 4 of 8 CY28351 Parameter Measurement Information CLKIN 1.25V 1.25V FBIN 1.25V 1.25V t(∅)n+1 t(∅)n t(∅)n = Σ n1=N t(∅)n (N is large number of samples) Figure 1. Static Phase Offset CLKIN 1.25V 1.25V FBIN td(∅) YT[0:9], FBOUT t(∅) td(∅) td(∅) t(∅ ) td(∅) Figure 2. Dynamic Phase Offset YC[0:9] YT[0:9], FBOUT YC[0:9] tsk(o) Figure 3. Output Skew Document #: 38-07370 Rev. *B Page 5 of 8 CY28351 YT[0:9], FBOUT YC[0:9] tc(n) YT[0:9], FBOUT YC[0:9] 1 f(o) tjit(hper) = tc(n) - 1 fo Figure 4. Period Jitter YT[0:9], FBOUT YC[0:9] t(hper_N+1) t(hper_n) 1 f(o) tjit(hper) = thper(n) - 1 2x fo Figure 5. Half-Period Jitter YT[0:9], FBOUT YC[0: 9] t c(n) t c(n) tjit(cc) = tc(n)-tc(n+1) Figure 6. Cycle-to-Cycle Jitter T PCB M easurem ent Point CLKT 16 pF CLKIN 110 Ω 50 Ω CLKC T PCB M easurem ent Point 16 pF FBIN 50 Ω FBO UT Figure 7. Differential Signal Using Direct Termination Resistor Document #: 38-07370 Rev. *B Page 6 of 8 CY28351 Ordering Information Part Number CY28351OC CY28351OCT Package Type Product Flow 48-pin SSOP Commercial, 0° to 70°C 48-pin SSOP–Tape and Reel Commercial, 0° to 70°C Package Drawing and Dimensions 48-lead Shrunk Small Outline Package O48 51-85061-*C Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07370 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28351 Document History Page Document Title: CY28351 Differential Clock Buffer/Driver, DDR400- and DDR333-Compliant Document Number: 38-07370 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 112786 05/08/02 DMG *A 122910 12/26/02 RBI Add power up requirements to maximum ratings information *B 127011 05/28/03 RGL Change the maximum operating clock frequency from 170 MHz to 200 MHz Added DDR400- and DDR333-Compliant in the title. Document #: 38-07370 Rev. *B New Data Sheet Page 8 of 8