Microchip MCP6V31UT-E/OT 23 î¼a, 300 khz zero-drift op amp Datasheet

MCP6V31/1U
23 µA, 300 kHz Zero-Drift Op Amps
Features
Description
• High DC Precision:
- VOS Drift: ±50 nV/°C (maximum)
- VOS: ±8 µV (maximum)
- AOL: 120 dB (minimum, VDD = 5.5V)
- PSRR: 120 dB (minimum, VDD = 5.5V)
- CMRR: 120 dB (minimum, VDD = 5.5V)
- Eni: 1.0 µVP-P (typical), f = 0.1 Hz to 10 Hz
- Eni: 0.33 µVP-P (typical), f = 0.01 Hz to 1 Hz
• Low Power and Supply Voltages:
- IQ: 23 µA/amplifier (typical)
- Wide Supply Voltage Range: 1.8V to 5.5V
• Small Packages
- Singles in SC70, SOT-23
• Easy to Use:
- Rail-to-Rail Input/Output
- Gain Bandwidth Product: 300 kHz (typical)
- Unity Gain Stable
• Extended Temperature Range: -40°C to +125°C
The Microchip Technology Inc. MCP6V31/1U family of
operational amplifiers provides input offset voltage
correction for very low offset and offset drift. These are
low power devices, with a gain bandwidth product of
300 kHz (typical). They are unity gain stable, have no
1/f noise, and have good Power Supply Rejection Ratio
(PSRR) and Common Mode Rejection Ratio (CMRR).
These products operate with a single supply voltage as
low as 1.8V, while drawing 23 µA/amplifier (typical) of
quiescent current.
Typical Applications
•
•
•
•
•
Portable Instrumentation
Sensor Conditioning
Temperature Measurement
DC Offset Correction
Medical Instrumentation
The Microchip Technology Inc. MCP6V31/1U op amps
are offered in single (MCP6V31 and MCP6V31U)
packages. They were designed using an advanced
CMOS process.
Package Types
MCP6V31
SOT-23
VOUT 1
5 VDD
VIN+ 1
5 VDD
VSS 2
VIN+ 3
4 VIN–
VSS 2
VIN– 3
4 VOUT
Typical Application Circuit
VIN
SPICE Macro Models
FilterLab® Software
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
R1
R2
Design Aids
•
•
•
•
•
MCP6V31U
SC70, SOT-23
R3
VOUT
R4
C2
U1
R5
R2
VDD/2
U2
MCP6XXX
VDD/2
MCP6V31
Offset Voltage Correction for Power Driver
Related Parts
•
•
•
•
MCP6V01/2/3: Auto-Zeroed, Spread Clock
MCP6V06/7/8: Auto-Zeroed
MCP6V26/7/8: Auto-Zeroed, Low Noise
MCP6V11/1U: Zero-Drift, Low Power
© 2012 Microchip Technology Inc.
DS25127A-page 1
MCP6V31/1U
NOTES:
DS25127A-page 2
© 2012 Microchip Technology Inc.
MCP6V31/1U
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Absolute Maximum Ratings †
VDD – VSS .................................................................................................................................................................6.5V
Current at Input Pins ..............................................................................................................................................±2 mA
Analog Inputs (VIN+ and VIN–) (Note 1) .....................................................................................VSS – 1.0V to VDD+1.0V
All other Inputs and Outputs .......................................................................................................VSS – 0.3V to VDD+0.3V
Difference Input voltage .................................................................................................................................|VDD – VSS|
Output Short Circuit Current ........................................................................................................................... Continuous
Current at Output and Supply Pins ...................................................................................................................... ±30 mA
Storage Temperature .............................................................................................................................-65°C to +150°C
Maximum Junction Temperature .......................................................................................................................... +150°C
ESD protection on all pins (HBM, CDM, MM) ........................................................................................... ≥ 2 kV, 1.5 kV, 400V
Note 1: See Section 4.2.1, Rail-to-Rail Inputs.
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1.2
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,
VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset Voltage
VOS
-8
—
+8
µV
Input Offset Voltage Drift with
Temperature (Linear Temp. Co.)
TC1
-50
—
+50
nV/°C TA = -40 to +125°C
(Note 1)
Input Offset Voltage Quadratic
Temp. Co.
TC2
—
±0.08
—
nV/°C2 TA = -40 to +125°C
PSRR
120
135
—
Input Bias Current
IB
—
+5
—
pA
Input Bias Current across Temperature
IB
—
+20
—
pA
TA = +85°C
+2.9
+5
nA
TA = +125°C
—
pA
Input Offset
Power Supply Rejection
TA = +25°C
dB
Input Bias Current and Impedance
IB
0
Input Offset Current
IOS
—
±130
Input Offset Current across Temperature
IOS
—
±140
—
pA
TA = +85°C
IOS
-1
±0.4
+1
nA
TA = +125°C
—
Ω||pF
—
Ω||pF
Common Mode Input Impedance
ZCM
—
1013||6
Differential Input Impedance
ZDIFF
—
1013||6
Note 1:
2:
For Design Guidance only; not tested.
Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot.
© 2012 Microchip Technology Inc.
DS25127A-page 3
MCP6V31/1U
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,
VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Common-Mode
Input Voltage Range Low
VCML
—
—
VSS − 0.15
V
(Note 2)
Common-Mode
Input Voltage Range High
VCMH
VDD + 0.2
—
—
V
(Note 2)
Common-Mode Rejection
CMRR
110
125
—
dB
VDD = 1.8V,
VCM = -0.15V to 2.0V
(Note 2)
CMRR
120
135
—
dB
VDD = 5.5V,
VCM = -0.15V to 5.7V
(Note 2)
AOL
103
125
—
dB
VDD = 1.8V,
VOUT = 0.3V to 1.6V
AOL
120
135
—
dB
VDD = 5.5V,
VOUT = 0.3V to 5.3V
VOL
VSS
VSS + 14
VSS + 45
mV
RL = 10 kΩ, G = +2,
0.5V input overdrive
VOL
—
VSS + 1.4
—
mV
RL = 100 kΩ, G = +2,
0.5V input overdrive
VOH
VDD – 45
VDD – 14
VDD
mV
RL = 10 kΩ, G = +2,
0.5V input overdrive
VOH
—
VDD – 1.4
—
mV
RL = 100 kΩ, G = +2,
0.5V input overdrive
ISC
—
±6
—
mA
VDD = 1.8V
ISC
—
±21
—
mA
VDD = 5.5V
VDD
1.8
—
5.5
V
IQ
12
23
34
µA
VPOR
0.9
—
1.6
V
Common Mode
Open-Loop Gain
DC Open-Loop Gain (large signal)
Output
Minimum Output Voltage Swing
Maximum Output Voltage Swing
Output Short Circuit Current
Power Supply
Supply Voltage
Quiescent Current per amplifier
POR Trip Voltage
Note 1:
2:
IO = 0
For Design Guidance only; not tested.
Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot.
DS25127A-page 4
© 2012 Microchip Technology Inc.
MCP6V31/1U
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
GBWP
—
300
—
kHz
Slew Rate
SR
—
0.13
—
V/µs
Phase Margin
PM
—
70
—
°
Eni
—
0.33
—
µVP-P
f = 0.01 Hz to 1 Hz
µVP-P
f = 0.1 Hz to 10 Hz
Amplifier AC Response
Gain Bandwidth Product
G = +1
Amplifier Noise Response
Input Noise Voltage
Eni
—
1.0
—
Input Noise Voltage Density
eni
—
50
—
nV/√Hz f < 2 kHz
Input Noise Current Density
ini
—
5
—
fA/√Hz
IMD
—
52
—
µVPK
Amplifier Distortion (Note 1)
Intermodulation Distortion (AC)
VCM tone = 50 mVPK at 100 Hz, GN = 1
Amplifier Step Response
Start Up Time
tSTR
—
2
—
ms
G = +1, 0.1% VOUT settling (Note 2)
Offset Correction Settling Time
tSTL
—
100
—
µs
G = +1, VIN step of 2V,
VOS within 100 µV of its final value
Output Overdrive Recovery Time
tODR
—
120
—
µs
G = -10, ±0.5V input overdrive to VDD/2,
VIN 50% point to VOUT 90% point (Note 3)
Note 1:
2:
3:
These parameters were characterized using the circuit in Figure 1-6. In Figure 2-36 and Figure 2-37,
there is an IMD tone at DC, a residual tone at 100 Hz and other IMD tones and clock tones.
High gains behave differently; see Section 4.3.3, Offset at Power Up.
tODR includes some uncertainty due to clock edge timing.
TABLE 1-3:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V,
VSS = GND.
Parameters
Sym.
Min.
Typ.
Max.
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5L-SC-70
θJA
—
331
—
°C/W
Thermal Resistance, 5L-SOT-23
θJA
—
256
—
°C/W
Conditions
Temperature Ranges
(Note 1)
Thermal Package Resistances
Note 1:
Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
© 2012 Microchip Technology Inc.
DS25127A-page 5
MCP6V31/1U
1.3
Timing Diagrams
1.4
1.8V to 5.5V
1.8V
VDD 0V
tSTR
1.001(VDD/3)
VOUT
Test Circuits
The circuits used for most DC and AC tests are shown
in Figure 1-4 and Figure 1-5. Lay the bypass capacitors
out as discussed in Section 4.3.10, Supply Bypassing
and Filtering. RN is equal to the parallel combination of
RF and RG to minimize bias current effects.
0.999(VDD/3)
FIGURE 1-1:
Amplifier Start Up.
VDD
1 µF
RN
VIN
RISO
VOUT
MCP6V3X
VIN
tSTL
VOS + 100 µV
RG
VOS
VOS – 100 µV
FIGURE 1-2:
Time.
Offset Correction Settling
100 nF
VDD/3
1 µF
RISO
VOUT
MCP6V3X
tODR
100 nF
VIN
VDD
tODR
VDD/2
VSS
FIGURE 1-3:
VL
FIGURE 1-4:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
VDD/3 RN
VOUT
RL
RF
VDD
VIN
CL
Output Overdrive Recovery.
RG
CL
RL
VL
RF
FIGURE 1-5:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
The circuit in Figure 1-6 tests the input’s dynamic
behavior (i.e., IMD, tSTR, tSTL and tODR). The
potentiometer balances the resistor network (VOUT
should equal VREF at DC). The op amp’s common
mode input voltage is VCM = VIN/2. The error at the
input (VERR) appears at VOUT with a noise gain of
10 V/V.
11.0 kΩ 100 kΩ 500 Ω
0.1%
0.1% 25 turn
VREF = VDD/3
VDD
1 µF
VIN
100 nF
MCP6V3X
11.0 kΩ 100 kΩ 249 Ω
1%
0.1%
0.1%
FIGURE 1-6:
Input Behavior.
DS25127A-page 6
RISO
0Ω
VOUT
CL
20 pF
RL
open
VL
Test Circuit for Dynamic
© 2012 Microchip Technology Inc.
MCP6V31/1U
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
DC Input Precision
15%
10%
5%
4
2
0
-4
-6
FIGURE 2-1:
Input Offset Voltage.
Input O
Offset V
Voltage
e (μV)
25%
20%
15%
10%
5%
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
VCM = VCMH
Representative
p
Part
6
4
2
0
+125°C
+85°C
85 C
+25°C
-40°C
-2
-4
-6
FIGURE 2-2:
Input Offset Voltage Drift.
25%
20%
15%
10%
5%
6.5
6.0
5.5
5.0
4.5
4.0
3.5
8
Representative Part
IInput O
Offset V
Voltage
e (μV)
30%
3.0
Power Supply Voltage (V)
FIGURE 2-5:
Input Offset Voltage vs.
Power Supply Voltage with VCM = VCMH.
42 Samples
VDD = 1.8V and 5.5V
35%
2.5
0.0
50
2.0
-8
-50 -40 -30 -20 -10 0 10 20 30 40
Input Offset Voltage Drift; TC1 (nV/°C)
1.5
Percentage of Occurrences
8
42 Samples
VDD = 1.8V and 5.5V
0%
Percen
ntage of Occurrences
1.0
Power Supply Voltage (V)
FIGURE 2-4:
Input Offset Voltage vs.
Power Supply Voltage with VCM = VCML.
35%
40%
0.5
0.0
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
Input Offset Voltage (μV)
45%
+125°C
+85°C
+85
C
+25°C
-40°C
-2
-8
0%
30%
VCM = VCML
Representative Part
6
1.0
20%
8
42 Samples
TA = +25°C
VDD = 1.8V and 5.5V
Input O
Offset V
Voltage
e (μV)
Percentage of Occurrences
25%
0.5
2.1
6
4
2
VDD = 1.8V
0
VDD = 5.5V
-2
-4
-6
0%
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
Input Offset Voltage's Quadratic Temp Co;
TC2 (nV/°C2)
FIGURE 2-3:
Input Offset Voltage
Quadratic Temp. Co.
© 2012 Microchip Technology Inc.
-8
8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-6:
Output Voltage.
Input Offset Voltage vs.
DS25127A-page 7
MCP6V31/1U
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
50%
VDD = 1.8V
Representative Part
6
Pe
ercenta
age of Occurrrences
s
Input O
Offset V
Voltage
e (μV)
8
4
2
0
-2
+125°C
+85°C
+25°C
+25
C
-40°C
-4
-6
-8
-0.5
30%
25%
20%
15%
10%
5%
FIGURE 2-10:
90%
VDD = 5.5V
Representative Part
6
Pe
ercenta
age of Occurrrences
s
Input O
Offset V
Voltage
e (μV)
35%
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
1/PSRR (μV/V)
4
2
0
-2
+125°C
+85°C
+25
C
+25°C
-40°C
-4
-6
80%
PSRR.
21 Samples
TA = +25°C
70%
60%
VDD = 5.5V
50%
40%
30%
20%
VDD = 1.8V
10%
-8
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
0%
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
1/AOL (μV/V)
Input Common Mode Voltage (V)
FIGURE 2-8:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 5.5V.
FIGURE 2-11:
DC Open-Loop Gain.
160
21 Samples
TA = 25°C
155
150
60%
CMRR, PS
SRR (dB)
Percentage of Occurrences
40%
2.5
8
70%
20 Samples
TA = +25°C
0%
0.0
0.5
1.0
1.5
2.0
Input Common Mode Voltage (V)
FIGURE 2-7:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 1.8V.
80%
45%
50%
VDD = 5.5V
40%
30%
20%
VDD = 1.8V
PSRR
145
140
135
130
125
120
10%
VDD = 5.5V
5 5V
VDD = 1.8V
115
1/CMRR (μV/V)
FIGURE 2-9:
DS25127A-page 8
CMRR.
1.6
1.2
0.8
0.4
0.0
-0.4
-0.8
-1.2
-1.6
0%
CMRR
110
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-12:
CMRR and PSRR vs.
Ambient Temperature.
© 2012 Microchip Technology Inc.
MCP6V31/1U
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
10000
1n
Input Bias
s, Offse
et Currrents (A
A)
160
DC Ope
D
en-Loo
op Gain
n (dB)
155
150
VDD = 5.5V
VDD = 1.8V
145
140
135
130
125
120
115
110
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
IB
10
10p
35
45
55 65 75 85 95 105 115 125
Ambient Temperature (°C)
1.E-02
10m
1.E-03
1.E
03
1m
Input Cu
urrent M
Magnitude (A
A)
Inpu
ut Bias
s, Offse
et Currents (p
pA)
IOS
100
100
100p
FIGURE 2-16:
Input Bias and Offset
Currents vs. Ambient Temperature with
VDD = +5.5V.
TA = +85°C
VDD = 5.5V
150
1000
1n
1
1p
25
125
FIGURE 2-13:
DC Open-Loop Gain vs.
Ambient Temperature.
200
VDD = 5.5V
1.E-04
100μ
100
1.E-05
10μ
50
IB
1.E-06
1μ
0
1.E-07
100n
-50
1.E-08
1
E-08
10n
-100
1.E-09
1n
IOS
-150
1.E-10
100p
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.0
0.5
-200
-0.5
+125°C
+85°C
+85
C
+25°C
-40°C
Common Mode Input Voltage (V)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +85°C.
1.E-11
p
10p
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-17:
Input Bias Current vs. Input
Voltage (below VSS).
Inpu
ut Bias
s, Offse
et Currrents (p
pA)
5000
4000
TA = +125°C
VDD = 5.5V
5 5V
3000
2000
IB
1000
0
IOS
1000
-1000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-2000
Common Mode Input Voltage (V)
FIGURE 2-15:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
© 2012 Microchip Technology Inc.
DS25127A-page 9
MCP6V31/1U
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
Other DC Voltages and Currents
6.5
6.0
5.5
30
VDD – VOH
100
VOL – VSS
VDD = 5.5V
VDD = 1.8V
10
Supply C
Current (μA/amplifier)
25
20
15
+125°C
+85°C
+25°C
-40°C
10
5
5.5
5.0
4.5
4.0
3.5
10
3.0
1
Output Current Magnitude (V)
1.5
0.1
2.5
0
1
2.0
Power Supply Voltage (V)
FIGURE 2-19:
Output Voltage Headroom
vs. Output Current.
FIGURE 2-22:
Supply Voltage.
Supply Current vs. Power
40%
Percenttage off Occurrence
P
es
RL = 25 k
VDD = 5.5V
VOL – VSS
VDD – VOH
VDD = 1.8V
35%
850 Samples
1 Wafer Lot
TA = +25°C
30%
25%
20%
15%
10%
5%
FIGURE 2-20:
Output Voltage Headroom
vs. Ambient Temperature.
DS25127A-page 10
1.30
0
1.28
8
1.26
6
1.24
4
125
1.22
2
100
1.20
0
0
25
50
75
Ambient Temperature (°C)
1.18
8
-25
1.16
6
-50
1.10
0
0%
1.14
4
Ou
utput V
Voltage Headrroom (V
V)
1000
Outpu
ut Headroom (mV)
5.0
Power Supply Voltage (V)
FIGURE 2-21:
Output Short Circuit Current
vs. Power Supply Voltage.
FIGURE 2-18:
Input Common Mode
Voltage Headroom (Range) vs. Ambient
Temperature.
12
11
10
9
8
7
6
5
4
3
2
1
0
-40
125
4.5
0
25
50
75
100
Ambient Temperature (°C)
4.0
-25
3.5
-50
-30
3.0
-0.4
+125°C
+85°C
+25°C
-40°C
-20
2.5
-0.3
0
-10
2.0
Lower (VCML – VSS)
-0.2
10
1.5
00
0.0
-0.1
20
1.0
0.1
-40°C
+25°C
+85°C
+125°C
30
0.5
Upper ( VCMH – VDD)
0.2
40
1.12
2
Inp
put Com
mmon Mode Voltag
ge
Headroo
H
om (V)
1 Wafer Lot
03
0.3
0.0
0.4
Output Sho
ort Circuit Current (mA)
2.2
POR Trip Voltage (V)
FIGURE 2-23:
Voltage.
Power-on Reset Trip
© 2012 Microchip Technology Inc.
MCP6V31/1U
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
1.6
POR
R Trip Voltage (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-24:
Power-on Reset Voltage vs.
Ambient Temperature.
© 2012 Microchip Technology Inc.
DS25127A-page 11
MCP6V31/1U
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
Frequency Response
Gain Band
dwidth Product (kHz)
700
80
70
60
CMRR
40
30
PSRR
70
300
60
200
50
VDD = 1.8V
GBWP
100
40
| AOL |
-10
-270
1M
1.E+06
10k
100k
1.E+04
1.E+05
Frequency (Hz)
50
40
‘AOL
30
-90
-120
20
10
-30
-60
-150
| AOL |
180
-180
0
-210
-10
-240
-20
1k
1.E+03
10k
100k
1.E+04
1.E+05
Frequency (Hz)
-270
1M
1.E+06
FIGURE 2-27:
Open-Loop Gain vs.
Frequency with VDD = 5.5V.
DS25127A-page 12
50
VDD = 1.8V
GBWP
100
40
0
30
Common Mode Input Voltage (V)
700
0
Open
n-Loop Phase (°)
VDD = 5.5V
CL = 20 pF
60
200
FIGURE 2-29:
Gain Bandwidth Product
and Phase Margin vs. Common Mode Input
Voltage.
FIGURE 2-26:
Open-Loop Gain vs.
Frequency with VDD = 1.8V.
70
60
-0.5
-20
1k
1.E+03
-240
300
6.0
-210
70
5.5
0
80
400
5.0
180
-180
500
4.5
-150
10
VDD = 5.5V
4.0
20
90
PM
3.5
-120
600
3.0
30
100
RF = 1 M
2.5
-30
-90
125
700
2.0
‘AOL
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-28:
Gain Bandwidth Product
and Phase Margin vs. Ambient Temperature.
0
-60
-25
1.5
50
30
-50
1.0
VDD = 1.8V
CL = 20 pF
60
40
100k
1.E+05
CMRR and PSRR vs.
70
Open
n-Loop Gain (dB)
80
400
0.5
1k
10k
1.E+03
1.E+04
Frequency (Hz)
Gain Bandwidth Product (kHz)
FIGURE 2-25:
Frequency.
Open
n-Loop Gain (dB)
500
VDD = 5.5V
0
100
1.E+02
Open
n-Loop Phase (°)
10
10
1.E+01
90
PM
hase Margin (°)
Ph
20
600
600
100
VDD = 5.5V
PM
90
500
80
400
70
300
60
200
50
Ph
hase Margin (°)
50
Gain Bandwidth Product (kHz)
CMR
RR, PSRR (dB)
90
100
Ph
hase Margin (°)
110
100
0.0
2.3
GBWP
100
VDD = 1.8V
0
40
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-30:
Gain Bandwidth Product
and Phase Margin vs. Output Voltage.
© 2012 Microchip Technology Inc.
MCP6V31/1U
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
10
VDD = 1.8V
Max
ximum Outputt Voltag
ge Swiing
(VP--P)
Closed-Loo
op Output Impedance
()
1.E+05
100k
1.E+04
10k
1.E+03
1k
1.E+02
100
1.E+01
10
1.E+001
100
1.E+02
G = 1 V/V
G = 11 V/V
G = 101 V/V
1k
1.E+03
100k
10k
1.E+04
1.E+05
Frequency (Hz)
1M
1.E+06
FIGURE 2-31:
Closed-Loop Output
Impedance vs. Frequency with VDD = 1.8V.
Closed-Loo
op Output Impedance
()
1.E+05
100k
VDD = 5.5V
VDD = 1.8V
1
0.1
0
1
1k
1.E+03
10k
100k
1.E+04
1.E+05
Frequency (Hz)
1M
1.E+06
FIGURE 2-33:
Maximum Output Voltage
Swing vs. Frequency.
VDD = 5.5V
1.E+04
10k
1.E+03
1k
1.E+02
100
1.E+01
10
1.E+00
10
100
1.E+02
G = 1 V/V
G = 11 V/V
G = 101 V/V
1k
1.E+03
10k
100k
1.E+04
1.E+05
Frequency (Hz)
1M
1.E+06
FIGURE 2-32:
Closed-Loop Output
Impedance vs. Frequency with VDD = 5.5V.
© 2012 Microchip Technology Inc.
DS25127A-page 13
MCP6V31/1U
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
Input Noise and Distortion
1000
1000
eni
100
100
10
VDD = 5.5V
VDD = 1.8V
10
Eni(0 Hz to f)
1
1
1
10 1.E+02
100 1.E+03
1k 1.E+04
10k 1.E+05
100k
1.E+00
1.E+01
Frequency (Hz)
IMD Sp
pectrum
m, RTI ((μVPK)
Input No
oise Voltage Density;
eni (nV/¥Hz)
1000
Integrated
d Input Noise Voltage;
Eni (μVP-P)
2.4
100
IMD tone at DC
10
100 Hz tone
1
10
1.E+01
Input N
Noise Voltage; eni(t)
(0.2 μV/div)
VDD = 1.8V
50
40
VDD = 5.5V
30
20
100k
1.E+05
10
NPBW = 10 Hz
NPBW = 1 Hz
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
0
0
10
20
30
Common Mode Input Voltage (V)
FIGURE 2-35:
Input Noise Voltage Density
vs. Input Common Mode Voltage.
40 50 60
Time (s)
70
80
90
100
FIGURE 2-38:
Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD = 1.8V.
1.4
GDM = 1 V/V
VCM tone = 50 mVPK, f = 100 Hz
VDD = 5.5V
1.2
Input N
Noise Voltage; eni(t)
(0.2 μV/div)
IMD Sp
pectrum
m, RTI ((μVPK)
10k
1.E+04
VDD = 1.8V
f < 2 kHz
70
1000
100
1k
1.E+02
1.E+03
Frequency (Hz)
FIGURE 2-37:
Inter-Modulation Distortion
vs. Frequency with VDD Disturbance
(see Figure 1-6).
80
In
nput No
oise Vo
oltage D
Density
y
(nV/¥
¥Hz)
VDD = 1.8V
VDD = 5.5V
5 5V
0.1
0
1
1
1.E+00
FIGURE 2-34:
Input Noise Voltage Density
and Integrated Input Noise Voltage vs.
Frequency.
60
GDM = 1 V/V
VDD tone = 50 mVPK, f = 100 Hz
1.0
100
0.8
0.6
0.4
10
residual 100 Hz tone
0.2
0.0
NPBW = 10 Hz
-0.2
1
-0.4
0.1
0
1
1
1.E+00
VDD = 1.8V
VDD = 5.5V
10
1.E+01
100
1k
1.E+02
1.E+03
Frequency (Hz)
-0.6
100k
1.E+05
FIGURE 2-36:
Inter-Modulation Distortion
vs. Frequency with VCM Disturbance (see
Figure 1-6).
DS25127A-page 14
NPBW = 1 Hz
-0.8
10k
1.E+04
0
10
20
30
40 50 60
Time (s)
70
80
90
100
FIGURE 2-39:
Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD = 5.5V.
© 2012 Microchip Technology Inc.
MCP6V31/1U
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
Time Response
80
80
35
60
70
TPCB
30
40
25
20
20
0
VDD = 1.8V
VDD = 5.5V
15
10
20
-20
-40
VOS
5
-60
0
-80
Temperature increased by
using heat gun for 5 seconds.
-5
-120
Input O
Offset Voltage (mV)
30
20
0
0
VDD
4
6
5.5
5
5.0
4
POR Trip Point
3
3
2
2
1
1
0
0
VOS
-1
20
30
-1
70
80
90
100
Non-inverting Small Signal
VDD = 5.5V
G=1
4.0
3.5
3.0
2.5
2.0
1.5
-2
-2
-3
-3
0.5
-4
-4
0.0
1.0
0
FIGURE 2-41:
Input Offset Voltage vs.
Time at Power Up.
40 50 60
Time (μs)
4.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Time (ms)
50
100
FIGURE 2-44:
Step Response.
150 200 250
Time (μs)
300
350
400
Non-inverting Large Signal
90
7
VDD = 5.5V
G=1
VIN
6
VDD = 5.5V
G = -1
80
0
Output V
Voltage (10 mV/div)
Input, O
Output Voltage (V)
10
FIGURE 2-43:
Step Response.
Power Supply Voltage (V)
G=1
5
40
10 20 30 40 50 60 70 80 90 100
Time (s)
FIGURE 2-40:
Input Offset Voltage vs.
Time with Temperature Change.
6
50
Outtput Voltage (V)
0
60
10
-100
-10
VDD = 5.5V
G=1
Output V
Voltage (10 mV/div)
40
PCB T
Tempe
erature (°C)
IInput O
Offset V
Voltage
e (μV)
2.5
-1
-10
70
5
60
VOUT
4
50
3
40
30
2
20
1
10
0
0
1
2
3
4
5
6
Time (ms)
7
8
9
10
FIGURE 2-42:
The MCP6V31/1U Family
Shows No Input Phase Reversal with Overdrive.
© 2012 Microchip Technology Inc.
0
10
20
FIGURE 2-45:
Response.
30
40 50 60
Time (μs)
70
80
90
100
Inverting Small Signal Step
DS25127A-page 15
MCP6V31/1U
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF.
VDD = 5.5V
G = -1
5.0
4.0
Outp
put Voltage (V)
Outtput Voltage (V)
4.5
3.5
3.0
2.5
2.0
1.5
1.0
7
6
6
5
5
VOUT
G VIN
4
4
3
3
2
2
VDD = 5
5.5V
5V
G = -10 V/V
0.5V Overdrive
1
G VIN
0.5
1
VOUT
0
0.0
0
50
100
FIGURE 2-46:
Response.
150 200 250
Time (μs)
300
350
-1
400
Inverting Large Signal Step
0
-1
0 100 200 300 Time
400 500
700 800 900 10001100
(100600
μs/div)
FIGURE 2-48:
Output Overdrive Recovery
vs. Time with G = -10 V/V.
1.E-02
10m
0.30
0.5V Input Overdrive
Overdriv
ve Recovery Time (s)
VDD = 5.5V
0.25
Falling Edge
Sle
ew Rate (V/μs)
7
Input Voltage × G (1 V/div)
5.5
0.20
VDD = 1.8V
1.E-03
1m
0.15
0 10
0.10
tODR, high
VDD = 5.5V
1.E-04
1
E
04
100μ
VDD = 1.8V
0.05
tODR, low
Rising Edge
0.00
1.E-05
10μ
-50
-25
FIGURE 2-47:
Temperature.
DS25127A-page 16
0
25
50
75
Ambient Temperature (°C)
100
Slew Rate vs. Ambient
125
1
10
100
Inverting Gain Magnitude (V/V)
1000
FIGURE 2-49:
Output Overdrive Recovery
Time vs. Inverting Gain.
© 2012 Microchip Technology Inc.
MCP6V31/1U
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
3.1
PIN FUNCTION TABLE
MCP6V31
MCP6V31U
SOT-23
SOT-23, SC-70
1
4
VOUT
2
2
VSS
3
1
VIN+
Non-inverting Input (op amp A)
4
3
VIN–
Inverting Input (op amp A)
5
5
VDD
Positive Power Supply
Symbol
Description
Output (op amp A)
Negative Power Supply
Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
© 2012 Microchip Technology Inc.
DS25127A-page 17
MCP6V31/1U
NOTES:
DS25127A-page 18
© 2012 Microchip Technology Inc.
MCP6V31/1U
4.0
APPLICATIONS
The MCP6V31/1U family of zero-drift op amps is
manufactured using Microchip’s state of the art CMOS
process. It is designed for precision applications with
requirements for small packages and low power. Its low
supply voltage and low quiescent current make the
MCP6V31/1U devices ideal for battery-powered
applications.
4.1
Overview of Zero-Drift Operation
Figure 4-1 shows a simplified diagram of the
MCP6V31/1U zero-drift op amps. This diagram will be
used to explain how slow voltage errors are reduced in
this architecture (much better VOS, ∆VOS/∆TA (TC1),
CMRR, PSRR, AOL and 1/f noise).
The Low-Pass Filter reduces high frequency content,
including harmonics of the Chopping Clock.
The Output Buffer drives external loads at the VOUT pin
(VREF is an internal reference voltage).
The Oscillator runs at fOSC1 = 200 kHz. Its output is
divided by two, to produce the Chopping Clock rate of
fCHOP = 100 kHz.
The internal POR part starts the part in a known good
state, protecting against power supply brown-outs.
The Digital Control block controls switching and POR
events.
4.1.2
CHOPPING ACTION
Figure 4-2 shows the amplifier connections for the first
phase of the Chopping Clock and Figure 4-3 shows
them for the second phase. Its slow voltage errors
alternate in polarity, making the average error small.
VREF
Output
Buffer
VOUT
VIN+
VIN+
VIN–
Main
Amp.
VIN–
NC
Oscillator
Aux.
Amp.
Digital Control
Chopper
Output
Switches
POR
FIGURE 4-1:
Simplified Zero-Drift Op
Amp Functional Diagram.
4.1.1
NC
Low-Pass
Filter
Low-Pass
Filter
Chopper
Input
Switches
Main
Amp.
Aux.
Amp.
FIGURE 4-2:
First Chopping Clock Phase;
Equivalent Amplifier Diagram.
VIN+
VIN–
Main
Amp.
NC
BUILDING BLOCKS
The Main Amplifier is designed for high gain and
bandwidth, with a differential topology. Its main input
pair (+ and - pins at the top left) is used for the higher
frequency portion of the input signal. Its auxiliary input
pair (+ and - pins at the bottom left) is used for the low
frequency portion of the input signal and corrects the
op amp’s input offset voltage. Both inputs are added
together internally.
The Auxiliary Amplifier, Chopper Input Switches and
Chopper Output Switches provide a high DC gain to the
input signal. DC errors are modulated to higher
frequencies, while white noise is modulated to low
frequency.
© 2012 Microchip Technology Inc.
Low-Pass
Filter
Aux.
Amp.
FIGURE 4-3:
Second Chopping Clock
Phase; Equivalent Amplifier Diagram.
DS25127A-page 19
MCP6V31/1U
4.1.3
INTERMODULATION DISTORTION
(IMD)
These op amps will show intermodulation distortion
(IMD) products when an AC signal is present.
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the zero-drift circuitry’s non-linear
response to produce IMD tones at sum and difference
frequencies. Each of the square wave clock’s
harmonics has a series of IMD tones centered on it.
See Figure 2-36 and Figure 2-37.
4.2
4.2.1
Other Functional Blocks
RAIL-TO-RAIL INPUTS
The input stage of the MCP6V31/1U op amps uses two
differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM,
which is approximately equal to VIN+ and VIN– in
normal operation) and the other at high VCM. With this
topology, the input operates with VCM up to VDD + 0.2V,
and down to VSS – 0.15V, at +25°C (see Figure 2-18).
The input offset voltage (VOS) is measured at
VCM = VSS – 0.15V and VDD + 0.2V to ensure proper
operation.
The transition between the input stages occurs when
VCM ≈ VDD – 0.9V (see Figure 2-7 and Figure 2-8). For
the best distortion and gain linearity, with non-inverting
gains, avoid this region of operation.
4.2.1.1
VIN+ Bond
Pad
Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum
Ratings †). This requirement is independent of the current limits discussed later on.
Bond V –
IN
Pad
Input
Stage
VSS Bond
Pad
FIGURE 4-4:
Structures.
Simplified Analog Input ESD
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that well above VDD; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
overvoltage (beyond VDD) events. Very fast ESD
events (that meet the spec) are limited so that damage
does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-5 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diode
connected FETs for low leakage.
Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-42 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.1.2
VDD Bond
Pad
VDD
U1
D1
MCP6V3X
V1
D2
VOUT
V2
FIGURE 4-5:
Protecting the Analog Inputs
Against High Voltages.
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions, and to minimize input bias
current (IB).
DS25127A-page 20
© 2012 Microchip Technology Inc.
MCP6V31/1U
4.2.1.3
Input Current Limits
4.3
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1, Absolute Maximum
Ratings †). This requirement is independent of the voltage limits discussed previously.
Figure 4-6 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
The diode currents will dump onto VDD.
V1
V2
R1
MCP6V3X
Table 1-1 gives both the linear and quadratic
temperature coefficients (TC1 and TC2) of input offset
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:
EQUATION 4-1:
=
TA – 25°C
VOS(TA)
=
input offset voltage at TA
VOS
=
input offset voltage at +25°C
TC1
=
linear temperature coefficient
TC2
=
quadratic temperature coefficient
R2
VSS – min(V1, V2)
2 mA
max(V1, V2) – VDD
min(R1, R2) >
2 mA
FIGURE 4-6:
Protecting the Analog Inputs
Against High Currents.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-17.
RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V31/1U zero-drift
op amps is VDD – 20 mV (minimum) and VSS + 20 mV
(maximum) when RL = 10 kΩ is connected to VDD/2
and VDD = 5.5V. Refer to Figure 2-19 and Figure 2-20
for more information.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
© 2012 Microchip Technology Inc.
2
∆T
VOUT
min(R1, R2) >
4.2.2
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Where:
U1
D2
4.3.1
V OS ( T A ) = VOS + TC 1 Δ T + TC2 Δ T
VDD
D1
Application Tips
4.3.2
DC GAIN PLOTS
Figures 2-9 to 2-11 are histograms of the reciprocals
(in units of µV/V) of CMRR, PSRR and AOL,
respectively. They represent the change in input offset
voltage (VOS) with a change in common mode input
voltage (VCM), power supply voltage (VDD) and output
voltage (VOUT).
The 1/AOL histogram is centered near 0 µV/V because
the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise and tester limitations, not unstable behavior.
Production tests make multiple VOS measurements,
which validates an op amp's stability; an unstable part
would show greater VOS variability, or the output would
stick at one of the supply rails.
4.3.3
OFFSET AT POWER UP
When these parts power up, the input offset (VOS)
starts at its uncorrected value (usually less than
±5 mV). Circuits with high DC gain can cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (like tODR), in addition to the startup time (like
tSTR).
It can be simple to avoid this extra startup time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (RF) is another method.
DS25127A-page 21
MCP6V31/1U
SOURCE RESISTANCES
The input bias currents have two significant
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10 Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
Small input resistances may be needed for high gains.
Without them, parasitic capacitances might cause
positive feedback and instability.
4.3.5
GN is the circuit’s noise gain. For non-inverting gains,
GN and the Signal Gain are equal. For inverting gains,
GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
1.E+04
10k
RL||(RF + RG) 100 k
1.E+03
1k
1.E+02
100
10p
1.E-11
SOURCE CAPACITANCE
The capacitances seen by the two inputs should be
small and matched. The internal switches connected to
the inputs dump charges on these capacitors; an offset
can be created if the capacitances do not match. Large
input capacitances and source resistances, together
with high gain, can lead to positive feedback and
instability.
4.3.6
Figure 4-8 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
load capacitance (CL). The y-axis is the resistance
(RISO).
Recom
mmended RISO ()
4.3.4
CAPACITIVE LOADS
When driving a capacitive load with these op amps, a
series resistor at the output (RISO in Figure 4-7)
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
GN = 100
1n
10n
100n
1.E-09
1.E-08
1.E-07
Capacitive Load (F)
1μ
1.E-06
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation is helpful.
STABILIZING OUTPUT LOADS
This family of zero-drift op amps has an output
impedance (Figure 2-31 and Figure 2-32) that has a
double zero when the gain is low. This can cause a
large phase shift in feedback networks that have low
impedance near the part’s bandwidth. This large phase
shift can cause stability problems.
Figure 4-9 shows that the load on the output is
(RL + RISO)||(RF + RG), where RISO is before the load
(like Figure 4-7). This load needs to be large enough to
maintain performance; it should be at least 10 kΩ.
RG
RF
VOUT
RL
RISO
CL
U1
VOUT
CL
GN = 10
100p
1.E-10
FIGURE 4-8:
Recommended RISO values
for Capacitive Loads.
4.3.7
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These zero-drift op amps have a different
output impedance than most op amps, due to their
unique topology.
GN = 1
MCP6V3X
FIGURE 4-9:
Output Load.
U1
MCP6V3X
FIGURE 4-7:
Output Resistor, RISO,
Stabilizes Capacitive Loads.
DS25127A-page 22
© 2012 Microchip Technology Inc.
MCP6V31/1U
4.3.8
GAIN PEAKING
4.3.9
Figure 4-10 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG represent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel. The capacitance CFP represents the
parasitic capacitance coupling the output and noninverting input pins.
RN
VP
CN
CFP
Reduce undesired noise and signals with:
• Low bandwidth signal filters:
- Minimizes random analog noise
- Reduces interfering signals
• Good PCB layout techniques:
- Minimizes crosstalk
- Minimizes parasitic capacitances and
inductances that interact with fast switching
edges
• Good power supply design:
- Isolation from other parts
- Filtering of interference on supply line(s)
4.3.10
U1
MCP6V3X
VM
RG
FIGURE 4-10:
Capacitance.
CG
RF
VOUT
Amplifier with Parasitic
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF||RG.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2πRNCN).
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.3.6, Capacitive
Loads), CG and the open-loop gain’s phase shift. An
approximate limit for RF is:
EQUATION 4-2:
2
12 pF
R F ≤ ( 10 k Ω ) × -------------- × G N
CG
Some applications may modify these values to reduce
either output loading or gain peaking (step response
overshoot).
At high gains, RN needs to be small, in order to prevent
positive feedback and oscillations. Large CN values
can also help.
© 2012 Microchip Technology Inc.
REDUCING UNDESIRED NOISE
AND SIGNALS
SUPPLY BYPASSING AND
FILTERING
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
of the pin for good high-frequency performance.
These parts also need a bulk capacitor (i.e., 1 µF or
larger) within 100 mm to provide large, slow currents.
This bulk capacitor can be shared with other low noise,
analog parts.
In some cases, high-frequency power supply noise
(e.g., switched mode power supplies) may cause
undue intermodulation distortion, with a DC offset shift;
this noise needs to be filtered. Adding a resistor into the
supply connection can be helpful.
4.3.11
PCB DESIGN FOR DC PRECISION
In order to achieve DC precision on the order of ±1 µV,
many physical errors need to be minimized. The design
of the Printed Circuit Board (PCB), the wiring, and the
thermal environment have a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6V31/1U op
amps’ minimum and maximum specifications.
4.3.11.1
PCB Layout
Any time two dissimilar metals are joined together, a
temperature dependent voltage appears across the
junction (the Seebeck or thermojunction effect). This
effect is used in thermocouples to measure
temperature. The following are examples of
thermojunctions on a PCB:
• Components (resistors, op amps, …) soldered to
a copper pad
• Wires mechanically attached to the PCB
• Jumpers
• Solder joints
• PCB vias
DS25127A-page 23
MCP6V31/1U
Typical thermojunctions have temperature to voltage
conversion coefficients of 1 to 100 µV/°C (sometimes
higher).
4.4
Microchip’s AN1258 (“Op Amp Precision Design: PCB
Layout Techniques”) contains in-depth information on
PCB layout techniques that minimize thermojunction
effects. It also discusses other effects, such as
crosstalk, impedances, mechanical stresses and
humidity.
Many sensors are configured as Wheatstone bridges.
Strain gauges and pressure sensors are two common
examples. These signals can be small and the
common mode noise large. Amplifier designs with high
differential gain are desirable.
4.3.11.2
Crosstalk
DC crosstalk causes offsets that appear as a larger
input offset voltage. Common causes include:
Typical Applications
4.4.1
WHEATSTONE BRIDGE
Figure 4-11 shows how to interface to a Wheatstone
bridge with a minimum of components. Because the
circuit is not symmetric, the ADC input is single ended,
and there is a minimum of filtering, the CMRR is good
enough for moderate common mode noise.
• Common mode noise (remote sensors)
• Ground loops (current return paths)
• Power supply coupling
Interference from the mains (usually 50 Hz or 60 Hz),
and other AC sources, can also affect the DC
performance. Non-linear distortion can convert these
signals to multiple tones, including a DC shift in voltage.
When the signal is sampled by an ADC, these AC
signals can also be aliased to DC, causing an apparent
shift in offset.
To reduce interference:
-
Keep traces and wires as short as possible
Use shielding
Use ground plane (at least a star ground)
Place the input signal source near to the DUT
Use good PCB layout techniques
Use a separate power supply filter (bypass
capacitors) for these zero-drift op amps
4.3.11.3
Miscellaneous Effects
Keep the resistances seen by the input pins as small
and as near to equal as possible, to minimize biascurrent-related offsets.
Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching
glitch-induced offset voltages.
Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
conductor (the triboelectric effect). Make sure the
bending radius is large enough to keep the conductors
and insulation in full contact.
Mechanical stresses can make some capacitor types
(such as some ceramics) to output small voltages. Use
more appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration.
Humidity can cause electrochemical potential voltages
to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.
DS25127A-page 24
0.01C
VDD
R R
0.2R
R R
1 kΩ
100R
VDD
ADC
U1
0.2R
MCP6V31
FIGURE 4-11:
4.4.2
Simple Design.
RTD SENSOR
The ratiometric circuit in Figure 4-12 conditions a twowire RTD, for applications with a limited temperature
range. U1 acts a difference amplifier, with a low
frequency pole. The sensor’s wiring resistance (RW) is
corrected in firmware. Failure (open) of the RTD is
detected by an out-of-range voltage.
VDD
RT
RN
34.8 kΩ 10.0 kΩ
10 nF
RF
2.00 MΩ
RW
RRTD
100Ω
RW
U1
MCP6V31
RG
RF
10.0 kΩ 2.00 MΩ
1.00 kΩ
100 nF
RB
4.99 kΩ
1.0 µF
10 nF
VDD
ADC
FIGURE 4-12:
RTD Sensor.
© 2012 Microchip Technology Inc.
MCP6V31/1U
4.4.3
OFFSET VOLTAGE CORRECTION
Figure 4-13 shows MCP6V31 (U2) correcting the input
offset voltage of another op amp (U1). R2 and C2
integrate the offset error seen at U1’s input; the
integration needs to be slow enough to be stable (with
the feedback provided by R1 and R3). R4 and R5
attenuate the integrator’s output; this shifts the
integrator pole down in frequency.
R1
VIN
R3
R2
VOUT
R4
C2
U1
R5
R2
VDD/2
MCP6XXX
U2
VDD/2
MCP6V31
FIGURE 4-13:
4.4.4
Offset Correction.
PRECISION COMPARATOR
Use high gain before a comparator to improve the
latter’s performance. Do not use MCP6V31/1U as a
comparator by itself; the VOS correction circuitry does
not operate properly without a feedback loop.
U1
VIN
MCP6V31
R1
R2
R3
R4
R5
VOUT
VDD/2
U2
MCP6541
FIGURE 4-14:
Precision Comparator.
© 2012 Microchip Technology Inc.
DS25127A-page 25
MCP6V31/1U
NOTES:
DS25127A-page 26
© 2012 Microchip Technology Inc.
MCP6V31/1U
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6V31/1U family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6V31/1U
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab® design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site
at www.microchip.com/maps, MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for Data Sheets, Purchase and Sampling of
Microchip parts.
5.4
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to
help customers achieve faster time to market. For a
complete listing of these boards and their corresponding user’s guides and technical information, visit the
Microchip web site at www.microchip.com/analog
tools.
Some boards that are especially useful are:
• MCP6V01 Thermocouple Auto-Zeroed Reference
Design (P/N MCP6V01RD-TCPL)
• MCP6XXX Amplifier Evaluation Board 1 (P/N
DS51667)
• MCP6XXX Amplifier Evaluation Board 2 (P/N
DS51668)
• MCP6XXX Amplifier Evaluation Board 3 (P/N
DS51673)
• MCP6XXX Amplifier Evaluation Board 4 (P/N
DS51681)
• Active Filter Demo Board Kit (P/N DS51614)
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board
(P/N SOIC8EV)
• 14-Pin SOIC/TSSOP/DIP Evaluation Board (P/N
SOIC14EV)
5.5
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
AN1228: “Op Amp Precision Design: Random Noise”,
DS01228
AN1258: “Op Amp Precision Design: PCB Layout
Techniques”, DS01258
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
© 2012 Microchip Technology Inc.
DS25127A-page 27
MCP6V31/1U
NOTES:
DS25127A-page 28
© 2012 Microchip Technology Inc.
MCP6V31/1U
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
5-Lead SC70 (MCP6V31U)
Device
MCP6V31UT-E/LT
Note:
Code
Applies to 5-Lead SC-70.
Example:
5-Lead SOT-23 (MCP6V31, MCP6V31U)
Device
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Code
MCP6V31T-E/OT
2BNN
MCP6V31UT-E/OT
2ENN
Note:
DK25
DKNN
2B25
Applies to 5-Lead SOT-23.
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2012 Microchip Technology Inc.
DS25127A-page 29
MCP6V31/1U
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DS25127A-page 30
© 2012 Microchip Technology Inc.
MCP6V31/1U
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© 2012 Microchip Technology Inc.
DS25127A-page 31
MCP6V31/1U
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DS25127A-page 32
© 2012 Microchip Technology Inc.
MCP6V31/1U
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2012 Microchip Technology Inc.
DS25127A-page 33
MCP6V31/1U
NOTES:
DS25127A-page 34
© 2012 Microchip Technology Inc.
MCP6V31/1U
APPENDIX A:
REVISION HISTORY
Revision A (March 2012)
• Original Release of this Document.
© 2012 Microchip Technology Inc.
DS25127A-page 35
MCP6V31/1U
NOTES:
DS25127A-page 36
© 2012 Microchip Technology Inc.
MCP6V31/1U
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
T
–X
Device Tape and Reel Temperature
Range
Device:
/XX
Package
MCP6V31T
Single Op Amp (Tape and Reel) (SOT-23)
MCP6V31UT Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
Temperature Range:
E
Package:
LT = Plastic Package (SC-70), 5-lead
OT = Plastic Small Outline Transistor (SOT-23), 5-lead
Examples:
a)
MCP6V31T-E/OT:
a)
MCP6V31UT-E/LT:
b)
Tape and Reel,
Extended temperature,
5LD SOT-23 package
Tape and Reel
Extended temperature,
5LD SC70 package
MCP6V31UT-E/OT: Tape and Reel,
Extended temperature,
5LD SOT-23 package
= -40°C to +125°C
© 2012 Microchip Technology Inc.
DS25127A-page 37
MCP6V31/1U
NOTES:
DS25127A-page 38
© 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-162076-154-0
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
© 2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS25127A-page 39
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS25127A-page 40
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
11/29/11
© 2012 Microchip Technology Inc.