CY25701JXC/FJXC Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO) and No-Spread Spectrum (XO) Option Features Benefits • Crystal Oscillator with Spread Spectrum Clock (SSXO) • No-Spread Spectrum (XO) Option • Wide operating output clock frequency range of 10–166 MHz • Programmable spread spectrum with nominal 31.5-kHz modulation frequency • Provides wide range of spread percentages for maximum electromagnetic interference (EMI) reduction, to meet regulatory agency electromagnetic compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market. • Center spread: ±0.25% to ±2.0% • This versatile programming feature enables the users to switch between SSXO (with Spread) and XO (without Spread) functions with ease. • Down spread: –0.5% to –4.0% • Internal PLL to generate up to 166-MHz output. • No spread: ± 0.0% • Suitable for most PC, consumer, and networking applications • Integrated phase-locked loop (PLL) • 85 ps typical cycle-to-cycle Jitter with SSCLK = 133MHz • 3.3V operation • Application compatibility in standard and low-power systems • In-house programming of samples and prototype quantities is available using the CY3672 programming kit and CY3613 (JEC package) socket adapters. Production quantities are available through Cypress’ value-added distribution partners or by using third-party programmers from BP Microsystems, HiLo Systems, and others. • Output Enable function • Package available in 4-pin Plastic JE • Pb-free package Pin Configuration Logic Block Diagram CY25701JXC/FJXC 4-pin Plastic JE RFB PLL with MODULATION CONTROL 1 OE 2 VSS VDD 4 C XIN PROGRAMMABLE CONFIGURATION C XOUT OUTPUT DIVIDERS and MUX 3 SSCLK 3 SSCLK 1 OE 4 2 VDD VSS Cypress Semiconductor Corporation Document #: 38-07684 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 27, 2006 [+] Feedback CY25701JXC/FJXC Pin Definition Pin Name Description 1 OE Output Enable pin: Active HIGH. If OE = 1, SSCLK is enabled. 2 VSS Power supply ground. 3 SSCLK Spread spectrum clock output (with or without spread). 4 VDD 3.3V power supply. Functional Description Programming Description The CY25701JXC/FJXC is a Spread Spectrum Crystal Oscillator (SSXO) IC used for the purpose of reducing EMI found in today’s high-speed digital electronic systems. Field/Factory-Programmable CY25701JXC/FJXC The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the embedded input crystal. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency (EMC) requirements and improve time-to-market without degrading system performance. The CY25701JXC/FJXC uses a programmable configuration memory array to synthesize output frequency and spread%. The spread% is programmed to either center spread or down spread with various spread percentages. The range for center spread is from ±0.25% to ±2.00%. The range for down spread is from –0.5% to –4.0%. Contact the factory for smaller or larger spread% amounts if required. Refer to Table 2 for spread selection and no-spread values. The frequency modulated SSCLK output can be programmed from 10–166 MHz. The CY25701JXC/FJXC is available in a 4-pin plastic package with operating temperature range of –20 to 70°C. Field/Factory programming is available for samples and manufacturing by Cypress and its distributors. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample requests and production orders. Additional information on the CY25701JXC/FJXC can be obtained from the Cypress web site at www.cypress.com. Output Frequency, SSCLK Output (SSCLK, pin 3) The modulated frequency at the SSCLK output is produced by synthesizing from the embedded crystal oscillator frequency input. The range of synthesized clock is from 10–166 MHz. Spread Percentage (SSCLK, pin 3) The SSCLK spread can be programmed to various spread percentage values from ±0.25% to ±2.0% for Center Spread and from –0.5% to –4.0% for Down Spread. Refer to Table 2 for available spread options. Enter ±0.0% (No spread) for XO (Crystal Oscillator) without spread option. Frequency Modulation (SSCLK, pin 3) The frequency modulation is programmed at 31.5 kHz for all SSCLK frequencies from 10 to 166 MHz. Contact the factory if a higher-modulation frequency is required. Table 1. Programming Data Requirement Pin Function Output Frequency Spread Percent Code[1] Frequency Modulation Pin Name SSCLK SSCLK SSCLK Pin# 3 3 3 Units MHz % kHz Program Value ENTER DATA ENTER DATA 31.5 Table 2. Spread Percent Selection Center Spread Down Spread Code A B C D E F Z Percentage ±0.25% ±0.5% ±0.75% ±1.0% ±1.5% ±2.0% ±0.0% Code G H J K L M Z Percentage –0.5% –1.0% –1.5% –2.0% –3.0% –4.0% ±0.0% Note: 1. ±0.0% or Code “Z” for XO (No-Spread) option. Document #: 38-07684 Rev. *E Page 2 of 7 [+] Feedback CY25701JXC/FJXC Absolute Maximum Rating Storage Temperature (Non-condensing) .... –55°C to +100°C Supply Voltage (VDD) .................................... –0.5V to +7.0V DC Input Voltage....................................–0.5V to VDD + 0.5V Junction Temperature ................................ –40°C to +125°C Data Retention @ Tj = 125°C................................> 10 years Package Power Dissipation...................................... 350 mW Operating Conditions Min. Typ. Max. Unit VDD Parameter Supply Voltage Description 3.00 3.30 3.60 V TA Ambient Temperature –20 – 70 °C CLOAD Max. Load Capacitance @ pin 3 – – 15 pF FSSCLK SSCLK output frequency, CLOAD = 15 pF 10 – 166 MHz FMOD Spread Spectrum Modulation Frequency 30.0 31.5 33.0 kHz TPU Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic) 0.05 – 500 ms Min. Typ. Max. Unit DC Electrical Characteristics Parameter Description Condition IOH Output High Current (pin 3) VOH = VDD – 0.5, VDD = 3.3V (source) 10 12 – mA IOL Output Low Current (pin 3) VOL = 0.5, VDD= 3.3V (sink) 10 12 – mA VIH Input High Voltage (pin 1) CMOS levels, 70% of VDD 0.7VDD – VDD V VIL Input Low Voltage (pin 1) CMOS levels, 30% of VDD VSS – 0.3VDD V IIH Input High Current (pin 1) Vin = VDD – – 10 µA IIL Input Low Current (pin 1) Vin = VSS – – 10 µA IOZ Output Leakage Current (pin 3) Three-state output, OE = 0 –10 – 10 µA CIN[2] Input Capacitance (pin 1) Pin 1, or OE – 5 7 pF IVDD Supply Current VDD = 3.3V, SSCLK = 10 to 166 MHz, CLOAD = 0, OE = VDD – – 50 mA ∆f Aging TA = 25°C, First year –5 – 5 ppm Min. Typ. Max. Unit AC Electrical Characteristics[2] Parameter Description Condition DC Output Duty Cycle SSCLK, Measured at VDD/2 45 50 55 % tR Output Rise Time 20%–80% of VDD, CL = 15 pF – – 2.7 ns tF Output Fall Time 20%–80% of VDD, CL = 15 pF – – 2.7 ns TCCJ1[3] Cycle-to-Cycle Jitter SSCLK (Pin 3) SSCLK ≥133 MHz, Measured at VDD/2 – 85 200 ps 25 MHz ≤ SSCLK <133 MHz, Measured at VDD/2 – 215 400 ps SSCLK < 25 MHz, Measured at VDD/2 – – 1% of 1/SSCK s TOE1 Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped outputs (Asynchronous) – 150 350 ns TOE2 Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) – 150 350 ns TLOCK PLL Lock Time – – 10 ms Time for SSCLK to reach valid frequency Notes: 2. Guaranteed by characterization, not 100% tested. 3. Jitter is configuration dependent. Actual jitter is dependent on output frequencies, spread percentage, temperature, and output load. For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html, or contact your local Cypress Field Application Engineer. Document #: 38-07684 Rev. *E Page 3 of 7 [+] Feedback CY25701JXC/FJXC Application Circuit 0.1 µF Power 4 3 VDD SSCLK CY25701 OE 1 VSS 2 VDD Figure 1. Application Circuit Diagram Switching Waveforms Duty Cycle Timing (DC = t1A/t1B) t1A SSCLK t1B Figure 2. Duty Cycle Waveform Output Rise/Fall Time VDD SSCLK 0V Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values. Figure 3. Output Rise/Fall Time Waveform Output Enable/Disable Timing OUTPUT ENABLE VDD 0V VIH VIL TOE2 High Impedance SSCLK (Asynchronous) TOE1 Figure 4. Output Enable/Disable Timing Waveforms Document #: 38-07684 Rev. *E Page 4 of 7 [+] Feedback CY25701JXC/FJXC Informational Graphs [4] 172.5 161.5 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 160.5 162.5 171.5 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4% 170.5 169.5 168.5 167.5 166.5 Fnominal 165.5 164.5 163.5 162.5 159.5 0 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1% Fnominal 0 20 68.5 40 60 80 100 120 Time (us) 140 160 180 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4% 68 20 40 60 80 200 67.5 100 120 Time (us) 140 160 180 200 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% 67 67.5 67 66.5 66.5 Fnominal 66 Fnominal 66 65.5 65.5 65 64.5 65 64 64.5 63.5 0 20 40 60 80 100 120 Time (us) 140 160 180 200 0 20 40 60 80 100 120 Time (us) 140 160 180 200 Ordering Information Part Number[5,6] Package description Product Flow Lead-free (Pb-free) CY25701JXC–ZZZ 4-Lead Plastic JE SMD Commercial, –20° to 70°C CY25701JXC–ZZZT 4-Lead Plastic JE SMD - Tape and Reel Commercial, –20° to 70°C CY25701FJXC 4-Lead Plastic JE SMD Commercial, –20° to 70°C CY25701FJXCT 4-Lead Plastic JE SMD - Tape and Reel Commercial, –20° to 70°C Notes: 4. The “Informational Graphs” are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on pages 4 and 5 for device specifications. 5. “ZZZ” denotes the assigned product dash number. This number will be assigned by factory after the output frequency and spread percent programming data is received from the customer. 6. “FJXC” suffix is used for products programmed in field by Cypress distributors. Document #: 38-07684 Rev. *E Page 5 of 7 [+] Feedback CY25701JXC/FJXC Package Drawings and Dimensions 4-Lead (10.2x5.6mm) JEC JE04A 10.2±0.3 (10.5 MAX) 4 1.0±0.2 (1.0) 3.6 5.0 5.6±0.2 (5.8 MAX) 1.0±0.2 (1.0) 1 1.3 2.1 2.4 +0.2 -0.1 2.5 (2.7 MAX) 4.6 0.1 0.15±0.1 (0.05 MIN) 0.51 5.08±0.1 DIMENSIONS IN MILLIMETERS REFERENCE JEDEC: N/A PKG. WEIGHT: 0.24 gms 5.08 RECOMMENDED SOLDERING PATTERN 51-85204-*A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07684 Rev. *E Page 6 of 7 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY25701JXC/FJXC Document History Page Document Title: CY25701JXC/FJXC Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO) and No-Spread Spectrum (XO) Option Document Number: 38-07684 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 224108 See ECN RGL New data sheet *A 258974 See ECN RGL Corrected the product suffix (lead-free) in the ordering information table Added note 4 *B 279379 See ECN RGL Added ordering part numbers *C 392505 See ECN RGL Added 4pin LCC SMD package *D 414085 See ECN RGL Added Spread OFF (XO) programming function Edited CY3724 socket adapter *E 436961 See ECN RGL Changed the Marketing part number from CY25701 to CY25701JXC/FJXC Removed all Ceramic Package references Document #: 38-07684 Rev. *E Page 7 of 7 [+] Feedback