Features • Fast Read Access Time - 120 ns • Automatic Page Write Operation • • • • • • • • – Internal Address and Data Latches for 128-Bytes – Internal Control Timer Fast Write Cycle Time – Page Write Cycle Time - 10 ms Maximum – 1 to 128-Byte Page Write Operation Low Power Dissipation – 80 mA Active Current – 300 µA CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology – Endurance: 104 or 105 Cycles – Data Retention: 10 Years Single 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout AT28C010 Mil 1-Megabit (128K x 8) Paged Parallel EEPROMs AT28C010 Military (continued) Pin Configuration 32 LCC Top View Function A0 - A16 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect CERDIP, FLATPACK Top View A12 A7 A6 A5 NC NC NC A4 A3 A2 A1 7 8 9 10 11 12 13 14 15 16 17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 A15 A16 NC NC NC NC VCC WE NC NC A14 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 6 5 4 3 2 1 44 43 42 41 40 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A0 I/O0 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 I/O6 I/O7 NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 44 LCC Top View 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 4 3 2 1 32 31 30 A12 A15 A16 NC VCC WE NC Pin Name A13 A8 A9 A11 NC NC NC NC OE A10 CE PGA Top View 0010D–PEEPR–7/09 Description The AT28C010 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its one megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 300 μA. The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128bytes simultaneously. During a write cycle, the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel's 28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 128-bytes of EEPROM for device identification or tracking. Block Diagram Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V 2 AT28C010 Military 0010D–PEEPR–7/09 AT28C010 Military Device Operation READ: The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28C010 allows 1 to 128-bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 additional bytes. Each successive byte must be written within 150 μs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28C010 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same. The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28C010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28C010 in the following ways: (a) VCC sense - if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay - once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C010. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after tWC the entire AT28C010 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C010. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP. 3 0010D–PEEPR–7/09 Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C010 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. DEVICE IDENTIFICATION: An extra 128-bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the regular memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software code. Please see Software Chip Erase application note for details. DC and AC Operating Range AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25 -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% Mode CE OE WE I/O Read VIL VIL VIH DOUT Write (2) VIL VIH VIL DIN X High Z Operating Temperature (Case) Mil. VCC Power Supply Operating Modes Standby/Write Inhibit (1) VIH X Write Inhibit X X VIH Write Inhibit X VIL X VIH X Output Disable Notes: X 1. X can be VIL or VIH. High Z 2. Refer to AC Programming Waveforms DC Characteristics Symbol Parameter Condition ILI Input Load Current ILO Max Units VIN = 0V to VCC + 1V 10 μA Output Leakage Current VI/O = 0V to VCC 10 μA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V 300 μA ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 80 mA VIL Input Low Voltage 0.8 V 4 Min AT28C010 Military 0010D–PEEPR–7/09 AT28C010 Military DC Characteristics (Continued) Symbol Parameter Condition Min Max Units VIH Input High Voltage VOL Output Low Voltage IOL = 2.1 mA VOH1 Output High Voltage IOH = -400 μA 2.4 V VOH2 Output High Voltage CMOS IOH = -100 μA; VCC = 4.5V 4,2 V 2.0 V 0.45 V AC Read Characteristics Symbol Parameter tACC AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25 Min Min Min Min Max Max Max Max Units Address to Output Delay 120 150 200 250 ns tCE (1) CE to Output Delay 120 150 200 250 ns tOE (2) OE to Output Delay 0 50 0 55 0 55 0 55 ns tDF (3, 4) CE or OE to Output Float 0 50 0 55 0 55 0 55 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 0 0 0 ns tCEPH(5) CE Pulse High Time 50 50 50 50 ns AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact in tACC. 3. tDF is specified from OE or CE wichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 5. If CE is de-asserted, it must remain de-asserted for at least 50ns during read operations otherwise incorrect data may be read. 5 0010D–PEEPR–7/09 Input Test Waveforms and Measurement Level Output Test Load Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 4 10 pF VIN = 0V COUT 8 Note: 12 pF 1. This parameter is 100% characterized and is not 100% tested. VOUT = 0V AC Write Characteristics Symbol Parameter tWC Write Cycle Time tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 100 ns tBLC Byte Load Cycle Time tWPH Write Pulse Width High 6 Min Max Units 10 ms 150 50 μs ns AT28C010 Military 0010D–PEEPR–7/09 AT28C010 Military AC Write Waveforms WE Controlled CE Controlled Page Mode Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 100 ns tDS Data Set-up Time 50 ns tDH, tOEH Data, OE Hold Time 0 ns 7 0010D–PEEPR–7/09 Page Mode Write Waveforms (1)(2) Notes: 8 1. A7 through A16 must specify the page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. AT28C010 Military 0010D–PEEPR–7/09 AT28C010 Military Chip Erase Waveforms min.) sec (min.) 0.5V Software Data Protection Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS Notes: ENTER DATA PROTECT STATE 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data if loaded. 4. 1 to 128 bytes of data are loaded. 9 0010D–PEEPR–7/09 Software Data Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT STATE(3) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS Software Protected Program Cycle Waveform(1)(2)(3) Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16) must be the same for each high to low transition of WE (or CE). 3. OE must be high only when WE and CE are both low. 10 AT28C010 Military 0010D–PEEPR–7/09 AT28C010 Military Data Polling Characterstics(1) Symbol Parameter Min Typ Max Units tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay (2) tWR Write Recovery Time Notes: ns 0 1. These parameters are characterized and not 100% tested. ns 2. See AC Read Characteristics. Data Polling Waveforms Toggle Bit Characteristics(1) Symbol Parameter Min tDH Data Hold Time tOEH OE Hold Time Typ OE to Output Delay tOEHP OE High Pulse tWR Write Recovery Time Notes: Units 10 ns 10 ns (2) tOE Max ns 150 0 1. These parameters are characterized and not 100% tested. ns ns 2. See AC Read Characteristics. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any addres location may be used but the address should not vary. 11 0010D–PEEPR–7/09 AT28C010 Ordering Information(1) ICC (mA) tACC (ns) Active Standby 120 80 150 Ordering Code Package 0.3 AT28C010(E)-12DM/883 AT28C010(E)-12EM/883 AT28C010-12FM/883 AT28C010(E)-12LM/883 AT28C010(E)-12UM/883 32D6 32L 32F 44L 30U Military/883C Class B, Fully Compliant (-55°C to 125°C) 80 0.3 AT28C010(E)-15DM/883 AT28C010(E)-15EM/883 AT28C010-15FM/883 AT28C010(E)-15LM/883 AT28C010(E)-15UM/883 32D6 32L 32F 44L 30U Military/883C Class B, Fully Compliant (-55°C to 125°C) 200 80 0.3 AT28C010(E)-20DM/883 AT28C010(E)-20EM/883 AT28C010-20FM/883 AT28C010(E)-20LM/883 AT28C010(E)-20UM/883 32D6 32L 32F 44L 30U Military/883C Class B, Fully Compliant (-55°C to 125°C) 250 80 0.3 AT28C010(E)-25DM/883 AT28C010(E)-25EM/883 AT28C010-25FM/883 AT28C010(E)-25LM/883 AT28C010(E)-25UM/883 32D6 32L 32F 44L 30U Military/883C Class B, Fully Compliant (-55°C to 125°C) Note: Operation Range 1. See Valid Part Number table below. Package Type 32D6 32-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (Cerdip) 32F 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32L 32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 44L 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 30U 30-Pin, Ceramic Pin Grid Array (PGA) W Die Options Blank E 12 Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms High Endurance Option: Endurance = 100K Write Cycles AT28C010 Military 0010D–PEEPR–7/09 AT28C010 Military 5962-38267 Ordering Information(1) ICC (mA) tACC (ns) Active Standby 120 80 150 Ordering Code Package 0.3 5962-38267 07 MXX 5962-38267 07 MZX 5962-38267 07 MYX 5962-38267 07 MTX 32D6 32F 44L 30U Military/883C Class B, Fully Compliant (-55°C to 125°C) 80 0.3 5962-38267 05 MXX 5962-38267 05 MUX 5962-38267 05 MZX 5962-38267 05 MYX 5962-38267 05 MTX 32D6 32L 32F 44L 30U Military/883C Class B, Fully Compliant (-55°C to 125°C) 200 80 0.3 5962-38267 03 MXX 5962-38267 03 MUX 5962-38267 03 MZX 5962-38267 03 MYX 5962-38267 03 MTX 32D6 32L 32F 44L 30U Military/883C Class B, Fully Compliant (-55°C to 125°C) 250 80 0.3 5962-38267 01 MXX 5962-38267 01 MUX 5962-38267 01 MZX 5962-38267 01 MYX 5962-38267 01 MTX 32D6 32L 32F 44L 30U Military/883C Class B, Fully Compliant (-55°C to 125°C) Note: Operation Range 1. See Valid Part Number table below. Package Type 32D6 32-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (Cerdip) 32F 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32L 32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 44L 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 30U 30-Pin, Ceramic Pin Grid Array (PGA) W Die Options Blank E Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms High Endurance Option: Endurance = 100K Write Cycles Valid Part Numbers 0010D–PEEPR–7/09 13 Packaging Information 32D6, 32-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual inline Package (Cerdip) Dimensions in Inches and (Millimeters) 32F, 32-Lead, Non-Windowed, Ceramic Bottom Brazed Flat Package (Flatpack) Dimensions in Inches and (Millimeters) MIL-STD-1835 D-16 CONFIG A MIL-STD-1835 F-18 CONFIG B 42.70(1.68) 41.70(1.64) PIN #1 ID 9.40(0.370) 6.86(0.270) PIN 1 15.50(0.610) 13.00(0.510) 0.51(0.020) 0.38(0.015) 21.08(0.830) 20.60(0.811) 1.27(0.050) BSC 2.49(0.098)MAX 38.10(1.500) REF 5.72(0.225) MAX 0.127(0.005)MIN SEATING PLANE 1.52(0.060) 0.38(0.015) 0.58(0.023) 0.36(0.014) 5.08(0.200) 3.18(0.125) 1.65(0.065) 1.14(0.045) 2.54(0.100)BSC 1.14(0.045) MAX 12.40(0.488) 11.99(0.472) 3.05(0.120) 2.49(0.098) 0.18(0.007) 0.10(0.004) 10.36(0.408) 9.02(0.355) 15.70(0.620) 15.00(0.590) 1.14(0.045) 0.66(0.026) 1.83(0.072) 0.76(0.030) 0º~ 15º REF 0.381(0.015) 0.203(0.008) 17.80(0.700) MAX MIL-STD-1835 C-12 JEDEC OUTLINE MO-115 32L, 32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters)* 44L, 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters)* 16.81(0.662) 16.26(0.640) 11.63(0.458) 11.23(0.442) 2.74(0.108) 2.16(0.085) 2.54(0.100) 2.16(0.085) 16.81(0.662) 16.26(0.640) 14.22(0.560) 13.72(0.540) 1.91(0.075) 1.40(0.055) PIN 1 2.41(0.095) 1.91(0.075) 1.40(0.055) 1.14(0.045) PIN 1 INDEX CORNER 2.41(0.095) 1.91(0.075) 1.40(0.055) 1.14(0.045) 0.635(0.025) X 45° 0.381(0.015) 0.305(0.012) RADIUS 0.178(0.007) 12.70(0.500) BSC 0.737(0.029) 0.533(0.021) 1.27(0.050) TYP 1.02(0.040) X 45° 7.62(0.300) BSC 2.16(0.085) 1.65(0.065) *Controlling dimension: millimeters 14 INDEX CORNER 0.635(0.025) X 45° 0.381(0.015) 0.305(0.012) RADIUS 0.178(0.007) 10.16(0.400) BSC 2.03(0.080) 1.40(0.055) 0.737(0.029) 0.533(0.021) 1.27(0.050) TYP 1.02(0.040) X 45° 12.70(0.500) BSC 2.16(0.085) 1.65(0.065) *Controlling dimension: millimeters AT28C010 Mil 0010D–PEEPR–7/09 AT28C010 Mil Packaging Information 30U, 30-Pin, Ceramic Pin Grid Array (PGA) Dimensions in Inches and (Millimeters) 7.26(0.286) 6.50(0.256) 13.74(0.541) 13.36(0.526) 2.57(0.101) 2.06(0.081) 16.18(0.637) 15.82(0.623) 1.40(0.055) 1.14(0.045) 0.58(0.023) 0.43(0.017) 3.12(0.123) 2.62(0.103) 1.83(0.072) 1.57(0.062) 14.17(0.558) 13.77(0.542) 2.54(0.100) TYP 16.71(0.658) 16.31(0.642) 12.70(0.500) TYP 2.54(0.100) TYP 10.41(0.410) 9.91(0.390) 15 0010D–PEEPR–7/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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