Qimonda HYS72D64320GBR-6-C 184-pin registered double data rate sdram module Datasheet

March 2007
HYS72D32300[G/H]BR–[5/6/7]–C
HYS72D64300[G/H]BR–[5/6/7]–C
HYS72D64320[G/H]BR–[5/6]–C
HYS72D128320[G/H]BR–[6/7]–C
184-Pin Registered Double Data Rate SDRAM Module
Reg DIMM
DDR SDRAM
Internet Data Sheet
Rev. 1.32
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
HYS72D32300[G/H]BR–[5/6/7]–C, HYS72D64300[G/H]BR–[5/6/7]–C, HYS72D64320[G/H]BR–[5/6]–C,
HYS72D128320[G/H]BR–[6/7]–C
Revision History: Rev. 1.32, 2007-03
Page
Subjects (major changes since last revision)
All
Adapted internet edition
6
Table updated
Previous Revision: Rev. 1.31, 2006-09
All
Qimonda update
Previous Revision: Rev. 1.3, 2005-11
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qag_techdoc_rev400 / 3.2 QAG / 2006-07-21
03292006-Q22P-G7TH
2
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
1
Overview
This chapter gives an overview of the 184-pin Registered Double Data Rate DDR2 SDRAM Modules with parity bit product
family and describes its main characteristics.
1.1
Features
• 184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM
Module for “1U” PC, Workstation and Server main memory
applications
• One rank 32M × 72 and 64M × 72 and two ranks 64M × 72
and 128M × 72 organization
• JEDEC standard Double Data Rate Synchronous DRAMs
(DDR SDRAM) with a single + 2.5 V (± 0.2 V) power
supply and + 2.6 V (± 0.1 V) power supply for DDR400
• Built with 256-Mbit DDR SDRAMs in P--TFBGA-60-1
packages
• Programmable CAS Latency, Burst Length, and Wrap
Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Re-drive for all input signals using register and PLL
devices.
• Serial Presence Detect with E2PROM
• Low Profile Modules form factor: 133.35 mm × 28.58 mm
× 4.00 mm / 2.64 mm and for 1GB 133.35 mm × 30.48 mm
(1.2”)× 4.00 mm
• JEDEC standard reference layout for one rank 256 MB,
512 MB and two ranks 512 MB, 1 GB: PC 2700 and
PC 3200 Registered DIMM Raw Cards A,B,C,D
• Gold plated contacts
TABLE 1
Performance
Part Number Speed Code
-5
–6
-7
Unit
Speed Grade
Component
DDR400B
DDR333B
DDR266A
—
Module
PC3200-3033
PC2700–2533
PC2100-2033
—
200
166
—
MHz
166
166
143
MHz
133
133
133
MHz
max. Clock
Frequency
@CL3
@CL2.5
@CL2
1.2
fCK3
fCK2.5
fCK2
Description
The HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C and
HYS72D64320GBR–5–C are low profile versions of the
standard Registered DIMM modules suitable for 1U Server
Applications. The Low Profile DIMM versions are available as
32M × 72 (256 MB), 64M × 72 (512 MB), 128M × 72 (1 GB)
The memory array is designed with Double Data Rate
Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. A variety of decoupling capacitors are
mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E2PROM device using the
2-pin I2C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
3
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 2
Ordering Information for Lead-Containing Products
Product Type
Compliance Code
Description
SDRAM
Technology
HYS72D32300GBR–5–C
PC3200R–30330–A0
1 Rank 256 MB Registered DIMM ECC
256 Mbit (×8)
HYS72D64300GBR–5–C
PC3200R–30330–C0
1 Rank 512 MB Registered DIMM ECC
256 Mbit (×4)
HYS72D64320GBR–5–C
PC3200R–30330–B0
2 Ranks 512 MB Registered DIMM ECC
256 Mbit (×8)
HYS72D32300GBR–6–C
PC2700R–25330–A0
1 Rank 256 MB Registered DIMM ECC
256 Mbit (×8)
PC3200 (CL = 3.0)
PC2700 (CL = 2.5)
HYS72D64300GBR–6–C
PC2700R–25330–C0
1 Rank 512 MB Registered DIMM ECC
256 Mbit (×4)
HYS72D64320GBR–6–C
PC2700R–25330–B0
2 Ranks 512 MB Registered DIMM ECC
256 Mbit (×8)
HYS72D128320GBR–6–C
PC2700R–25330–D0
2 Ranks 1 GB Registered DIMM ECC
256 Mbit (×4)
HYS72D32300GBR–7–C
PC2100R–20330–A0
1 Rank 256 MB Registered DIMM ECC
256 Mbit (×8)
HYS72D64300GBR–7–C
PC2100R–20330–C0
1 Rank 512 MB Registered DIMM ECC
256 Mbit (×4)
HYS72D128320GBR–7–C
PC2100R–20330–D0
2 Ranks 1 GB Registered DIMM ECC
256 Mbit (×4)
PC2100 (CL = 2.0)
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
4
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 3
Ordering Information for Lead-Free (RoHS Compliant) Products
Compliance Code2)
Description
SDRAM
Technology
HYS72D32300HBR–5–C
PC3200R–30330–A0
1 Rank 256 MB Registered DIMM ECC
256 Mbit (×8)
HYS72D64300HBR–5–C
PC3200R–30330–C0
1 Rank 512 MB Registered DIMM ECC
256 Mbit (×4)
HYS72D64320HBR–5–C
PC3200R–30330–B0
2 Ranks 512 MB Registered DIMM ECC 256 Mbit (×8)
PC2700R–25330–A0
1 Rank 256 MB Registered DIMM ECC
256 Mbit (×8)
256 Mbit (×4)
Product Type
1)
Note3)
PC3200 (CL = 3.0)
PC2700 (CL = 2.5)
HYS72D32300HBR–6–C
HYS72D64300HBR–6–C
PC2700R–25330–C0
1 Rank 512 MB Registered DIMM ECC
HYS72D64320HBR–6–C
PC2700R–25330–B0
2 Ranks 512 MB Registered DIMM ECC 256 Mbit (×8)
HYS72D128320HBR–6–C PC2700R–25330–D0
2 Ranks 1 GB Registered DIMM ECC
256 Mbit (×4)
256 Mbit (×8)
PC2100 (CL = 2.0)
HYS72D32300HBR–7–C
PC2100R–20330–A0
1 Rank 256 MB Registered DIMM ECC
HYS72D64300HBR–7–C
PC2100R–20330–C0
1 Rank 512 MB Registered DIMM ECC
256 Mbit (×4)
2 Ranks 1 GB Registered DIMM ECC
256 Mbit (×4)
HYS72D128320HBR–7–C PC2100R–20330–D0
1) All product types end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS72D128300GBR-5-B, indicating Rev.B die are used for SDRAM components.
2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC2100R”), the latencies (for example
“20330” means CAS latency of 2.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), JEDEC
SPD code definition version 0, and the Raw Card used for this module.
3) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
5
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
2
Pin Configuration
The pin configuration of the Registered DDR SDRAM DIMM
is listed by function in Table 4 (184 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 5
and Table 6 respectively. The pin numbering is depicted in
Figure 1.
TABLE 4
Pin Configuration of RDIMM
Pin
#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
137
CK0
I
SSTL
Clock Signal
138
CK0
I
SSTL
Complement Clock
21
CKE0
I
SSTL
Clock Enable Rank 0
111
CKE1
I
SSTL
Clock Enable Rank 1
Note: 2-rank module
NC
NC
SSTL
Note: 1-rank module
Pin
#
Name
Pin
Type
Buffer
Type
Function
125
A6
I
SSTL
Address Bus 11:0
29
A7
I
SSTL
122
A8
I
SSTL
27
A9
I
SSTL
141
A10
I
SSTL
AP
I
SSTL
118
A11
I
SSTL
115
A12
I
SSTL
Address Signal 12
Note: Module based on
256 Mbit or larger
dies
NC
NC
—
Note: 128 Mbit based
module
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based
module
NC
NC
—
Note: Module based on
512 Mbit or smaller
dies
Data Bus 63:0
167
Control Signals
157
S0
I
SSTL
Chip Select of Rank 0
158
S1
I
SSTL
Chip Select of Rank 1
Note: 2-ranks module
NC
NC
—
Note: 1-rank module
Data Signals
RAS
I
SSTL
Row Address Strobe
2
DQ0
I/O
SSTL
DQ1
I/O
SSTL
154
65
CAS
I
SSTL
Column Address Strobe
4
63
WE
I
SSTL
Write Enable
6
DQ2
I/O
SSTL
Register Reset
8
DQ3
I/O
SSTL
94
DQ4
I/O
SSTL
Address Signals
95
DQ5
I/O
SSTL
59
BA0
I
SSTL
98
DQ6
I/O
SSTL
52
BA1
I
SSTL
99
DQ7
I/O
SSTL
48
A0
I
SSTL
12
DQ8
I/O
SSTL
DQ9
I/O
SSTL
10
RESET
I
LVCMOS
Bank Address Bus 1:0
Address Bus 11:0
43
A1
I
SSTL
13
41
A2
I
SSTL
19
DQ10
I/O
SSTL
20
DQ11
I/O
SSTL
130
A3
I
SSTL
37
A4
I
SSTL
32
A5
I
SSTL
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
6
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin
#
Name
Pin
Type
Buffer
Type
Function
Pin
#
Name
Pin
Type
Buffer
Type
Function
105
DQ12
I/O
SSTL
Data Bus 63:0
165
DQ52
I/O
SSTL
Data Bus 63:0
106
DQ13
I/O
SSTL
166
DQ53
I/O
SSTL
109
DQ14
I/O
SSTL
170
DQ54
I/O
SSTL
110
DQ15
I/O
SSTL
171
DQ55
I/O
SSTL
23
DQ16
I/O
SSTL
83
DQ56
I/O
SSTL
24
DQ17
I/O
SSTL
84
DQ57
I/O
SSTL
28
DQ18
I/O
SSTL
87
DQ58
I/O
SSTL
31
DQ19
I/O
SSTL
88
DQ59
I/O
SSTL
114
DQ20
I/O
SSTL
174
DQ60
I/O
SSTL
117
DQ21
I/O
SSTL
175
DQ61
I/O
SSTL
121
DQ22
I/O
SSTL
178
DQ62
I/O
SSTL
123
DQ23
I/O
SSTL
179
DQ63
I/O
SSTL
33
DQ24
I/O
SSTL
44
CB0
I/O
SSTL
35
DQ25
I/O
SSTL
45
CB1
I/O
SSTL
39
DQ26
I/O
SSTL
49
CB2
I/O
SSTL
40
DQ27
I/O
SSTL
51
CB3
I/O
SSTL
126
DQ28
I/O
SSTL
134
CB4
I/O
SSTL
127
DQ29
I/O
SSTL
135
CB5
I/O
SSTL
131
DQ30
I/O
SSTL
142
CB6
I/O
SSTL
133
DQ31
I/O
SSTL
144
CB7
I/O
SSTL
53
DQ32
I/O
SSTL
5
DQS0
I/O
SSTL
55
DQ33
I/O
SSTL
14
DQS1
I/O
SSTL
57
DQ34
I/O
SSTL
25
DQS2
I/O
SSTL
60
DQ35
I/O
SSTL
36
DQS3
I/O
SSTL
146
DQ36
I/O
SSTL
56
DQS4
I/O
SSTL
147
DQ37
I/O
SSTL
67
DQS5
I/O
SSTL
150
DQ38
I/O
SSTL
78
DQS6
I/O
SSTL
151
DQ39
I/O
SSTL
86
DQS7
I/O
SSTL
61
DQ40
I/O
SSTL
47
DQS8
I/O
SSTL
64
DQ41
I/O
SSTL
97
DM0
I
SSTL
68
DQ42
I/O
SSTL
Data Mask 0
Note: ×8 based module
69
DQ43
I/O
SSTL
DQS9
I/O
SSTL
153
DQ44
I/O
SSTL
Data Strobe 9
Note: ×4 based module
155
DQ45
I/O
SSTL
DM1
I
SSTL
161
DQ46
I/O
SSTL
Data Mask 1
Note: ×8 based module
162
DQ47
I/O
SSTL
DQS10
I/O
SSTL
72
DQ48
I/O
SSTL
Data Strobe 10
Note: ×4 based module
73
DQ49
I/O
SSTL
79
DQ50
I/O
SSTL
80
DQ51
I/O
SSTL
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
107
7
Check Bits 7:0
Data Strobes 8:0
Data Strobes 8:0
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin
#
Name
Pin
Type
Buffer
Type
Function
Pin
#
119
DM2
I
SSTL
Data Mask 2
Note: ×8 based module
DQS11
I/O
SSTL
Data Strobe 11
Note: ×4 based module
DM3
I
SSTL
Data Mask 3
Note: ×8 based module
DQS12
I/O
SSTL
Data Strobe 12
Note: ×4 based module
DM4
I
SSTL
Data Mask 4
Note: ×8 based module
DQS13
I/O
SSTL
Data Strobe 13
Note: ×4 based module
DM5
I
SSTL
Data Mask 5
Note: ×8 based module
DQS14
I/O
SSTL
Data Strobe 14
Note: ×4 based module
DM6
I
SSTL
Data Mask 6
Note: ×8 based module
DQS15
I/O
SSTL
Data Strobe 15
Note: ×4 based module
DM7
I
SSTL
Data Mask 7
Note: ×8 based module
129
149
159
169
177
DQS16
I/O
SSTL
Data Strobe 16
Note: ×4 based module
DM8
I
SSTL
Data Mask 8
Note: ×8 based module
DQS17
I/O
SSTL
Data Strobe 17
Note: ×4 based module
SCL
I
CMOS
Serial Bus Clock
91
SDA
I/O
OD
Serial Bus Data
181
SA0
I
CMOS
182
SA1
I
CMOS
Slave Address Select
Bus 2:0
183
SA2
I
CMOS
140
E2PROM
92
Power Supplies
VREF
184 VDDSPD
1
AI
—
I/O Reference Voltage
PWR
—
E2PROM Power Supply
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
8
Name
Pin
Type
Buffer
Type
Function
15, VDDQ
22,
30,
54,
62,
77,
96,
104,
112,
128,
136,
143,
156,
164,
172,
180
PWR
—
I/O Driver Power Supply
7,
VDD
38,
46,
70,
85,
108,
120,
148,
168
PWR
—
Power Supply
VSS
3,
11,
18,
26,
34,
42,
50,
58,
66,
74,
81,
89,
93,
100,
116,
124,
132,
139,
145,
152,
160,
176
GND
—
Ground Plane
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Pin
#
Name
Pin
Type
Buffer
Type
Function
TABLE 5
Abbreviations for Pin Type
Other Pins
82
VDDID
9,
NC
16,
17,
71,
75,
76,
90,
101,
102,
103,
113,
163,
173
O
OD
VDD Identification
NC
—
Not connected
Abbreviatio
n
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NU
Not Usable (JEDEC Standard)
NC
Not Connected (JEDEC Standard)
TABLE 6
Abbreviations for Buffer Type
Abbreviatio
n
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
9
Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
FIGURE 1
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TABLE 7
Address Table
Density
Organization
Memory
Ranks
SDRAMs
# of SDRAMs
# of row/rank/
columns bits
Refresh
Period
Interval
256 MB
32 M ×72
1
32 M ×8
9
13 / 2 / 10
8K
64 ms
7.8 µs
512 MB
64 M ×72
1
64 M ×4
18
13 / 2 / 11
8K
64 ms
7.8 µs
512 MB
64 M ×72
2
32 M ×8
18
13 / 2 / 10
8K
64 ms
7.8 µs
1 GB
128 M ×72
2
64 M ×4
36
13 / 2 / 11
8K
64 ms
7.8 µs
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
10
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Operating Conditions
This chapter contains the operating conditions tables.
TABLE 8
Absolute Maximum Ratings
Parameter
Symbol
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
Values
VIN, VOUT
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
Unit
min.
typ.
max.
–0.5
—
VDDQ +0.5
V
–1
—
+3.6
V
–1
—
+3.6
V
–1
—
+3.6
V
0
—
+70
°C
–55
—
+150
°C
—
1
—
W
—
50
—
mA
Note/ Test
Condition
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress
rating only, and functional operation should be restricted to recommended operation conditions. Exposure
to absolute maximum rating conditions for extended periods of time may affect device reliability and
exceeding only one of the values may cause irreversible damage to the integrated circuit.
TABLE 9
Electrical Characteristics and DC Operating Conditions
Parameter
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
E2PROM supply voltage
Supply Voltage, I/O Supply
Voltage
Input Reference Voltage
I/O Termination Voltage
(System)
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
Symbol
VDD
VDD
VDDQ
VDDQ
VDDSPD
VSS,
VSSQ
VREF
VTT
Unit Note1)/Test Condition
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
3.6
V
0
—
0
V
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
4)
VREF – 0.04
—
VREF + 0.04
V
5)
11
fCK ≤ 166 MHz
fCK > 166 MHz 2)
fCK ≤ 166 MHz 3)
fCK > 166 MHz 2)3)
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Parameter
Symbol
Unit Note1)/Test Condition
Values
Min.
Typ.
Max.
VIH(DC)
Input Low (Logic0) Voltage
VIL(DC)
Input Voltage Level, CK and VIN(DC)
VREF + 0.15
—
V
6)
–0.3
—
V
6)
–0.3
—
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
6)
Input Differential Voltage, CK VID(DC)
and CK Inputs
0.36
—
VDDQ + 0.6
V
6)7)
VI-Matching Pull-up Current
to Pull-down Current
VIRatio
0.71
—
1.4
—
8)
Input Leakage Current
II
–2
—
2
µA
Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V
Input High (Logic1) Voltage
CK Inputs
6)9)
µA
DQs are disabled; 0 V ≤ VOUT ≤
IOZ
–5
Output High Current, Normal IOH
Strength Driver
—
—
–16.2
mA
VDDQ
VOUT = 1.95 V
16.2
—
—
mA
VOUT = 0.35 V
Output Leakage Current
Output Low Current, Normal
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C
2)
3)
4)
5)
6)
7)
8)
9)
IOL
—
5
DDR400 conditions apply for all clock frequencies above 166 MHz
Under all conditions, VDDQ must be less than or equal to VDD.
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
Inputs are not recognized as valid until VREF stabilizes.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
Values are shown per DDR SDRAM component
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
12
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
3.2
Current Conditions
This chapter describes the Conditions.
TABLE 10
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50 % of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50 % of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
13
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
3.3
Current Specifications
This chapter describes the Specifications.
TABLE 11
Product Type
HYS72D32300GBR–5–C
HYS72D32300HBR-–5–C
HYS72D64300GBR–5–C
HYS72D64300HBR–5–C
HYS72D64320GBR–5–C
HYS72D64320HBR–5–C
IDD Specification for HYS72D[128/64/32]3xxx[G/H]BR–5–C
Organization
256 MB
512 MB
512 MB
×72
×72
×72
1 Rank
1 Rank
2 Ranks
–5
–5
–5
Unit
Note/ Test Conditions1) 2)
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
1140
1370
2070
2480
1780
2080
mA
3)
1360
1600
2380
2800
2000
2310
mA
3)4)
390
440
730
790
730
790
mA
5)
880
990
1450
1620
1450
1620
mA
5)
540
650
1020
1200
1020
1200
mA
5)
470
560
890
720
890
1020
mA
5)
950
1080
1590
1780
1590
1780
mA
5)
1400
1600
2470
2800
2040
2310
mA
3)4)
1450
1650
2560
2890
2090
2350
mA
3)
1630
2120
3190
4130
2270
2830
mA
3)
330
370
640
700
640
700
mA
5)
3)4)
2950
4720
5500
3170
3660
mA
1) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
2) Module IDD is calculated on the basis of component IDD and includes Register and PLL
3) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank) n * IDD × [component] + n * IDD3N [component] for two bank modules (n: number of
2530
components per module bank)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank)2 * n * IDD × [component] for single two bank modules (n: number of components per module
bank)
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
14
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 12
Product Type
HYS72D32300GBR–6–C
HYS72D32300HBR–6–C
HYS72D64300GBR–6–C
HYS72D64300HBR–6–C
HYS72D64320GBR–6–C
HYS72D64320HBR–6–C
HYS72D128320GBR–6–C
HYS72D128320HBR–6–C
IDD Specification for HYS72D[256/128/64/32]3xxx[G/H]BR–6–C
Organization
256 MB
512 MB
512 MB
1 GB
×72
×72
×72
×72
1 Rank
1 Rank
2 Ranks
2 Ranks
–6
–6
–6
–6
Unit
Note/ Test Conditions1) 2)
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
1000
1190
1790
2110
1540
1780
2870
3290
mA
3)
1210
1410
2090
2420
1750
2000
3160
3600
mA
3)4)
370
410
650
710
650
710
1220
1300
mA
5)
780
880
1250
1400
1250
1400
2200
2440
mA
5)
480
580
890
1050
890
1050
1690
1980
mA
5)
430
500
780
640
780
890
1480
1660
mA
5)
840
950
1380
1540
1380
1540
2450
2730
mA
5)
1210
1410
2090
2420
1750
2000
3160
3600
mA
3)4)
1250
1450
2180
2510
1790
2040
3250
3690
mA
3)
1420
1820
2750
3510
1960
2410
3830
4690
mA
3)
320
370
580
640
580
640
1110
1190
mA
5)
3)4)
4070 4760 2740 3170 5140 5940 mA
1) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
2) Module IDD is calculated on the basis of component IDD and includes Register and PLL
3) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank)n * IDD × [component] + n * IDD3N [component] for two bank modules (n: number of
2200
2580
components per module bank)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank)2 * n * IDD × [component] for single two bank modules (n: number of components per module
bank)
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
15
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 13
Product Type
HYS72D32300GBR-7-C
HYS72D32300HBR-7-C
HYS72D64300GBR-7-C
HYS72D64300HBR-7-C
HYS72D128320GBR-7-C
HYS72D128320HBR-7-C
IDD Specification for HYS72D[128/64/32]3xxx[G/H]BR–7–C
Organization
256 MB
512 MB
1 GB
×72
×72
×72
1 Rank
1 Rank
2 Ranks
–7
–7
–7
Unit
Note/ Test Conditions1) 2)
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
860
1040
1510
1830
2410
2870
mA
3)
1100
1250
1890
2120
2790
3170
mA
3)4)
330
370
560
610
1010
1080
mA
5)
670
760
1050
1180
1810
2010
mA
5)
440
520
770
910
1440
1690
mA
5)
380
450
660
570
1230
1400
mA
5)
740
870
1200
1390
2100
2440
mA
5)
1060
1200
1800
2030
2700
3080
mA
3)4)
1100
1250
1890
2120
2790
3170
mA
3)
1210
1600
2310
3060
3210
4110
mA
3)
300
350
520
580
940
1030
mA
5)
3)4)
2100
3240
3830
4140
4880
mA
1) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
2) Module IDD is calculated on the basis of component IDD and includes Register and PLL
3) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank)n * IDD × [component] + n * IDD3N [component] for two bank modules (n: number of
1780
components per module bank)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDD values are calculated from the component IDD datasheet values are: n * IDD × [component] for single bank modules
(n: number of components per module bank)2 * n * IDD × [component] for single two bank modules (n: number of components per module
bank)
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
16
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
3.4
AC Characteristics
This chapter describes the AC characteristics.
TABLE 14
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
DQ output access time from CK/CK
CK high-level width
Clock cycle time
CK low-level width
Auto precharge write recovery +
precharge time
Symbol
tAC
tCH
tCK
tCL
tDAL
–5
–6
DDR400B
DDR333
Unit Note/ Test
Condition 1)
Min.
Max.
Min.
Max.
–0.5
+0.5
–0.7
+0.7
ns
2)3)4)5)
0.45
0.55
0.45
0.55
tCK
2)3)4)5)
5
8
6
12
ns
CL = 3.0 2)3)4)5)
6
12
6
12
ns
CL = 2.5 2)3)4)5)
7.5
12
7.5
12
ns
CL = 2.0 2)3)4)5)
tCK
tCK
2)3)4)5)
0.45
0.55
0.45
0.55
(tWR/tCK)+(tRP/tCK)
2)3)4)5)6)
tDH
DQ and DM input pulse width (each tDIPW
0.4
—
0.45
—
ns
2)3)4)5)
1.75
—
1.75
—
ns
2)3)4)5)6)
DQS output access time from CK/CK tDQSCK
–0.6
+0.6
–0.6
+0.6
ns
2)3)4)5)
tDQSL,H
0.35
—
0.35
—
tCK
2)3)4)5)
DQS-DQ skew (DQS and associated tDQSQ
DQ signals)
—
+0.40
—
+0.40
ns
TFBGA 2)3)4)5)
Write command to 1st DQS latching
transition
0.72
1.25
0.75
1.25
tCK
2)3)4)5)
tDS
DQS falling edge hold time from CK tDSH
0.4
—
0.45
—
ns
2)3)4)5)
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge to CK setup time
(write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
Clock Half Period
tHP
tHZ
min. (tCL, tCH) —
min. (tCL, tCH)
—
ns
2)3)4)5)
—
+0.7
–0.7
+0.7
ns
2)3)4)5)6)
tIH
0.6
—
0.75
—
ns
fast slew rate
DQ and DM input hold time
input)
DQS input low (high) pulse width
(write cycle)
tDQSS
DQ and DM input setup time
(write cycle)
Data-out high-impedance time from
CK/CK
Address and control input hold time
Control and Addr. input pulse width
(each input)
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
tIPW
3)4)5)6)7)
0.7
—
0.8
—
ns
slow slew
rate3)4)5)6)7)
2.2
—
2.2
—
ns
2)3)4)5)8)
17
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HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Parameter
Symbol
Address and control input setup time tIS
–5
–6
DDR400B
DDR333
Unit Note/ Test
Condition 1)
Min.
Max.
Min.
Max.
0.6
—
0.75
—
ns
fast slew rate
3)4)5)6)7)
0.7
—
0.8
—
ns
slow slew rate
3)4)5)6)7)
Data-out low-impedance time from
CK/CK
tLZ
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)6)
Mode register set command cycle
time
tMRD
2
—
2
—
tCK
2)3)4)5)
DQ/DQS output hold time
tQH
tQHS
tRAP
tRAS
tRC
tHP –tQHS
—
tHP –tQHS
—
ns
2)3)4)5)
—
+0.50
—
+0.50
ns
TFBGA 2)3)4)5)
tRCD
—
tRCD
—
ns
2)3)4)5)
40
70E+3
42
70E+3
ns
2)3)4)5)
55
—
60
—
ns
2)3)4)5)
tRCD
tREFI
tRFC
15
—
18
—
ns
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)9)
65
—
72
—
ns
2)3)4)5)
tRP
tRPRE
tRPST
tRRD
15
—
18
—
ns
2)3)4)5)
2)3)4)5)
Data hold skew factor
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh
command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-refresh
command period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B
command
tWPRE
Write preamble setup time
tWPRES
Write postamble
tWPST
Write recovery time
tWR
Internal write to read command delay tWTR
Exit self-refresh to non-read
tXSNR
Write preamble
0.9
1.1
0.9
1.1
0.40
0.60
0.40
0.60
tCK
tCK
10
—
12
—
ns
2)3)4)5)
0.25
—
0.25
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)8)
0.40
0.60
0.40
0.60
tCK
2)3)4)5)8)
15
—
15
—
ns
2)3)4)5)
2)3)4)5)
2
—
1
—
tCK
2)3)4)5)
75
—
75
—
ns
2)3)4)5)
command
2)3)4)5)
Exit self-refresh to read command
tXSRD
200
—
200
—
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac).
8) These parameters guarantee device timing, but they are not necessarily tested on each device.
9) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
18
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 15
AC Timing - Absolute Specifications for PC2700
Parameter
Symbol
–7
Unit
DDR266A
DQ output access time from CK/CK
CK high-level width
Clock cycle time
tAC
tCH
tCK
tCL
Auto precharge write recovery + precharge time tDAL
DQ and DM input hold time
tDH
DQ and DM input pulse width (each input)
tDIPW
DQS output access time from CK/CK
tDQSCK
DQS input low (high) pulse width (write cycle)
tDQSL,H
DQS-DQ skew (DQS and associated DQ signals) tDQSQ
Write command to 1st DQS latching transition
tDQSS
DQ and DM input setup time
tDS
DQS falling edge hold time from CK (write cycle) tDSH
DQS falling edge to CK setup time (write cycle) tDSS
Clock Half Period
tHP
Data-out high-impedance time from CK/CK
tHZ
Address and control input hold time
tIH
CK low-level width
Min.
Max.
–0.75
+0.75
Note/Test
Condition 1)
ns
2)3)4)5)
0.45
0.55
tCK
2)3)4)5)
7.5
12
ns
CL = 2.52)3)4)5)
7.5
12
ns
CL = 2.02)3)4)5)
0.45
0.55
2)3)4)5)
(tWR/tCK)+(tRP/tCK)
—
tCK
tCK
0.5
—
ns
2)3)4)5)
1.75
—
ns
2)3)4)5)
–0.75
+0.75
ns
2)3)4)5)
2)3)4)5)6)
0.35
—
tCK
2)3)4)5)
—
+0.5
ns
FBGA2)3)4)5)
0.75
1.25
tCK
2)3)4)5)
0.5
—
ns
2)3)4)5)
0.2
—
2)3)4)5)
0.2
—
tCK
tCK
min. (tCL, tCH)
—
ns
2)3)4)5)
–0.75
+0.75
ns
2)3)4)5)6)
0.9
—
ns
fast slew rate
2)3)4)5)
3)4)5)6)7)
1.0
—
ns
slow slew rate
3)4)5)6)8)
Control and Addr. input pulse width (each input)
Address and control input setup time
tIPW
tIS
2.2
—
ns
2)3)4)5)8)
0.9
—
ns
fast slew rate
3)4)5)6)8)
1.0
—
ns
slow slew rate
3)4)5)6)8)
Data-out low-impedance time from CK/CK
Mode register set command cycle time
DQ/DQS output hold time
Data hold skew factor
Active to Read w/AP delay
Active to Precharge command
Active to Active/Auto-refresh command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-refresh command
period
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
tLZ
tMRD
tQH
tQHS
tRAP
tRAS
tRC
tRCD
tREFI
tRFC
–0.75
+0.75
ns
2)3)4)5)6)
2
—
tCK
2)3)4)5)
ns
2)3)4)5)
tHP – tQHS
—
0.75
ns
FBGA2)3)4)5)
tRCD or tRASmin
—
ns
2)3)4)5)
45
120E+3
ns
2)3)4)5)
65
—
ns
2)3)4)5)
20
—
ns
2)3)4)5)
7.8
—
µs
2)3)4)5)8)
75
—
ns
2)3)4)5)
19
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Parameter
Symbol
–7
Unit
Note/Test
Condition 1)
DDR266A
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B command
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command delay
Exit self-refresh to non-read command
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tWTR
tXSNR
tXSRD
Exit self-refresh to read command
1) VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V ; 0 °C ≤ TA ≤ 70 °C
Min.
Max.
20
—
ns
2)3)4)5)
0.9
1.1
2)3)4)5)
0.4
0.6
tCK
tCK
15
—
ns
2)3)4)5)
0.25
—
tCK
2)3)4)5)
0
—
ns
2)3)4)5)9)
0.4
—
tCK
2)3)4)5)10)
15
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
1
—
tCK
75
—
ns
2)3)4)5)11)
tCK
2)3)4)5)
200
—
2) Input slew rate ≥ 1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
7) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac).
8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
10) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
11) In all circumstances, tXSNR can be satisfied using tXSNR = tRFC,min + 1 × tCK
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
20
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
•
•
Table 16 “HYS72D[32/64]3x0GBR-5-C” on Page 21
Table 17 “HYS72D[32/64/128]3x0GBR-6-C” on Page 25
Table 18 “HYS72D[32/64/128]3x0GBR-7-C” on Page 29
Table 19 “HYS72D[32/64]3x0HBR-5-C” on Page 33
Table 20 “HYS72D[32/64/128]3x0HBR-6-C” on Page 37
Table 21 “HYS72D[32/64/128]3x0HBR-7-C” on Page 41
TABLE 16
Product Type
HYS72D32300GBR–5–C
HYS72D64300GBR–5–C
HYS72D64320GBR–5–C
HYS72D[32/64]3x0GBR-5-C
Organization
256MB
512MB
512MB
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331
PC3200R–30331
PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
3
Number of Row Addresses
0D
0D
0D
4
Number of Column Addresses
0A
0B
0A
5
Number of DIMM Ranks
01
01
02
6
Data Width (LSB)
48
48
48
7
Data Width (MSB)
00
00
00
8
Interface Voltage Levels
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
50
50
50
10
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
50
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
21
Internet Data Sheet
Product Type
HYS72D32300GBR–5–C
HYS72D64300GBR–5–C
HYS72D64320GBR–5–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331
PC3200R–30331
PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
HEX
HEX
HEX
Description
11
Error Correction Support
02
02
02
12
Refresh Rate
82
82
82
13
Primary SDRAM Width
08
04
08
14
Error Checking SDRAM Width
08
04
08
15
tCCD [cycles]
01
01
01
16
Burst Length Supported
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
18
CAS Latency
1C
1C
1C
19
CS Latency
01
01
01
20
Write Latency
02
02
02
21
DIMM Attributes
26
26
26
22
Component Attributes
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
60
60
60
24
tAC SDRAM @ CLmax -0.5 [ns]
50
50
50
25
tCK @ CLmax -1 (Byte 18) [ns]
75
75
75
26
tAC SDRAM @ CLmax -1 [ns]
50
50
50
27
tRPmin [ns]
3C
3C
3C
28
tRRDmin [ns]
28
28
28
29
tRCDmin [ns]
3C
3C
3C
30
tRASmin [ns]
28
28
28
31
Module Density per Rank
40
80
40
32
tAS, tCS [ns]
60
60
60
33
tAH, tCH [ns]
60
60
60
34
tDS [ns]
40
40
40
35
tDH [ns]
40
40
40
36 - 40
Not used
00
00
00
41
tRCmin [ns]
37
37
37
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
22
Internet Data Sheet
Product Type
HYS72D32300GBR–5–C
HYS72D64300GBR–5–C
HYS72D64320GBR–5–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331
PC3200R–30331
PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
HEX
HEX
HEX
Description
42
tRFCmin [ns]
41
41
41
43
tCKmax [ns]
28
28
28
44
tDQSQmax [ns]
28
28
28
45
tQHSmax [ns]
50
50
50
46
not used
00
00
00
47
DIMM PCB Height
01
01
01
48 - 61
Not used
00
00
00
62
SPD Revision
10
10
10
63
Checksum of Byte 0-62
26
5F
27
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Part Number, Char 1
37
37
37
74
Part Number, Char 2
32
32
32
75
Part Number, Char 3
44
44
44
76
Part Number, Char 4
33
36
36
77
Part Number, Char 5
32
34
34
78
Part Number, Char 6
33
33
33
79
Part Number, Char 7
30
30
32
80
Part Number, Char 8
30
30
30
81
Part Number, Char 9
47
47
47
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
23
Internet Data Sheet
Product Type
HYS72D32300GBR–5–C
HYS72D64300GBR–5–C
HYS72D64320GBR–5–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331
PC3200R–30331
PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
82
Part Number, Char 10
42
42
42
83
Part Number, Char 11
52
52
52
84
Part Number, Char 12
35
35
35
85
Part Number, Char 13
43
43
43
86
Part Number, Char 14
20
20
20
87
Part Number, Char 15
20
20
20
88
Part Number, Char 16
20
20
20
89
Part Number, Char 17
20
20
20
90
Part Number, Char 18
20
20
20
91
Module Revision Code
1x
1x
1x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
00
00
00
99 - 127 Not used
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
24
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 17
Product Type
HYS72D32300GBR–6–C
HYS72D64300GBR–6–C
HYS72D64320GBR–6–C
HYS72D128320GBR–6–C
HYS72D[32/64/128]3x0GBR-6-C
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
07
3
Number of Row Addresses
0D
0D
0D
0D
4
Number of Column Addresses
0A
0B
0A
0B
5
Number of DIMM Ranks
01
01
02
02
6
Data Width (LSB)
48
48
48
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
60
60
60
60
10
tAC SDRAM @ CLmax (Byte 18) [ns]
70
70
70
70
11
Error Correction Support
02
02
02
02
12
Refresh Rate
82
82
82
82
13
Primary SDRAM Width
08
04
08
04
14
Error Checking SDRAM Width
08
04
08
04
15
tCCD [cycles]
01
01
01
01
16
Burst Length Supported
0E
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
04
18
CAS Latency
0C
0C
0C
0C
19
CS Latency
01
01
01
01
20
Write Latency
02
02
02
02
21
DIMM Attributes
26
26
26
26
22
Component Attributes
C1
C1
C1
C1
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
25
Internet Data Sheet
Product Type
HYS72D32300GBR–6–C
HYS72D64300GBR–6–C
HYS72D64320GBR–6–C
HYS72D128320GBR–6–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Rev. 0.0
Byte#
HEX
HEX
HEX
HEX
Description
23
tCK @ CLmax -0.5 (Byte 18) [ns]
75
75
75
75
24
tAC SDRAM @ CLmax -0.5 [ns]
70
70
70
70
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
00
00
26
tAC SDRAM @ CLmax -1 [ns]
00
00
00
00
27
tRPmin [ns]
48
48
48
48
28
tRRDmin [ns]
30
30
30
30
29
tRCDmin [ns]
48
48
48
48
30
tRASmin [ns]
2A
2A
2A
2A
31
Module Density per Rank
40
80
40
80
32
tAS, tCS [ns]
75
75
75
75
33
tAH, tCH [ns]
75
75
75
75
34
tDS [ns]
45
45
45
45
35
tDH [ns]
45
45
45
45
36 - 40
Not used
00
00
00
00
41
tRCmin [ns]
3C
3C
3C
3C
42
tRFCmin [ns]
48
48
48
48
43
tCKmax [ns]
30
30
30
30
44
tDQSQmax [ns]
28
28
28
28
45
tQHSmax [ns]
50
50
50
50
46
not used
00
00
00
00
47
DIMM PCB Height
00
00
00
00
48 - 61
Not used
00
00
00
00
62
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62
0F
48
10
49
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
26
Internet Data Sheet
Product Type
HYS72D32300GBR–6–C
HYS72D64300GBR–6–C
HYS72D64320GBR–6–C
HYS72D128320GBR–6–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
HEX
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
73
Part Number, Char 1
37
37
37
37
74
Part Number, Char 2
32
32
32
32
75
Part Number, Char 3
44
44
44
44
76
Part Number, Char 4
33
36
36
31
77
Part Number, Char 5
32
34
34
32
78
Part Number, Char 6
33
33
33
38
79
Part Number, Char 7
30
30
32
33
80
Part Number, Char 8
30
30
30
32
81
Part Number, Char 9
47
47
47
30
82
Part Number, Char 10
42
42
42
47
83
Part Number, Char 11
52
52
52
42
84
Part Number, Char 12
36
36
36
52
85
Part Number, Char 13
43
43
43
36
86
Part Number, Char 14
20
20
20
43
87
Part Number, Char 15
20
20
20
20
88
Part Number, Char 16
20
20
20
20
89
Part Number, Char 17
20
20
20
20
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
27
Internet Data Sheet
Product Type
HYS72D32300GBR–6–C
HYS72D64300GBR–6–C
HYS72D64320GBR–6–C
HYS72D128320GBR–6–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
HEX
90
Part Number, Char 18
20
20
20
20
91
Module Revision Code
1x
1x
1x
1x
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
00
00
00
00
99 - 127 Not used
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
28
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 18
Product Type
HYS72D32300GBR–7–C
HYS72D64300GBR–7–C
HYS72D128320GBR–7–C
HYS72D[32/64/128]3x0GBR-7-C
Organization
256MB
512MB
1 GByte
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330
PC2100R–20331
PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
Rev. 1.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
3
Number of Row Addresses
0D
0D
0D
4
Number of Column Addresses
0A
0B
0B
5
Number of DIMM Ranks
01
01
02
6
Data Width (LSB)
48
48
48
7
Data Width (MSB)
00
00
00
8
Interface Voltage Levels
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
70
70
70
10
tAC SDRAM @ CLmax (Byte 18) [ns]
75
75
75
11
Error Correction Support
02
02
02
12
Refresh Rate
82
82
82
13
Primary SDRAM Width
08
04
04
14
Error Checking SDRAM Width
08
04
04
15
tCCD [cycles]
01
01
01
16
Burst Length Supported
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
18
CAS Latency
0C
0C
0C
19
CS Latency
01
01
01
20
Write Latency
02
02
02
21
DIMM Attributes
26
26
26
22
Component Attributes
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
75
75
75
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
29
Internet Data Sheet
Product Type
HYS72D32300GBR–7–C
HYS72D64300GBR–7–C
HYS72D128320GBR–7–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
1 GByte
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330
PC2100R–20331
PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
Rev. 1.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
24
tAC SDRAM @ CLmax -0.5 [ns]
75
75
75
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
00
26
tAC SDRAM @ CLmax -1 [ns]
00
00
00
27
tRPmin [ns]
50
50
50
28
tRRDmin [ns]
3C
3C
3C
29
tRCDmin [ns]
50
50
50
30
tRASmin [ns]
2D
2D
2D
31
Module Density per Rank
40
80
80
32
tAS, tCS [ns]
90
90
90
33
tAH, tCH [ns]
90
90
90
34
tDS [ns]
50
50
50
35
tDH [ns]
50
50
50
36 - 40
Not used
00
00
00
41
tRCmin [ns]
41
41
41
42
tRFCmin [ns]
4B
4B
4B
43
tCKmax [ns]
30
30
30
44
tDQSQmax [ns]
32
32
32
45
tQHSmax [ns]
75
75
75
46
not used
00
00
00
47
DIMM PCB Height
00
00
00
48 - 61
Not used
00
00
00
62
SPD Revision
00
10
00
63
Checksum of Byte 0-62
CB
14
05
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
30
Internet Data Sheet
Product Type
HYS72D32300GBR–7–C
HYS72D64300GBR–7–C
HYS72D128320GBR–7–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
1 GByte
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330
PC2100R–20331
PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
Rev. 1.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Part Number, Char 1
37
37
37
74
Part Number, Char 2
32
32
32
75
Part Number, Char 3
44
44
44
76
Part Number, Char 4
33
36
31
77
Part Number, Char 5
32
34
32
78
Part Number, Char 6
33
33
38
79
Part Number, Char 7
30
30
33
80
Part Number, Char 8
30
30
32
81
Part Number, Char 9
47
47
30
82
Part Number, Char 10
42
42
47
83
Part Number, Char 11
52
52
42
84
Part Number, Char 12
37
37
52
85
Part Number, Char 13
43
43
37
86
Part Number, Char 14
20
20
43
87
Part Number, Char 15
20
20
20
88
Part Number, Char 16
20
20
20
89
Part Number, Char 17
20
20
20
90
Part Number, Char 18
20
20
20
91
Module Revision Code
1x
0x
1x
92
Test Program Revision Code
xx
xx
xx
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
31
Internet Data Sheet
Product Type
HYS72D32300GBR–7–C
HYS72D64300GBR–7–C
HYS72D128320GBR–7–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
1 GByte
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330
PC2100R–20331
PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
Rev. 1.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
00
00
00
99 - 127 Not used
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
32
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 19
Product Type
HYS72D32300HBR–5–C
HYS72D64300HBR–5–C
HYS72D64320HBR–5–C
HYS72D[32/64]3x0HBR-5-C
Organization
256MB
512MB
512MB
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331
PC3200R–30331
PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
3
Number of Row Addresses
0D
0D
0D
4
Number of Column Addresses
0A
0B
0A
5
Number of DIMM Ranks
01
01
02
6
Data Width (LSB)
48
48
48
7
Data Width (MSB)
00
00
00
8
Interface Voltage Levels
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
50
50
50
10
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
50
11
Error Correction Support
02
02
02
12
Refresh Rate
82
82
82
13
Primary SDRAM Width
08
04
08
14
Error Checking SDRAM Width
08
04
08
15
tCCD [cycles]
01
01
01
16
Burst Length Supported
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
18
CAS Latency
1C
1C
1C
19
CS Latency
01
01
01
20
Write Latency
02
02
02
21
DIMM Attributes
26
26
26
22
Component Attributes
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
60
60
60
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
33
Internet Data Sheet
Product Type
HYS72D32300HBR–5–C
HYS72D64300HBR–5–C
HYS72D64320HBR–5–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331
PC3200R–30331
PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
24
tAC SDRAM @ CLmax -0.5 [ns]
50
50
50
25
tCK @ CLmax -1 (Byte 18) [ns]
75
75
75
26
tAC SDRAM @ CLmax -1 [ns]
50
50
50
27
tRPmin [ns]
3C
3C
3C
28
tRRDmin [ns]
28
28
28
29
tRCDmin [ns]
3C
3C
3C
30
tRASmin [ns]
28
28
28
31
Module Density per Rank
40
80
40
32
tAS, tCS [ns]
60
60
60
33
tAH, tCH [ns]
60
60
60
34
tDS [ns]
40
40
40
35
tDH [ns]
40
40
40
36 - 40
Not used
00
00
00
41
tRCmin [ns]
37
37
37
42
tRFCmin [ns]
41
41
41
43
tCKmax [ns]
28
28
28
44
tDQSQmax [ns]
28
28
28
45
tQHSmax [ns]
50
50
50
46
not used
00
00
00
47
DIMM PCB Height
01
01
01
48 - 61
Not used
00
00
00
62
SPD Revision
10
10
10
63
Checksum of Byte 0-62
26
5F
27
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
34
Internet Data Sheet
Product Type
HYS72D32300HBR–5–C
HYS72D64300HBR–5–C
HYS72D64320HBR–5–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331
PC3200R–30331
PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Part Number, Char 1
37
37
37
74
Part Number, Char 2
32
32
32
75
Part Number, Char 3
44
44
44
76
Part Number, Char 4
33
36
36
77
Part Number, Char 5
32
34
34
78
Part Number, Char 6
33
33
33
79
Part Number, Char 7
30
30
32
80
Part Number, Char 8
30
30
30
81
Part Number, Char 9
48
48
48
82
Part Number, Char 10
42
42
42
83
Part Number, Char 11
52
52
52
84
Part Number, Char 12
35
35
35
85
Part Number, Char 13
43
43
43
86
Part Number, Char 14
20
20
20
87
Part Number, Char 15
20
20
20
88
Part Number, Char 16
20
20
20
89
Part Number, Char 17
20
20
20
90
Part Number, Char 18
20
20
20
91
Module Revision Code
1x
1x
1x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
35
Internet Data Sheet
Product Type
HYS72D32300HBR–5–C
HYS72D64300HBR–5–C
HYS72D64320HBR–5–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8)
Label Code
PC3200R–30331
PC3200R–30331
PC3200R–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
95 - 98
Module Serial Number
xx
xx
xx
00
00
00
99 - 127 Not used
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
36
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 20
Product Type
HYS72D32300HBR–6–C
HYS72D64300HBR–6–C
HYS72D64320HBR–6–C
HYS72D128320HBR–6–C
HYS72D[32/64/128]3x0HBR-6-C
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
07
3
Number of Row Addresses
0D
0D
0D
0D
4
Number of Column Addresses
0A
0B
0A
0B
5
Number of DIMM Ranks
01
01
02
02
6
Data Width (LSB)
48
48
48
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
60
60
60
60
10
tAC SDRAM @ CLmax (Byte 18) [ns]
70
70
70
70
11
Error Correction Support
02
02
02
02
12
Refresh Rate
82
82
82
82
13
Primary SDRAM Width
08
04
08
04
14
Error Checking SDRAM Width
08
04
08
04
15
tCCD [cycles]
01
01
01
01
16
Burst Length Supported
0E
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
04
18
CAS Latency
0C
0C
0C
0C
19
CS Latency
01
01
01
01
20
Write Latency
02
02
02
02
21
DIMM Attributes
26
26
26
26
22
Component Attributes
C1
C1
C1
C1
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
37
Internet Data Sheet
Product Type
HYS72D32300HBR–6–C
HYS72D64300HBR–6–C
HYS72D64320HBR–6–C
HYS72D128320HBR–6–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Rev. 0.0
Byte#
HEX
HEX
HEX
HEX
Description
23
tCK @ CLmax -0.5 (Byte 18) [ns]
75
75
75
75
24
tAC SDRAM @ CLmax -0.5 [ns]
70
70
70
70
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
00
00
26
tAC SDRAM @ CLmax -1 [ns]
00
00
00
00
27
tRPmin [ns]
48
48
48
48
28
tRRDmin [ns]
30
30
30
30
29
tRCDmin [ns]
48
48
48
48
30
tRASmin [ns]
2A
2A
2A
2A
31
Module Density per Rank
40
80
40
80
32
tAS, tCS [ns]
75
75
75
75
33
tAH, tCH [ns]
75
75
75
75
34
tDS [ns]
45
45
45
45
35
tDH [ns]
45
45
45
45
36 - 40
Not used
00
00
00
00
41
tRCmin [ns]
3C
3C
3C
3C
42
tRFCmin [ns]
48
48
48
48
43
tCKmax [ns]
30
30
30
30
44
tDQSQmax [ns]
28
28
28
28
45
tQHSmax [ns]
50
50
50
50
46
not used
00
00
00
00
47
DIMM PCB Height
00
00
00
00
48 - 61
Not used
00
00
00
00
62
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62
0F
48
10
49
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
38
Internet Data Sheet
Product Type
HYS72D32300HBR–6–C
HYS72D64300HBR–6–C
HYS72D64320HBR–6–C
HYS72D128320HBR–6–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
HEX
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
73
Part Number, Char 1
37
37
37
37
74
Part Number, Char 2
32
32
32
32
75
Part Number, Char 3
44
44
44
44
76
Part Number, Char 4
33
36
36
31
77
Part Number, Char 5
32
34
34
32
78
Part Number, Char 6
33
33
33
38
79
Part Number, Char 7
30
30
32
33
80
Part Number, Char 8
30
30
30
32
81
Part Number, Char 9
48
48
48
30
82
Part Number, Char 10
42
42
42
48
83
Part Number, Char 11
52
52
52
42
84
Part Number, Char 12
36
36
36
52
85
Part Number, Char 13
43
43
43
36
86
Part Number, Char 14
20
20
20
43
87
Part Number, Char 15
20
20
20
20
88
Part Number, Char 16
20
20
20
20
89
Part Number, Char 17
20
20
20
20
90
Part Number, Char 18
20
20
20
20
91
Module Revision Code
1x
1x
1x
1x
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
39
Internet Data Sheet
Product Type
HYS72D32300HBR–6–C
HYS72D64300HBR–6–C
HYS72D64320HBR–6–C
HYS72D128320HBR–6–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
512MB
1 GByte
×72
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×8) 2 Ranks (×4)
Label Code
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
PC2700R–
25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Rev. 0.0
Byte#
HEX
HEX
HEX
HEX
Description
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
00
00
00
00
99 - 127 Not used
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
40
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
TABLE 21
Product Type
HYS72D32300HBR–7–C
HYS72D64300HBR–7–C
HYS72D128320HBR–7–C
HYS72D[32/64/128]3x0HBR-7-C
Organization
256MB
512MB
1 GByte
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330
PC2100R–20331
PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
Rev. 1.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
3
Number of Row Addresses
0D
0D
0D
4
Number of Column Addresses
0A
0B
0B
5
Number of DIMM Ranks
01
01
02
6
Data Width (LSB)
48
48
48
7
Data Width (MSB)
00
00
00
8
Interface Voltage Levels
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
70
70
70
10
tAC SDRAM @ CLmax (Byte 18) [ns]
75
75
75
11
Error Correction Support
02
02
02
12
Refresh Rate
82
82
82
13
Primary SDRAM Width
08
04
04
14
Error Checking SDRAM Width
08
04
04
15
tCCD [cycles]
01
01
01
16
Burst Length Supported
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
18
CAS Latency
0C
0C
0C
19
CS Latency
01
01
01
20
Write Latency
02
02
02
21
DIMM Attributes
26
26
26
22
Component Attributes
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
75
75
75
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
41
Internet Data Sheet
Product Type
HYS72D32300HBR–7–C
HYS72D64300HBR–7–C
HYS72D128320HBR–7–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
1 GByte
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330
PC2100R–20331
PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
Rev. 1.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
24
tAC SDRAM @ CLmax -0.5 [ns]
75
75
75
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
00
26
tAC SDRAM @ CLmax -1 [ns]
00
00
00
27
tRPmin [ns]
50
50
50
28
tRRDmin [ns]
3C
3C
3C
29
tRCDmin [ns]
50
50
50
30
tRASmin [ns]
2D
2D
2D
31
Module Density per Rank
40
80
80
32
tAS, tCS [ns]
90
90
90
33
tAH, tCH [ns]
90
90
90
34
tDS [ns]
50
50
50
35
tDH [ns]
50
50
50
36 - 40
Not used
00
00
00
41
tRCmin [ns]
41
41
41
42
tRFCmin [ns]
4B
4B
4B
43
tCKmax [ns]
30
30
30
44
tDQSQmax [ns]
32
32
32
45
tQHSmax [ns]
75
75
75
46
not used
00
00
00
47
DIMM PCB Height
00
00
00
48 - 61
Not used
00
00
00
62
SPD Revision
00
10
00
63
Checksum of Byte 0-62
CB
14
05
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
42
Internet Data Sheet
Product Type
HYS72D32300HBR–7–C
HYS72D64300HBR–7–C
HYS72D128320HBR–7–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
1 GByte
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330
PC2100R–20331
PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
Rev. 1.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Part Number, Char 1
37
37
37
74
Part Number, Char 2
32
32
32
75
Part Number, Char 3
44
44
44
76
Part Number, Char 4
33
36
31
77
Part Number, Char 5
32
34
32
78
Part Number, Char 6
33
33
38
79
Part Number, Char 7
30
30
33
80
Part Number, Char 8
30
30
32
81
Part Number, Char 9
48
48
30
82
Part Number, Char 10
42
42
48
83
Part Number, Char 11
52
52
42
84
Part Number, Char 12
37
37
52
85
Part Number, Char 13
43
43
37
86
Part Number, Char 14
20
20
43
87
Part Number, Char 15
20
20
20
88
Part Number, Char 16
20
20
20
89
Part Number, Char 17
20
20
20
90
Part Number, Char 18
20
20
20
91
Module Revision Code
1x
0x
1x
92
Test Program Revision Code
xx
xx
xx
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
43
Internet Data Sheet
Product Type
HYS72D32300HBR–7–C
HYS72D64300HBR–7–C
HYS72D128320HBR–7–C
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Organization
256MB
512MB
1 GByte
×72
×72
×72
1 Rank (×8)
1 Rank (×4)
2 Ranks (×4)
Label Code
PC2100R–20330
PC2100R–20331
PC2100R–20330
JEDEC SPD Revision
Rev. 0.0
Rev. 1.0
Rev. 0.0
Byte#
Description
HEX
HEX
HEX
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
00
00
00
99 - 127 Not used
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
44
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
5
Package Outlines
This chapter contains the package outlines of the products.
5.1
Raw Card A
FIGURE 2
0.1 A B C
Package Outlines – Raw Card A HYS72D32300[G/H]BR–[5/6/7]–C (1 Rank × 8)
133.35
0.15 A B C
128.95
2.64 MAX.
28.58 ±0.13
4 ±0.1
A
1
2.5 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
1.8 ±0.1
0.1 A B C
184
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
45
17.8
93
10
3.8 ±0.13
95 x 1.27 = 120.65
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
5.2
Raw Card B
FIGURE 3
0.1 A B C
Package Outlines – Raw Card B HYS72D64320GBR–[5/6]–C (2 Ranks ×8)
133.35
0.15 A B C
128.95
4 MAX.
28.58 ±0.13
4 ±0.1
A
1
2.5 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
1.8 ±0.1
0.1 A B C
184
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
46
17.8
93
10
3.8 ±0.13
95 x 1.27 = 120.65
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
5.3
Raw Card C
FIGURE 4
Package Outlines – Raw Card C HYS72D64300[G/H]BR–[5/6/7]–C (1 Rank × 4)
$ % &
$ % &
0
$;
“ “
$
“
%
¡$ %&
&
“ “
$ % &
“ [ 0
,1
“ 'HWD LORIFR Q
WDF WV
“ $ %&
%XU UPD [ DOORZ
H G
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
*/' 47
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
5.4
Raw Card D
FIGURE 5
Package Outlines – Raw Card D HYS72D128320[G/H]BR–[6/7]–C (2 Ranks ×4)
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
30.48 ±0.13
4 ±0.1
A
1
2.5 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
0.1 A B C
93
184
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
48
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
Internet Data Sheet
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
5.1
5.2
5.3
5.4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Raw Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Raw Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Raw Card C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Raw Card D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
13
14
17
45
45
46
47
48
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
49
Internet Data Sheet
Edition 2007-03
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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