AD ADG5419BCPZ-RL7 High voltage latch-up proof, single spdt switch Datasheet

High Voltage Latch-Up Proof,
Single SPDT Switch
ADG5419
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Latch-up immune under all circumstances
Human body model (HBM) ESD rating: 8 kV
Low on resistance: 13.5 Ω
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VDD to VSS analog signal range
SA
ADG5419
D
SB
IN
EN
SWITCHES SHOWN FOR A LOGIC 0 INPUT.
APPLICATIONS
11370-001
DECODER
Figure 1. 8-Lead LFCSP
High voltage signal routing
Automatic test equipment
Analog front-end circuits
Precision data acquisition
Industrial instrumentation
Amplifier gain select
Relay replacement
ADG5419
SA
D
SB
SWITCHES SHOWN FOR A LOGIC 0 INPUT.
11370-101
IN
Figure 2. 8-Lead MSOP
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG5419 is a monolithic industrial, complementary metal
oxide semiconductor (CMOS) analog switch containing a latchup immune single-pole/double-throw (SPDT) switch.
1.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked. The ADG5419 exhibits break-before-make
switching action for use in multiplexer applications.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications where low distortion is critical. The
latch-up immune construction and high ESD rating make these
switches more robust in harsh environments.
Rev. A
2.
3.
4.
5.
6.
7.
Trench isolation guards against latch-up. A dielectric trench
separates the P channel and N channel transistors, thereby
preventing latch-up even under severe overvoltage
conditions.
Low RON of 13.5 Ω.
Dual-supply operation. For applications where the analog
signal is bipolar, the ADG5419 can be operated from dual
supplies up to ±22 V.
Single-supply operation. For applications where the analog
signal is unipolar, the ADG5419 can be operated from a
single-rail power supply up to 40 V.
3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
No VL logic power supply required.
Available in 8-lead MSOP and 8-lead, 2 mm × 3 mm
LFCSP packages.
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ADG5419
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Continuous Current per Channel, Sx or D ................................7
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................8
Functional Block DiagramS ............................................................ 1
ESD Caution...................................................................................8
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ............................9
Product Highlights ........................................................................... 1
Typical Performance Characteristics ........................................... 10
Revision History ............................................................................... 2
Test Circuits ..................................................................................... 14
Specifications..................................................................................... 3
Terminology .................................................................................... 17
±15 V Dual Supply ....................................................................... 3
Applications Information .............................................................. 18
±20 V Dual Supply ....................................................................... 4
Trench Isolation .......................................................................... 18
12 V Single Supply ........................................................................ 5
Outline Dimensions ....................................................................... 19
36 V Single Supply ........................................................................ 6
Ordering Guide .......................................................................... 19
REVISION HISTORY
3/15—Rev. 0 to Rev. A
Added 8-Lead LFCSP ......................................................... Universal
Added Figure 1; Renumbered Sequentially .................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Changes to Table 4 ............................................................................ 6
Changed Continuous Current, Sx or D to 8-Lead MSOP,
Table 5 ................................................................................................ 7
Added Figure 3 and Table 8; Renumbered Sequentially ............. 9
Changes to Table 7 ............................................................................ 9
Changes to Figure 5 ........................................................................ 10
Added Figure 23 ............................................................................. 13
Changes to Figure 24 Caption ...................................................... 14
Added Figure 25 and Figure 26 .................................................... 14
Deleted Figure 27; Renumbered Sequentially ............................ 14
Added Figure 32 and Figure 33 .................................................... 15
Changes to Terminology Section ................................................. 17
Added Figure 37, Outline Dimensions ........................................ 19
Changes to Ordering Guide .......................................................... 19
9/13—Revision 0: Initial Version
Rev. A | Page 2 of 19
Data Sheet
ADG5419
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels,
∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
13.5
15
0.1
0.8
1.8
2.2
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −10 mA; see Figure 27
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −10 mA
19
23
1.3
1.4
2.7
3.1
±0.1
±0.25
±0.1
±0.4
±0.1
±1
±10
±4
±10
±0.4
±4
nA typ
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD =  10 V; see Figure 24 and
Figure 25
nA max
nA typ
nA max
nA typ
nA max
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
6
Break-Before-Make Time Delay, tD
217
260
179
212
153
176
86
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
130
−60
−80
0.01
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
190
−0.8
12
23
55
MHz typ
dB typ
pF typ
pF typ
pF typ
tON (EN)
tOFF (EN)
310
336
261
298
195
209
45
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
ISS
45
55
0.001
VDD/VSS
1
VS = ±10 V, IS = −10 mA
±10
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
Ω max
Ω typ
Ω max
70
1
±9/±22
Guaranteed by design; not subject to production test.
Rev. A | Page 3 of 19
μA typ
μA max
μA typ
μA max
V min/V max
VS = ±10 V, VD =  10 V; see Figure 25
VS = VD = ±10 V; see Figure 24 and
Figure 26
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 34
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz; see
Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
ADG5419
Data Sheet
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels,
∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
12.5
14
0.1
0.8
2.3
2.7
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
VS = ±15 V, IS = −10 mA; see Figure 27
VDD = +18 V, VSS = −18 V
VS = ±15 V, IS = −10 mA
18
22
1.3
1.4
3.3
3.7
±0.1
±0.25
±0.1
±0.4
±0.1
±1
±10
±4
±10
±0.4
±4
nA typ
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD =  15 V; see Figure 24 and
Figure 25
nA max
nA typ
nA max
nA typ
nA max
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
6
Break-Before-Make Time Delay, tD
200
235
199
239
157
185
77
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
160
−60
−80
0.01
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
190
−0.7
11
22
55
MHz typ
dB typ
pF typ
pF typ
pF typ
tON (EN)
tOFF (EN)
279
294
300
344
208
227
46
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
ISS
50
70
0.001
VDD/VSS
1
VS = ±15 V, IS = −10 mA
±10
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
Ω max
Ω typ
Ω max
110
1
±9/±22
Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 19
μA typ
μA max
μA typ
μA max
V min/V max
VS = ±15 V, VD =  15 V; see Figure 25
VS = VD = ±15 V; see Figure 24 and
Figure 26
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 34
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz; see
Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
Data Sheet
ADG5419
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels,
∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to +85°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
26
38
44
Ω max
Ω typ
1
5.5
6.8
1.5
1.6
VS = 0 V to 10 V, IS = −10 mA
8.3
12.3
Ω max
Ω typ
Ω max
nA typ
VDD = +13.2 V, VSS = 0 V
VS = 1 V to 10 V, VD = 10 V to 1 V;
see Figure 24 and Figure 25
±0.1
±0.25
±0.1
±0.4
±0.1
±1
±10
±4
±10
±0.4
±4
±10
nA max
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.002
6
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
55
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−60
dB typ
Channel-to-Channel Crosstalk
−80
dB typ
Total Harmonic Distortion + Noise
0.03
% typ
−3 dB Bandwidth
Insertion Loss
170
−1.7
MHz typ
dB typ
15
29
50
pF typ
pF typ
pF typ
tOFF (EN)
508
567
526
612
528
611
97
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
40
50
VDD
1
nA max
nA typ
nA max
nA typ
333
414
327
410
166
200
176
tON (EN)
VS = 0 V to 10 V, IS = −10 mA; see
Figure 27
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
30
0.1
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
Test Conditions/Comments
65
9/40
Guaranteed by design; not subject to production test.
Rev. A | Page 5 of 19
μA typ
μA max
V min/V max
VS = 1V to10 V, VD = 10 V to 1V; see Figure 25
VS = VD = 1 V to 10 V; see Figure 24 and
Figure 26
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 34
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 28
RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz; see
Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 31
VS = 6 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
ADG5419
Data Sheet
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels,
∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
25°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
14.5
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
24
Ω max
Ω typ
0.8
3.5
4.3
1.3
1.4
VS = 0 V to 30 V, IS = −10 mA
5.5
6.5
Ω max
Ω typ
Ω max
nA typ
VDD = 39.6 V, VSS = 0 V
VS = 1 V to 30 V, VD = 30 V to 1 V; see Figure 24
and Figure 25
±0.1
±0.25
±0.1
±0.4
±0.1
±1
±10
±4
±10
±4
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
ns typ
ns max
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 34
VS = 18 V, RS = 0 Ω, CL = 1 nF; see
Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 28
RL = 1 kΩ, 18 V p-p, f = 20 Hz to 20 kHz; see
Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
VS = 18 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
Digital inputs = 0 V or VDD
286
310
279
315
284
315
80
Charge Injection, QINJ
135
ns typ
ns min
pC typ
Off Isolation
−60
dB typ
Channel-to-Channel Crosstalk
−80
dB typ
Total Harmonic Distortion + Noise
0.01
% typ
−3 dB Bandwidth
Insertion Loss
170
−1
MHz typ
dB typ
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
14
26
50
pF typ
pF typ
pF typ
VDD
VS = VD = 1 V to 30 V;
see Figure 24 and Figure 26
2.0
0.8
6
80
100
VS = 1V to 30 V, VD = 30 V to 1V; see Figure 25
nA max
0.002
216
250
199
232
160
193
nA max
nA typ
nA max
nA typ
±10
47
1
VS = 0 V to 30 V, IS = −10 mA; see
Figure 27
VDD = 32.4 V, VSS = 0 V
VS = 0 V to 30 V, IS = −10 mA
20
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
Test Conditions/Comments
16
0.1
±0.4
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
−40°C to +85°C
130
9/40
Guaranteed by design; not subject to production test.
Rev. A | Page 6 of 19
μA typ
μA max
V min/V max
GND = 0 V, VSS = 0 V
Data Sheet
ADG5419
CONTINUOUS CURRENT PER CHANNEL, Sx OR D
Table 5.
Parameter
8-LEAD MSOP
VDD = 15 V, VSS = −15 V
VDD = 20 V, VSS = −20 V
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
8-LEAD LFCSP
VDD = 15 V, VSS = −15 V
VDD = 20 V, VSS = −20 V
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
25°C
85°C
125°C
Unit
113
118
90
116
73
76
60
74
46
47
41
46
mA maximum
mA maximum
mA maximum
mA maximum
156
163
126
160
92
95
78
93
52
53
48
53
mA maximum
mA maximum
mA maximum
mA maximum
Test Conditions/Comments
θJA = 133.1°C/W
θJA = 60.88°C/W
Rev. A | Page 7 of 19
ADG5419
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, Sx or D Pins
Continuous Current, Sx or D2
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
8-Lead MSOP (4-Layer Board)
8-Lead LFCSP
Reflow Soldering Peak
Temperature, Pb Free
Human Body Model (HBM) ESD
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or 30
mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
410 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data + 15%
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
133.1°C/W
60.88°C/W
As per JEDEC J-STD-020
8 kV
1
Overvoltages at the IN, Sx, and D pins are clamped by internal diodes. Limit
current to the maximum ratings given.
2
See Table 5.
Rev. A | Page 8 of 19
Data Sheet
ADG5419
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
GND 3
TOP VIEW
(Not to Scale)
VDD 4
D 1
7 VSS
SA 2
6 IN
GND 3
VDD 4
5 EN
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
ADG5419
TOP VIEW
(Not to Scale)
8
SB
7
VSS
6
IN
5
NC
NOTES
1. NC = NO CONNECT. NOT INTERNALLY CONNECTED.
Figure 3. 8-Lead LFCSP Pin Configuration
11370-002
8 SB
ADG5419
11370-103
D 1
SA 2
Figure 4. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
LFCSP
1
2
3
4
5
6
7
8
Pin No.
MSOP
1
2
3
4
6
7
8
5
Not applicable
Mnemonic
D
SA
GND
VDD
EN
IN
VSS
SB
NC
EPAD
Description
Drain Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or an output.
Ground (0 V) Reference.
Most Positive Power Supply Potential.
Active High Digital Input. When this pin is low, the device is disabled
and all switches are turned off. When this pin is high, the IN logic input
determines the state of the switch.
Logic Control Input.
Most Negative Power Supply Potential.
Source Terminal. This pin can be an input or an output.
No Connect. Not internally connected.
Exposed Pad. Exposed pad tied to substrate, VSS.
Table 8. LFCSP Truth Table
EN
0
1
1
1
IN
X1
0
1
Switch A
Off
On
Off
Switch B
Off
Off
On
X = don’t care.
Table 9. MSOP Truth Table
IN
0
1
Switch A
On
Off
Switch B
Off
On
Rev. A | Page 9 of 19
ADG5419
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
25
16
TA = 25°C
20
12
VDD = +11V
VSS = –11V
15
10
VDD = +13.5V
VSS = –13.5V
VDD = +15V
VSS = –15V
VDD = +16.5V
VSS = –16.5V
5
TA = 25°C
14
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
VDD = +10V
VSS = –10V
VDD = +9V
VSS = –9V
10
VDD = 32.4V
VSS = 0V
8
VDD = 39.6V
VSS = 0V
VDD = 36V
VSS = 0V
6
4
–16
–14
–12
–10
–8
–6
–4
–2
2
0
4
VS, VD (V)
6
8
10
12
14
16
18
0
11370-003
0
–18
5
10
15
20
25
30
35
40
45
VS, VD (V)
Figure 8. On Resistance as a Function of VS, VD (Single Supply)
Figure 5. On Resistance as a Function of VS, VD Dual Supply
16
0
11370-006
2
25
TA = 25°C
14
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
20
VDD = +18V
VSS = –18V
12
10
8
VDD = +22V
VSS = –22V
VDD = +20V
VSS = –20V
6
TA = +125°C
15
TA = +85°C
TA = +25°C
10
TA = –40°C
4
5
2
–15
–10
–5
0
5
10
15
20
25
VS, VD (V)
Figure 6. On Resistance as a Function of VS, VD Dual Supply)
VDD = 10.8V
VSS = 0V
VDD = 9V
VSS = 0V
25
20
15
VDD = 13.2V
VSS = 0V
10
VDD = 12V
VSS = 0V
0
5
10
15
VDD = +20V
VSS = –20V
20
VDD = 11V
VSS = 0V
TA = +125°C
15
TA = +85°C
TA = +25°C
10
TA = –40°C
5
0
0
2
4
6
8
VS, VD (V)
10
12
14
Figure 7. On Resistance as a Function of VS, VD (Single Supply)
0
–20
–15
–10
–5
0
VS, VD (V)
5
10
15
20
11370-008
5
11370-005
ON RESISTANCE (Ω)
30
VDD = 10V
VSS = 0V
–5
Figure 9. On Resistance as a Function of VS (VD) for Different Temperatures,
±15 V Dual Supply
25
TA = 25°C
–10
VS, VD (V)
ON RESISTANCE (Ω)
35
0
–15
11370-007
–20
11370-004
0
–25
VDD = +15V
VSS = –15V
Figure 10. On Resistance as a Function of VS (VD) for Different Temperatures,
±20 V Dual Supply
Rev. A | Page 10 of 19
Data Sheet
ADG5419
0.4
VDD = +20V
VSS = –20V
VBIAS = +15V/–15V
35
LEAKAGE CURRENT (nA)
20
TA = +25°C
15
TA = –40°C
10
0
ID, IS (ON) – –
–0.2
IS (OFF) – +
–0.4
5
0
2
4
6
8
10
12
VS, VD (V)
–0.6
11370-009
0
VDD = 12V
VSS = 0V
0.4
VDD = 36V
VSS = 0V
LEAKAGE CURRENT (nA)
ON RESISTANCE (Ω)
TA = +125°C
TA = +85°C
TA = +25°C
10
TA = –40°C
5
5
10
15
20
25
30
35
40
ID, IS (ON) – –
IS (OFF) + –
0
ID (OFF) – +
IS (OFF) – +
ID (OFF) + –
0
0.4
LEAKAGE CURRENT (nA)
IS (OFF) + –
ID (OFF) – +
ID, IS (ON) – –
0
IS (OFF) – +
–0.2
50
75
100
VDD = 36V
VSS = 0V
VBIAS = 1V/30V
IS (OFF) + –
0
ID (OFF) – +
ID, IS (ON) – –
–0.2
IS (OFF) – +
–0.4
ID (OFF) + –
ID (OFF) + –
0
25
50
75
TEMPERATURE (°C)
100
125
–0.6
11370-011
–0.4
125
ID, IS (ON) + +
0.2
ID, IS (ON) + +
0.2
25
Figure 15. Leakage Currents as a Function of Temperature,
12 V Single Supply
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
0.4
125
TEMPERATURE (°C)
Figure 12. On Resistance as a Function of VS (VD) for Different Temperatures,
36 V Single Supply
0.6
100
0.1
–0.2
11370-010
0
75
ID, IS (ON) + +
0.2
–0.1
VS, VD (V)
LEAKAGE CURRENT (nA)
50
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
0.3
15
25
Figure 14. Leakage Currents as a Function of Temperature,
±20 V Dual Supply
20
0
0
TEMPERATURE (°C)
Figure 11. On Resistance as a Function of VS (VD) for Different Temperatures,
12 V Single Supply
25
ID (OFF) + –
11370-013
TA = +85°C
25
IS (OFF) + –
ID (OFF) – +
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 13. Leakage Currents as a Function of Temperature, ±15 V Dual Supply
Rev. A | Page 11 of 19
Figure 16. Leakage Currents as a Function of Temperature,
36 V Single Supply
11370-014
ON RESISTANCE (Ω)
0.2
TA = +125°C
30
ID, IS (ON) + +
11370-012
40
ADG5419
0
–10
Data Sheet
0.05
TA = 25°C
VDD = +15V
VSS = –15V
TA = 25°C
RL = 1kΩ
VDD = 12V, VSS = 0V, VS = 6V p-p
VDD = 36V, VSS = 0V, VS = 18V p-p
VDD = 15V, VSS = –15V, VS = 15V p-p
VDD = 20V, VSS = –20V, VS = 20V p-p
0.04
–30
–40
THD + N (%)
OFF ISOLATION (dB)
–20
–50
–60
0.03
0.02
–70
–80
0.01
100k
1M
10M
100M
1G
FREQUENCY (Hz)
0
11370-015
10k
0
5
0
0
TA = 25°C
VDD = +15V
VSS = –15V
20
TA = 25°C
VDD = +15V
VSS = –15V
–0.5
–1.0
INSERTION LOSS (dB)
CROSSTALK (dB)
15
Figure 20. THD + N vs. Frequency
Figure 17. Off Isolation vs. Frequency
–20
10
FREQUENCY (kHz)
11370-018
–90
–100
1k
–40
–60
–80
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–100
100k
1M
10M
FREQUENCY (Hz)
100M
1G
–5.0
1k
11370-016
–120
10k
10k
100k
100M
1G
Figure 21. Bandwidth
500
300
VDD
VDD
VDD
VDD
= 15V, VSS = –15V
= 20V, VSS = –20V
= 12V, VSS = 0V
= 36V, VSS = 0V
450
400
350
TIME (ns)
200
150
100
300
250
200
VDD
VDD
VDD
VDD
150
100
50
= 12V, VSS = 0V
= 36V, VSS = 0V
= 15V, VSS = –15V
= 20V, VSS = –20V
0
–20
–10
0
10
20
30
VS (V)
40
0
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 22. tTRANSITION Times vs. Temperature
Figure 19. Charge Injection vs. Source Voltage
Rev. A | Page 12 of 19
120
11370-020
50
11370-017
CHARGE INJECTION (pC)
10M
FREQUENCY (Hz)
Figure 18. Crosstalk vs. Frequency
250
1M
11370-019
–4.5
Data Sheet
0
–20
ADG5419
TA = 25°C
VDD = +15V
VSS = –15V
NO DECOUPLING
CAPACITORS
ACPSRR (dB)
–40
–60
–80
–120
1k
10k
100k
1M
FREQUENCY (Hz)
10M
11370-123
DECOUPLING
CAPACITORS
–100
Figure 23. ACPSRR vs. Frequency
Rev. A | Page 13 of 19
ADG5419
Data Sheet
TEST CIRCUITS
D
A
SB
A
V
ID (ON)
Sx
D
IS (OFF)
IDS
Figure 24. Channel On and Source Off Leakage (MSOP Only)
11370-022
RON = V/IDS
VS
11370-021
VD
VS
Figure 27. On Resistance
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VOUT
A
RL
50Ω
D
SB
SA
D
ID (OFF)
11370-121
VD
VS
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VDD
VSS
0.1µF
0.1µF
VDD
IN
NC
SB
D
VOUT
VS
Figure 28. Channel-to-Channel Crosstalk
Figure 25. Off Leakage (LFCSP Only)
SA
R
50Ω
IN
VS
A
SB
A
VSS
NETWORK
ANALYZER
VSS
NC
SB
SA
50Ω
50Ω
VS
ID (ON)
D
A
VIN
RL
50Ω
VD
11370-122
GND
VS
11370-023
IS (OFF)
VDD
SA
OFF ISOLATION = 20 log
VOUT
VS
Figure 29. Off Isolation
Figure 26. On Leakage (LFCSP Only)
Rev. A | Page 14 of 19
VOUT
11370-024
SA
NC
Data Sheet
ADG5419
VDD
VSS
0.1µF
0.1µF
VDD
AUDIO PRECISION
VDD
VSS
RS
Sx
VS
V p-p
IN
D
VIN
SB
RL
50Ω
GND
INSERTION LOSS = 20 log
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
0.1µF
VIN (SB = VS)
50%
50%
VIN (SA = VS)
50%
50%
VSS
SA*
D
SB*
VOUT
RL
300Ω
IN
CL
35pF
VS
0.9VS
VOUT
0.1VS
0V
GND
VIN
VOUT
Figure 31. Bandwidth
VSS
VDD
VS
50Ω
VIN
11370-025
VDD
50Ω
VS
Figure 30. THD + Noise
0.1µF
NC
D
VOUT
RL
1kΩ
GND
SA
IN
NETWORK
ANALYZER
VSS
tTRANSITION
tTRANSITION
*ALTERNATIVELY, SB CAN BE CONNECTED TO VS WITH SA CONNECTED TO GROUND.
11370-127
0.1µF
Figure 32. Transition Time, tTRANSITION
3V
ENABLE
DRIVE
(VEN)
50%
VDD
VSS
VDD
VSS
IN
50%
SA
VS
SB
0V
ADG5419
OUTPUT
(VOUT)
0V
tON (EN)
tOFF (EN)
0.9VS
D
EN
VEN
50Ω
0.1VS
Figure 33. Enable Delay, tON (EN), tOFF (EN) (LFCSP Only)
Rev. A | Page 15 of 19
GND
VOUT
300Ω
35pF
11370-132
VS
11370-026
VDD
VSS
0.1µF
ADG5419
Data Sheet
0.1µF
VS
VDD
VSS
VDD
VSS
SB
0.1µF
VIN
D
VOUT
SA
RL
300Ω
IN
VOUT
CL
35pF
80%
tD
tD
GND
11370-028
VIN
Figure 34. Break-Before-Make Delay, tD
VDD
VSS
SB
D
NC
SA
CL
1nF
IN
VIN
VIN (NORMALLY
CLOSED SWITCH)
VSS
VDD
VS
0.1µF
GND
VOUT
ON
OFF
VIN (NORMALLY
OPEN SWITCH)
VOUT
∆VOUT
Figure 35. Charge Injection
Rev. A | Page 16 of 19
QINJ = CL × ∆VOUT
11370-029
0.1µF
Data Sheet
ADG5419
TERMINOLOGY
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
CIN
CIN represents digital input capacitance.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
tON (EN)
tON represents the delay time between the 50% and 90% points
of the digital input and switch on condition. See Figure 33.
RON
RON is the ohmic resistance between Terminal D and
Terminal S.
tOFF (EN)
tOFF represents the delay time between the 50% and 90% points
of the digital input and switch off condition. See Figure 33.
ΔRON
ΔRON represents the difference between the RON of any two
channels.
RFLAT (ON)
The difference between the maximum and minimum value of
on resistance as measured over the specified analog signal range
is represented by RFLAT (ON).
IS (Off)
IS (Off) is the source leakage current with the switch off.
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
tD
tD represents the off time measured between the 80% point of
both switches when switching from one address state to another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated by
3 dB, from its dc level.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
Total Harmonic Distortion + Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR measures the ability of a device to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the
amplitude of signal on the output to the amplitude of the
modulation is the ACPSRR. See Figure 23.
Rev. A | Page 17 of 19
ADG5419
Data Sheet
APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, aerospace, and
other harsh environments that are prone to latch-up, which is an
undesirable high current state that can lead to device failure and
persists until the power supply is turned off. The ADG5419
high voltage switch allows single-supply operation from 9 V
to 40 V and dual-supply operation from ±9 V to ±22 V. The
ADG5419 (as well as other select devices within this family)
achieves an 8 kV human body model ESD rating, which provides
a robust solution, eliminating the need for separate protection
circuitry designs in some applications.
TRENCH ISOLATION
NMOS
PMOS
P-WELL
N-WELL
TRENCH
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. The two transistors form a
silicon-controlled rectifier (SCR) type circuit, causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up immune switch.
Rev. A | Page 18 of 19
HANDLE WAFER
Figure 36. Trench Isolation
11370-030
BURIED OXIDE LAYER
In the ADG5419, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction-isolated switches, are eliminated, and the result is a
completely latch-up immune switch.
Data Sheet
ADG5419
OUTLINE DIMENSIONS
1.75
1.65
1.50
2.00 BSC
5
3.00 BSC
8
1.90
1.80
1.65
EXPOSED
PAD
0.20 MIN
4
INDEX
AREA
0.50
0.40
0.30
TOP VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.05 MAX
0.02 NOM
0.30
0.25
0.20
0.50
081806-A
SEATING
PLANE
BOTTOM VIEW
0.15 REF
SIDE VIEW
PIN 1
INDICATOR
1
Figure 37. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
2 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-4)
Dimensions shown in millimeters
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
Figure 38. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG5419BCPZ-RL7
ADG5419BRMZ
ADG5419BRMZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
Z = RoHS Compliant Part.
©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11370-0-3/15(A)
Rev. A | Page 19 of 19
Package Option
CP-8-4
RM-8
RM-8
Branding
BL
S48
S48