ON MC14012BDR2G B−suffix series cmos gate Datasheet

MC14012B
B−Suffix Series CMOS Gates
The B Series logic gates are constructed with P−Channel and
N−Channel enhancement mode devices in a single monolithic
structure (Complementary MOS). Their primary use is where low
power dissipation and/or high noise immunity is desired.
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Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
•
•
•
MARKING
DIAGRAMS
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
Pin−for−Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
Pb−Free Packages are Available
14
PDIP−14
P SUFFIX
CASE 646
MC14012BCP
AWLYYWWG
1
14
SOIC−14
D SUFFIX
CASE 751A
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
VDD
Vin, Vout
Iin, Iout
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Value
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
1
14012BG
AWLYWW
1
14
SOEIAJ−14
F SUFFIX
CASE 965
MC14012B
ALYWG
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
MC14012B/D
MC14012B
MC14012B
Dual 4−Input NAND Gate
OUTA
1
14
VDD
IN 1A
2
13
OUTB
IN 2A
3
12
IN 4B
IN 3A
4
11
IN 3B
IN 4A
5
10
IN 2B
NC
6
9
IN 1B
VSS
7
8
NC
2
3
4
5
9
10
11
12
1
13
NC = 6, 8
VDD = PIN 14
VSS = PIN 7
NC = NO CONNECTION
Figure 1. Pin Assignment
Figure 2. Logic Diagram
ORDERING INFORMATION
Device
Package
MC14012BCP
PDIP−14
MC14012BCPG
PDIP−14
(Pb−Free)
MC14012BD
SOIC−14
MC14012BDG
SOIC−14
(Pb−Free)
MC14012BDR2
SOIC−14
MC14012BDR2G
SOIC−14
(Pb−Free)
MC14012BFEL
SOEIAJ−14
MC14012BFELG
SOEIAJ−14
(Pb−Free)
Shipping †
25 Units / Rail
55 Units / Rail
2500 Units / Tape & Reel
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MC14012B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
− 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
“1” Level
VIH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
± 0.1
−
± 0.00001
± 0.1
−
± 1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Source
Sink
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Gate, CL = 50 pF)
IOH
Vdc
Vdc
mAdc
IT = (0.3 mA/kHz) f + IDD/N
IT = (0.6 mA/kHz) f + IDD/N
IT = (0.9 mA/kHz) f + IDD/N
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised
gates per package.
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3
MC14012B
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise Time
tTLH = (1.35 ns/pF) CL + 33 ns
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/PF) CL + 20 ns
tTLH
Output Fall Time
tTHL = (1.35 ns/pF) CL + 33 ns
tTHL = (0.60 ns/pF) CL + 20 ns
tTHL = (0.40 ns/pF) CL + 20 ns
tTHL
Propagation Delay Time
tPLH, tPHL = (0.90 ns/pF) CL + 115 ns
tPLH, tPHL = (0.36 ns/pF) CL + 47 ns
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
VDD
Vdc
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
160
65
50
300
130
100
Unit
ns
ns
tPLH, tPHL
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
14
PULSE
GENERATOR
20 ns
VDD
20 ns
90%
50%
10%
INPUT
INPUT
OUTPUT
tPHL
CL
*
7
OUTPUT
INVERTING
*All unused inputs of AND, NAND gates must be connected to VDD.
All unused inputs of OR, NOR gates must be connected to VSS.
tTHL
tPLH
Figure 3. Switching Time Test Circuit and Waveforms
VDD
VDD
2, 9
*
3, 10
VSS
4, 11
5, 12
1, 13
SAME AS
ABOVE
7
*Inverter omitted
VSS
Figure 4. Circuit Schematic − One of Two Gates Shown
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4
VOH
tTLH
tPHL
tTLH
14
0V
tPLH
90%
50%
10%
OUTPUT
NON−INVERTING
VSS
VDD
90%
50%
10%
tTHL
VOL
VOH
VOL
MC14012B
TYPICAL B−SERIES GATE CHARACTERISTICS
N−CHANNEL DRAIN CURRENT (SINK)
P−CHANNEL DRAIN CURRENT (SOURCE)
−10
5.0
ID , DRAIN CURRENT (mA)
ID , DRAIN CURRENT (mA)
−9.0
4.0
TA = −55°C
3.0
−40°C
+85°C +25°C
2.0
+125°C
1.0
−8.0
TA = −55°C
−7.0
−40°C
−6.0
−5.0
+25°C
+85°C
−4.0
−3.0
+125°C
−2.0
−1.0
0
0
1.0
2.0
3.0
4.0
0
5.0
0
VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)
−5.0
−45
TA = −55°C
16
14
−40°C
12
+25°C
+85°C
10
ID , DRAIN CURRENT (mA)
ID , DRAIN CURRENT (mA)
−4.0
−50
18
+125°C
8.0
6.0
−40
−35
TA = −55°C
−30
−25
+ 25°C
−20
+125°C
4.0
−10
2.0
−5.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
0
0
10
−1.0 −2.0 −3.0 −4.0 −5.0 −6.0 −7.0 −8.0 −9.0 −10
VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)
Figure 7. VGS = 10 Vdc
Figure 8. VGS = − 10 Vdc
50
− 100
45
− 90
ID , DRAIN CURRENT (mA)
40
TA = −55°C
35
30
−40°C
25
+25°C
20
+85°C
+125°C
15
−40°C
+85°C
−15
VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)
ID , DRAIN CURRENT (mA)
−3.0
Figure 6. VGS = − 5.0 Vdc
20
10
5.0
0
−2.0
VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)
Figure 5. VGS = 5.0 Vdc
0
−1.0
− 80
− 70
− 60
TA = −55°C
− 50
+25°C
− 40
−40°C
+85°C
− 30
+125°C
− 20
− 10
0
2.0
4.0
6.0
8.0
10
12
14
16
18
0
20
0
VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)
Figure 9. VGS = 15 Vdc
−2.0 −4.0 −6.0 −8.0 −10 −12 −14 −16 −18 −20
VDS, DRAIN−TO−SOURCE VOLTAGE (Vdc)
Figure 10. VGS = − 15 Vdc
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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5
MC14012B
V out , OUTPUT VOLTAGE (Vdc)
V out , OUTPUT VOLTAGE (Vdc)
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
5.0
4.0
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
3.0
2.0
1.0
0
0
1.0
8.0
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
6.0
4.0
2.0
0
2.0
3.0
4.0
5.0
Vin, INPUT VOLTAGE (Vdc)
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
10
2.0
0
4.0
6.0
8.0
10
Vin, INPUT VOLTAGE (Vdc)
Figure 11. VDD = 5.0 Vdc
DC NOISE MARGIN
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
16
V out , OUTPUT VOLTAGE (Vdc)
Figure 12. VDD = 10 Vdc
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values VIL and VIH for the output(s) to
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
14
12
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, A
10
8.0
6.0
4.0
2.0
0
0
2.0
4.0
6.0
8.0
10
Vin, INPUT VOLTAGE (Vdc)
Figure 13. VDD = 15 Vdc
VDD
Vout
Vout
VO
VO
VO
VO
VDD
VDD
VDD
0
Vin
0
VIL
VIH
Vin
VIL
VIH
VSS = 0 VOLTS DC
(a) Inverting Function
(b) Non−Inverting Function
Figure 14. DC Noise Immunity
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6
MC14012B
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
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7
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
MC14012B
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
8
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC14012B
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
M_
L
7
1
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
1.42
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.056
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC14012B/D
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