Infineon HYS72D16000GR-7-A Registered ddr sdram-module Datasheet

D a t a S h e e t , Rev. 1.04, J a n . 2 0 0 4
HYS72D16000GR-[7/8]-A
HYS72D32001GR-[7/8]-A
Registered DDR SDRAM-Modules
DDR SDRAM
Memory Products
N e v e r
s t o p
t h i n k i n g .
Edition 2004-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S h e e t , Rev. 1.04, J a n . 2 0 0 4
HYS72D16000GR-[7/8]-A
HYS72D32001GR-[7/8]-A
Registered DDR SDRAM-Modules
DDR SDRAM
Memory Products
N e v e r
s t o p
t h i n k i n g .
HYS72D16000GR-[7/8]-A HYS72D32001GR-[7/8]-A
Revision History:
Rev. 1.04
2004-01
Previous Version:
Rev. 1.03
2003-10
Page
Subjects (major changes since last revision)
Rev. 1.04
16
Editorial and table-layout changes
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
Template: mp_a4_v2.2_2003-10-07.fm
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Table of Contents
Page
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data Sheet
5
13
13
17
17
Rev. 1.04, 2004-01
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Overview
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
184-pin Registered 8 Byte Dual-In-Line DDR SDRAM Module for PC and Server main memory applications
One bank 16M × 72 and 32M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single +2.5 V (± 0.2 V) power
supply
Built with 128 Mbit DDR SDRAMs in 66-Lead TSOPII package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Re-drive for all input signals using register and PLL devices.
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor:
133.35 mm (nom.) × 43.18 mm (nom.) × 4.00 mm (max.)
(6,80 mm max. with stacked components)
JEDEC standard reference layout:
Raw Cards A, B and C
Gold plated contacts
Table 1
Performance -8/-7
Part Number Speed Code
Speed Grade
max. Clock Frequency
–7
Unit
Component
DDR266A
DDR200
—
Module
PC2100-2033
PC1600-2022
—
143
125
MHz
133
100
MHz
@CL2.5
@CL2
1.2
–8
fCK2.5
fCK2
Description
The HYS 72D××0×0GR are industry standard 184-pin 8 byte Dual in-line Memory Modules (DIMMs) organized as
16M × 72 (128 MB) and 32M × 72 (256 MB). The memory array is designed with Double Data Rate Synchronous
DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices
and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the
SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Overview
Table 2
Ordering Information
Type
Compliance Code
Description
SDRAM Technology
HYS72D16000GR-7-A
PC2100R-20330-A1
one bank 128 MB Reg. DIMM 128 Mbit (×8)
HYS72D32001GR-7-A
PC2100R-20330-B1
one bank 256 MB Reg. DIMM 128 Mbit (×4)
HYS72D16000GR-8-A
PC1600R-20220-A1
one bank 128 MB Reg. DIMM 128 Mbit (×8)
HYS72D32001GR-8-A
PC1600R-20220-B1
one bank 256 MB Reg. DIMM 128 Mbit (×4)
PC2100 (CL=2)
PC1600 (CL=2)
Note: All part numbers end with a place code (not shown), designating the silicon-die revision. Reference
information available on request. Example: HYS72D16000GR-8-A, indicating Rev. A die are used for
SDRAM components The Compliance Code is printed on the module labels and describes the speed sort
for example “PC2100R”, the latencies (for example “20330” means CAS latency = 2, tRCD latency = 3 and
tRP latency = 3 ) and the Raw Card used for this module.
Data Sheet
7
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 3
Pin Definitions and Functions
Symbol
Type
Function
A0 – A11
Input
Address Inputs
BA0, BA1
Input
Rank Selects
DQ0 – DQ63
Input/Output
Data Input/Output
CB0 – CB7
Input/Output
Check Bits (×72 organization only)
RAS
Input
Row Address Strobe
CAS
Input
Column Address Strobe
WE
Input
Read/Write Input
CKE0, CKE1
Input
Clock Enable
DQS0 – DQS8
Input/Output
SDRAM low data strobes
CK0, CK0
Input
Differential Clock Input
DM0 – DM8
Input
SDRAM low data mask
DQS9 – DQS17
Input/Output
high data strobes
CS0, CS1
Input
Chip Selects
VDD
VSS
VDDQ
VDDID
VDDSPD
VREF
Supply
Power (+2.5 V)
Supply
Ground
Supply
I/O Driver power supply
Output
VDD Indentification flag
Supply
EEPROM power supply
Supply
I/O reference supply
SCL
Input
Serial bus clock
SDA
Output
Serial bus data line
SA0 – SA2
Input
slave address select
NC
Input
no connect
DU
Input
don’t use
RESET
Input
Reset pin (forces register inputs low) *)
*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at the
end of this datasheet
Table 4
Address Format
Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of
row/rank/
columns
bits
Refresh Period Interval
128 MB
16M × 72
1
16M × 8
9
12/2/10
4K
64 ms
15.6 µs
256 MB
32M × 72
1
32M × 4
18
12/2/11
4K
64 ms
15.6 µs
Density
Data Sheet
8
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Pin Configuration
Table 5
PIN#
Pin Configuration
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
VREF
48
A0
94
DQ4
141
A10
2
DQ0
49
CB2
95
DQ5
142
CB6
3
VSS
50
VSS
96
VDDQ
143
VDDQ
4
DQ1
51
CB3
97
DM0/DQS9
144
CB7
5
DQS0
52
BA1
98
DQ6
6
DQ2
99
DQ7
145
VSS
7
VDD
53
DQ32
100
VSS
146
DQ36
8
DQ3
54
VDDQ
101
NC
147
DQ37
9
NC
55
DQ33
102
NC
148
VDD
10
RESET
56
DQS4
103
NC
149
DM4/DQS13
11
VSS
57
DQ34
104
VDDQ
150
DQ38
12
DQ8
58
VSS
105
DQ12
151
DQ39
13
DQ9
59
BA0
106
DQ13
152
VSS
14
DQS1
60
DQ35
107
DM1/DQS10
153
DQ44
15
VDDQ
61
DQ40
108
VDD
154
RAS
16
DU
62
VDDQ
109
DQ14
155
DQ45
17
DU
63
WE
110
DQ15
156
VDDQ
18
VSS
64
DQ41
111
CKE1
157
CS0
19
DQ10
65
CAS
112
VDDQ
158
CS1
20
DQ11
66
VSS
113
NC
159
DM5/DQS14
21
CKE0
67
DQS5
114
DQ20
160
VSS
22
VDDQ
68
DQ42
115
NC/A12
161
DQ46
KEY
KEY
A12 is used for
256 Mbit and
512 Mbit based
modules only
23
DQ16
69
DQ43
116
VSS
162
DQ47
24
DQ17
70
VDD
117
DQ21
163
NC
25
DQS2
71
NC
118
A11
164
VDDQ
26
VSS
72
DQ48
119
DM2/DQS11
165
DQ52
27
A9
73
DQ49
120
VDD
166
DQ53
28
DQ18
74
VSS
121
DQ22
167
NC
29
A7
75
DU
122
A8
168
VDD
30
VDDQ
76
DU
123
DQ23
169
DM6/DQS15
31
DQ19
77
VDDQ
124
VSS
170
DQ54
32
A5
78
DQS6
125
A6
171
DQ55
33
DQ24
79
DQ50
126
DQ28
172
VDDQ
34
VSS
80
DQ51
127
DQ29
173
NC
35
DQ25
81
128
VDDQ
174
DQ60
36
DQS3
82
VSS
VDDID
129
DM3/DQS12
175
DQ61
37
A4
83
DQ56
130
A3
176
VSS
38
VDD
84
DQ57
131
DQ30
177
DM7/DQS16
Data Sheet
9
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Pin Configuration
Table 5
PIN#
Pin Configuration (cont’d)
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
39
DQ26
85
VDD
132
VSS
178
DQ62
40
DQ27
86
DQS7
133
DQ31
179
DQ63
41
A2
87
DQ58
134
CB4
180
VDDQ
42
VSS
88
DQ59
135
CB5
181
SA0
43
A1
89
VSS
136
VDDQ
182
SA1
44
CB0
90
NC
137
CK0
183
SA2
45
CB1
91
SDA
138
CK0
184
46
VDD
92
SCL
139
VSS
185
VDDSPD
VSS
47
DQS8
93
VSS
140
DM8/DQS17
–
–
Data Sheet
10
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Pin Configuration
RS0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D2
DQS8
DM8/DQS17
CS0
RAS
CAS
CKE0
WE
PCK
PCK
Figure 1
Data Sheet
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D5
CS
DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D3
CS DQS
D7
VDDSPD
R
E
G
I
S
T
E
R
A0-A12
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D4
Serial PD
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
BA0-BA1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
CS
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D0 - D8
DQS
SDA
D8
SCL
A0
A1
A2
RS0 -> CS : SDRAMs D0-D8
VDD, V DDQ
D0 - D8
VREF
D0 - D8
V SS
SA0 SA1 SA2
V DDID
D0 - D8
Strap: see Note 4
Notes:
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
RA0-RA12 -> A0-A12: SDRAMs D0 - D8
RRAS -> RAS : SDRAMs D0 - D8
RCAS -> CAS : SDRAMs D0 - D8
RCKE0 -> CKE: SDRAMs D0 - D8
RWE -> WE : SDRAMs D0 - D8
RESET
EEPROM
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
5. SDRAM placement alternates between the back
and front of the DIMM.
Block Diagram One Rank 16 MB × 72 DDR SDRAM DIMM Modules HYS72D16000GR-[7/8]-A
using ×8 organized SDRAMs on RAW Card Version A
11
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Pin Configuration
VSS
RS0B
RS0A
DQS0
DM0/DQS9
DQS
CS
DQ0
DQ1
DQ2
DQ3
I/O 0
I/O 1
I/O 2
I/O 3
DQ8
DQ9
DQ10
DQ11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ16
DQ17
DQ18
DQ19
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ24
DQ25
DQ26
DQ27
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ32
DQ33
DQ34
DQ35
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ40
DQ41
DQ42
DQ43
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ48
DQ49
DQ50
DQ51
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
CS
DM
DQ4
DQ5
DQ6
DQ7
D0
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D9
DM1/DQS10
DQS1
CS
DM
DQ12
DQ13
DQ14
DQ15
D1
DQS2
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D10
DM2/DQS11
DQS3
DM
DQ20
DQ21
DQ22
DQ23
D2
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D11
DM3/DQS12
DM
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DQS6
DM
DM5/DQS14
DQ44
DQ45
DQ46
DQ47
D5
DM
DM6/DQS15
DQ52
DQ53
DQ54
DQ55
D6
DQS7
D12
DQS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CS0
BA0-BA1
A0-A11,A12
RAS
CAS
CKE0
WE
PCK
PCK
Figure 2
Data Sheet
R
E
G
I
S
T
E
R
DQ60
DQ61
DQ62
DQ63
D7
DQS
CB0
CB1
CB2
CB3
DM
CS
DM
DM8/DQS17
D8
CB4
CB5
CB6
CB7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
V DDSPD
EEPROM
VDD, VDDQ
D0 - D17
VREF
D0 - D17
V SS
CS
DM
D0 - D17
V DDID
Strap: see Note 4
D14
Serial PD
CS
DQS
I/O 0
I/O 1
D15
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
D13
DM7/DQS16
DQ56
DQ57
DQ58
DQ59
DQS8
DM4/DQS13
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D17
A0
A1
A2
SA0 SA1 SA2
DM
Notes:
D16
CS
SDA
SCL
DM
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
RS 0 -> CS : SDRAMs D0-D17
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
RA0-RA11,RA12 -> A0-A11,A12: SDRAMs D0 - D17
RRAS -> RAS : SDRAMs D0 - D17
RCAS -> CAS : SDRAMs D0 - D17
RCKE0A -> CKE: SDRAMs D0 - D8
RCKEB -> CKE: SDRAMs D9 - D17
CK0, CK 0 --------- PLL*
RWE -> WE : SDRAMs D0 - D17
*
Wire
per
Clock
Loading Table/Wiring Diagrams
RESET
Block Diagram One Rank 32 MB × 72 DDR SDRAM DIMM Modules HYS72D32001GR-[7/8]-A
using ×4 organized SDRAMs on RAW Card Version B
12
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 6
Absolute Maximum Ratings
Parameter
Symbol
Voltage on I/O pins relative to VSS
VIN, VOUT
Values
min.
typ.
max.
Unit Note/ Test
Condition
–0.5
–
VDDQ +
V
–
0.5
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
–1
–
+3.6
V
–
–1
–
+3.6
V
–
–1
–
+3.6
V
–
0
–
+70
°C
–
-55
–
+150
°C
–
–
1
–
W
–
–
50
–
mA
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Data Sheet
13
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Electrical Characteristics
Table 7
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
VDD
Output Supply Voltage
VDDQ
Supply Voltage, I/O Supply VSS,
Voltage
VSSQ
Input Reference Voltage
VREF
I/O Termination Voltage
VTT
Device Supply Voltage
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.3
2.5
2.7
V
2)
0
V
—
0
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V
3)
VREF – 0.04
VREF + 0.04 V
4)
Input High (Logic1) Voltage VIH(DC)
VREF + 0.15
7)
Input Low (Logic0) Voltage VIL(DC)
–0.3
Input Voltage Level,
CK and CK Inputs
VIN(DC)
–0.3
VDDQ + 0.3 V
VREF – 0.15 V
VDDQ + 0.3 V
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
VDDQ + 0.6
V
7)5)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
—
6)
Input Leakage Current
II
–2
2
µA
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 7)8)
Output Leakage Current
IOZ
–5
5
µA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ 7)
Output High Current,
Normal Strength Driver
IOH
—
–16.2
mA
VOUT = 1.95 V 7)
Output Low
Current, Normal Strength
Driver
IOL
16.2
—
mA
VOUT = 0.35 V 7)
(System)
7)
7)
1) 0 °C ≤ TA ≤ 70 °C
2) Under all conditions, VDDQ must be less than or equal to VDD.
3) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
5) VID is the magnitude of the difference between the input level on CK and the input level on CK.
6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
7) Inputs are not recognized as valid until VREF stabilizes.
8) Values are shown per component
Data Sheet
14
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Electrical Characteristics
Table 8
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Data Sheet
15
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Electrical Characteristics
HYS72D16000GR-8-A
Note 1)2)
HYS72D16000GR-8-A
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
Unit
HYS72D32001GR-7-A
Symbol
IDD Specification and Conditions
HYS72D16000GR-7-A
Part Number & Organization
Table 9
128MB
256MB
128MB
256MB
x72
x72
x72
x72
1 Rank
1 Rank
1 Rank
1 Rank
–7
–7
–8
–8
max.
max.
max.
max.
810
1620
765
1530
mA
3)
990
1980
900
1800
mA
3)4)
45
90
40.5
81
mA
5)
405
810
315
630
mA
5)
405
810
315
630
mA
5)
135
270
135
270
mA
5)
405
810
315
630
mA
5)
990
1980
810
1620
mA
3)4)
990
1980
855
1710
mA
3)
1710
3420
1620
3240
mA
3)
22.5
45
22.5
45
mA
5)
2520
5040
2430
4860
mA
3)4)
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
16
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Electrical Characteristics
3.2
Current Specification and Conditions
3.3
AC Characteristics
Table 10
AC Timing - Absolute Specifications –8/–7
Parameter
Symbol
–8
–7
DDR200
DDR266A
Unit Note/
Test Condition 1)
Min.
Max.
Min.
Max.
tAC
tDQSCK
tCH
tCL
tHP
tCK2.5
tCK2
tCK1.5
tDH
tDS
tIPW
–0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)
–0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)
0.45
0.55
0.45
0.55
2)3)4)5)
0.45
0.55
0.45
0.55
tCK
tCK
ns
2)3)4)5)
DQ and DM input pulse width (each
input)
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
min. (tCL, tCH)
min. (tCL, tCH)
2)3)4)5)
8
12
7
12
ns
CL = 2.5 2)3)4)5)
10
12
7.5
12
ns
CL = 2.0 2)3)4)5)
10
12
—
—
ns
CL = 1.5 2)3)4)5)
0.6
—
0.5
—
ns
2)3)4)5)
0.6
—
0.5
—
ns
2)3)4)5)
2.5
—
2.2
—
ns
2)3)4)5)6)
tDIPW
2.0
—
1.75
—
ns
2)3)4)5)6)
Data-out high-impedance time from
CK/CK
tHZ
–0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)7)
Data-out low-impedance time from
CK/CK
tLZ
–0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)7)
Write command to 1st DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
tCK
2)3)4)5)
DQS-DQ skew (DQS and associated
DQ signals)
tDQSQ
—
+0.6
—
+0.5
ns
2)3)4)5)
Data hold skew factor
tQHS
tQH
—
1.0
—
0.75
ns
2)3)4)5)
tHP –
tQHS
—
tHP –
tQHS
—
ns
2)3)4)5)
0.35
—
0.35
—
tCK
2)3)4)5)
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
DQ/DQS output hold time
DQS input low (high) pulse width (write tDQSL,H
cycle)
DQS falling edge to CK setup time
(write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time from CK
(write cycle)
tDSH
0.2
—
0.2
—
tCK
2)3)4)5)
2
—
2
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)8)
0.40
0.60
0.40
0.60
2)3)4)5)9)
0.25
—
0.25
—
tCK
tCK
Mode register set command cycle time tMRD
Write preamble setup time
Write postamble
Write preamble
Data Sheet
tWPRES
tWPST
tWPRE
17
2)3)4)5)
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Electrical Characteristics
Table 10
AC Timing - Absolute Specifications –8/–7
Parameter
Address and control input setup time
Symbol
tIS
–8
–7
DDR200
DDR266A
Min.
Max.
Min.
Max.
1.1
—
0.9
—
Unit Note/
Test Condition 1)
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
1.1
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
tRPRE
tRPRE1.5
Read preamble setup time
tRPRES
Read postamble
tRPST
Active to Precharge command
tRAS
Active to Active/Auto-refresh command tRC
Read preamble
CL > 1.5 2)3)4)5)
NA
tCK
tCK
—
NA
ns
2)3)4)5)12)
0.40
0.60
0.40
0.60
tCK
2)3)4)5)
50
120E+3
45
120E+3 ns
2)3)4)5)
70
—
65
—
ns
2)3)4)5)
0.9
1.1
0.9
0.9
1.1
1.5
1.1
CL = 1.5 2)3)4)5)11)
period
Auto-refresh to Active/Auto-refresh
command period
tRFC
80
—
75
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
tRP
tRAP
tRRD
20
—
20
—
ns
2)3)4)5)
20
—
20
—
ns
2)3)4)5)
20
—
20
—
ns
2)3)4)5)
15
—
15
—
ns
2)3)4)5)
tWR
tDAL
15
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)13)
CL > 1.5 2)3)4)5)
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
tWTR
tWTR1.5
Exit self-refresh to non-read command tXSNR
Exit self-refresh to read command
tXSRD
Average Periodic Refresh Interval
tREFI
Internal write to read command delay
(twr/tCK) + (trp/tCK)
1
—
1
—
2
—
—
—
tCK
tCK
80
—
75
—
ns
2)3)4)5)
200
—
200
—
tCK
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)14)
CL = 1.5 2)3)4)5)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns for DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
Data Sheet
18
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Electrical Characteristics
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12) tRPRES is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
19
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
SPD Contents
4
SPD Contents
Table 11
SPD Codes
Byte#
Description
128MB
x72
1rank
–7
128MB
x72
1rank
–8
256MB
x72
1rank
–7
256MB
x72
1rank
–8
HEX.
HEX.
HEX.
HEX.
0
Number of SPD Bytes
128
80
80
80
80
1
Total Bytes in Serial PD
256
08
08
08
08
2
Memory Type
DDR-SDRAM
07
07
07
07
3
Number of Row Addresses
12
0C
0C
0C
0C
4
Number of Column Addresses
10/11
0A
0A
0B
0B
5
Number of DIMM Banks
1
01
01
01
01
6
Module Data Width
×72
48
48
48
48
7
Module Data Width (cont’d)
0
00
00
00
00
8
Module Interface Levels
SSTL_2.5
04
04
04
04
9
SDRAM Cycle Time at CL = 2.5 7 ns/8 ns
70
80
70
80
10
Access Time from Clock at
CL = 2.5
0.75 ns/0.8 ns
75
80
75
80
11
DIMM config
ECC
02
02
02
02
12
Refresh Rate/Type
Self-Refresh 15.6 ms
80
80
80
80
13
SDRAM Width, Primary
×8/×4
08
08
04
04
14
Error Checking SDRAM Data
Witdh
na
08
08
04
04
15
Minimum Clock Delay for Back- tCCD = 1 CLK
to-Back Random Column
Address
01
01
01
01
16
Burst Length Supported
2, 4 & 8
0E
0E
0E
0E
17
Number of SDRAM Banks
4
04
04
04
04
18
Supported CAS Latencies
CAS latency = 2 & 2.5
0C
0C
0C
0C
19
CS Latencies
CS latency = 0
01
01
01
01
20
WE Latencies
Write latency = 1
02
02
02
02
21
SDRAM DIMM Module
Attributes
registered
26
26
26
26
22
SDRAM Device Attributes:
General
Concurrent Auto
Precharge
C0
C0
C0
C0
23
Min. Clock Cycle Time at CAS
Latency = 2
7.5 ns/10 ns
75
A0
75
A0
24
Access Time from Clock for
CL = 2
0.75 ns/0.8 ns
75
80
75
80
25
Minimum Clock Cycle Time for
CL = 1.5
not supported
00
00
00
00
26
Access Time from Clock at
CL = 1.5
not supported
00
00
00
00
Data Sheet
20
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
SPD Contents
Table 11
Byte#
SPD Codes (cont’d)
Description
128MB
x72
1rank
–7
128MB
x72
1rank
–8
256MB
x72
1rank
–7
256MB
x72
1rank
–8
HEX.
HEX.
HEX.
HEX.
27
Minimum Row Precharge Time
20 ns
50
50
50
50
28
Minimum Row Act. to Row Act.
Delay tRRD
15 ns
3C
3C
3C
3C
29
Minimum RAS to CAS Delay tRCD 20 ns
50
50
50
50
30
Minimum RAS Pulse Width tRAS 45 ns/50 ns
2D
32
2D
32
31
Module Bank Density (per Bank) 128 MByte/256 Mbyte
20
20
40
40
32
Addr. and Command Setup Time 0.9 ns/1.1 ns
90
B0
90
B0
33
Addr. and Command Hold Time 0.9 ns/1.1 ns
90
B0
90
B0
34
Data Input Setup Time
0.5 ns/0.6 ns
50
60
50
60
35
Data Input Hold Time
0.5 ns/0.6 ns
50
60
50
60
36 to 40
Superset Information
–
00
00
00
00
41
Minimum Core Cycle Time tRC
65 ns/70 ns
41
46
41
46
42
Min. Auto Refresh Cmd Cycle 75 ns/80 ns
Time tFRC
4B
50
4B
50
43
Maximum Clock Cycle Time tCK 12 ns
0C
0C
0C
0C
44
Max. DQS-DQ Skew tDQSQ
0.5 ns/0.6 ns
32
3C
32
3C
45
X-Factor tQHS
0.75 ns/1.0 ns
75
A0
75
A0
46 to 61
Superset Information
–
00
00
00
00
62
SPD Revision
Revision 0.0
00
00
00
00
63
Checksum for Bytes 0 - 62
–
A7
9C
C0
B5
64
Manufactures JEDEC ID Codes –
C1
C1
C1
C1
65 to 71
Manufactures
–
Infineon Infineon Infineon Infineon
72
Module Assembly Location
–
–
–
–
–
73 to 90
Module Part Number
–
–
–
–
–
91 to 92
Module Revision Code
–
–
–
–
–
93 to 94
Module Manufacturing Date
–
–
–
–
–
95 to 98
Module Serial Number
–
–
–
–
–
99 to 127
–
–
–
–
–
–
–
–
–
–
–
128 to 255 open for Customer use
Data Sheet
21
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Package Outlines
5
Package Outlines
Module Package
DDR Registered DIMM Modules Raw Card A, 128 MB Module
(one physical bank, 9 components)
Front View
4.0 max.
43.18 +- 0.13
133.35 +- 0.15
4.0
2.3 typ.
Register
Register
PLL
52
pin 1
92
53
64.77
1.27 +- 0.1
49.53
2.3 typ.
6.62
Backside View
144 145
184
2.5D
10.0
17.80
pin 93
3
3
Detail of Contacts B
6.35
2.5 +- 0.20
0.20 +- 0.15
Detail of Contacts A
3.8 typ.
0.9R
1+- 0.05
1.27
1.8
2.175
L-DIM-184-10, Raw Card A, one
bank
Figure 3
Data Sheet
Package Outlines Raw Card A
22
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Package Outlines
Module Package
DDR Registered DIMM Modules Raw Card B, 256 MB Module
(one physical bank, 18 components)
Front View
4.0 max.
43.43 +- 0.13
133.35 +- 0.15
4.0
2.3 typ.
Register
Register
PLL
52
pin 1
92
53
64.77
1.27 +- 0.1
49.53
2.3 typ.
6.62
Backside View
144 145
184
2.5D
10.0
17.80
pin 93
3
3
Detail of Contacts B
6.35
2.5 +- 0.20
0.20 +- 0.15
Detail of Contacts A
3.8 typ.
0.9R
1 +- 0.05
1.27
1.8
2.175
L-DIM-184-8, Raw Card
B
Figure 4
Data Sheet
Package Outlines Raw Card B
23
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Application Note
6
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item
1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and
to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked
Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM
inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the
register outputs are forced to a low level, and all differential register input receivers are powered down, resulting
in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as
an asynchronous signal according to the attached details. Using this function also permits the system and DIMM
clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh
mode.
Table 12
RESET Truth Table
Register Inputs
Register
Outputs
RESET
CK
CK
Data in (D)
Data out (Q)
H
Rising
Falling
H
H
H
Rising
Falling
L
L
H
L or H
L or H
X
Qo
H
High Z
High Z
X
Illegal input
conditions
L
X or Hi-Z
X or Hi-Z
X or Hi-Z
L
X: Don’t care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until
activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20 MHz. When an input clock frequency of 20 MHz
or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating
frequency at which all specifications will be met is 95 MHz). If the clock input frequency drops below 20 MHz
(actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are
made High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less
than 1 mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it
is tied inactive on the DIMM. This application note describes the required and optional system sequences
associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer
to both CKE0 and CKE1 for a 2-bank DIMM. Because RESET applies to all DIMM register devices, it is therefore
not possible to uniquely control CKE to one physical DIMM bank through the use of the RESET pin.
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low state
independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level
at the DDR SDRAMs.
Data Sheet
24
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Application Note
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a
stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior to
SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would
be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
1. The system applies Self Refresh entry command.
(CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→ High)
Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.The system sets RESET at a valid
low level.
This input condition forces all register outputs to a low state, independent of the condition on the registerm
inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable lowlevel at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation
to a specific clock edge is not required.
2. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the
register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address
signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which
Data Sheet
25
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Application Note
the clocks and the control and the address signals must maintain valid levels after RESET low has been
applied. It is highly recommended that CKE continue to remain low during this operation.
3. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM.
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches ~ 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to
be consistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
RESET timing relationship to a specific clock edge is not required (during this period, register inputs must
remain stable).
4. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this
is an alternate operating mode for these DIMMs.
1. System enters Self Refresh entry command.
(CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares — with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the data and clock
register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes
the time in which the clocks and the control and the address signals must maintain valid levels after RESET
low has been applied. It is highly recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be
Data Sheet
26
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A
Registered DDR SDRAM Modules
Application Note
a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent
with the state of the register outputs.
2. The system switches RESET to a logic 'high' level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain
stable).
3. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE
outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation
time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept
an input signal, is t (ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
sequence defined in this application note. In the case where RESET remains high and the clocks are powered off,
the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM
state will result.
Data Sheet
27
Rev. 1.04, 2004-01
10282003-ROLI-0GQ8
http://www.infineon.com
Published by Infineon Technologies AG