DAC7742 DAC 774 2 SBAS256A – DECEMBER 2002 – AUGUST 2007 16-Bit, Single Channel DIGITAL-TO-ANALOG CONVERTER With Internal Reference and Parallel Interface FEATURES DESCRIPTION ● LOW POWER: 150mW Maximum ● +10V INTERNAL REFERENCE ● UNIPOLAR OR BIPOLAR OPERATION ● SETTLING TIME: 5µs to ±0.003% FSR ● 16-BIT MONOTINICITY, –40°C TO +85°C ● ±10V, ±5V OR +10V CONFIGURABLE VOLTAGE OUTPUT ● RESET TO MIN-SCALE OR MID-SCALE ● DOUBLE-BUFFERED DATA INPUT ● INPUT REGISTER DATA READBACK ● SMALL LQFP-48 PACKAGE ● SUPPORTS TRANSPARENT DATA INPUT OPERATION The DAC7742 is a 16-bit Digital-to-Analog Converter (DAC) that provides 16 bits of monotonic performance over the specified operating temperature range and offers a +10V, low-drift internal reference. Designed for automatic test equipment and industrial process control applications, the DAC7742 output swing can be configured in a ±10V, ±5V, or +10V range. The flexibility of the output configuration allows the DAC7742 to provide both unipolar and bipolar operation by pin strapping. The DAC7742 includes a high-speed output amplifier with a maximum settling time of 5µs to ±0.003% FSR for a 20V full-scale change and only consumes 100mW (typical) of power. The DAC7742 features a standard 16-bit parallel interface with double buffering to allow asynchronous updates of the analog output, and data read-back to support data integrity verification prior to an update. A user-programmable reset control allows the DAC output to reset to min-scale (FFFFH) or mid-scale (7FFFH) overriding the DAC register values. The DAC7742 is available in an LQFP-48 package and three performance grades specified to operate from –40°C to +85°C. APPLICATIONS ● PROCESS CONTROL ● ATE PIN ELECTRONICS ● CLOSED-LOOP SERVO CONTROL ● MOTOR CONTROL ● DATA ACQUISITION SYSTEMS VDD VSS VCC REFADJ REFOUT REFIN VREF ROFFSET Buffer REFEN RFB2 +10V Reference CS R/W Control Logic RST RFB1 RSTSEL SJ Data I/O 16 AGND I/O Buffer DGND Input Register DAC Register DAC VOUT LDAC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2002-2007, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VCC to VSS ........................................................................... –0.3V to +32V VCC to AGND ...................................................................... –0.3V to +16V VSS to AGND ...................................................................... –16V to +0.3V AGND to DGND ................................................................. –0.3V to +0.3V REFIN to AGND ............................................................. 0V to VCC – 1.4V VDD to DGND ........................................................................ –0.3V to +6V Digital Input Voltage to DGND ................................. –0.3V to VDD + 0.3V Digital Output Voltage to DGND .............................. –0.3V to VDD + 0.3V Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Junction Temperature .................................................................... +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT LINEARITY ERROR (LSB) DIFFERENTIAL NONLINEARITY (LSB) PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE DAC7742 ±6 " ±4 LQFP-48 PT –40°C to +85°C " " " " ±4 ±2 LQFP-48 PT –40°C to +85°C " " " " " ±3 ±1 LQFP-48 PT –40°C to +85°C " " " " " " DAC7742 " DAC7742 " ORDERING NUMBER PACKAGE MARKING TRANSPORT MEDIA, QUANTITY DAC7742Y/250 DAC7742Y/2K DAC7742Y Tape and Reel, 250 Tape and Reel, 2000 DAC7742YB/250 DAC7742YB/2K DAC7742YB DAC7742YC/250 DAC7742YC/2K DAC7742YC " " " Tape and Reel, 250 Tape and Reel, 2000 Tape and Reel, 250 Tape and Reel, 2000 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ELECTRICAL CHARACTERISTICS All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, Internal reference enabled, unless otherwise noted. DAC7742Y PARAMETER CONDITIONS MIN TYP ACCURACY Linearity Error (INL) Gain Error Drift PSRR (VCC or VSS) ANALOG OUTPUT(1) Voltage Output(2) Output Current Output Impedance Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration 14 MIN TYP +11.4/–4.75 +11.4/–11.4 +11.4/–6.4 0 to 10 ±10 ±5 ±0.4 ±0.25 ±10 ✻ 200 ±25 4.75 VCC – 1.4 ✻ ✻ ±0.25 ±0.1 0 10 ✻ +2 ✻ ±7 ✻ ✻ V V V mA Ω pF mA ✻ ✻ ✻ ±10 ✻ 1 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 10.025 ✻ ✻ ✻ ✻ ✻ ✻ ±7 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 50 –2 LSB LSB LSB Bits % of FSR ppm/°C % of FSR % of FSR ppm/°C ppm/V ±0.2 ✻ ✻ 10 ±3 ±2 ±1 ✻ ✻ ✻ ✻ ✻ 9.975 UNITS ✻ ✻ ✻ ✻ 10.04 MAX 16 ✻ 10 400 ±15 TYP ✻ 0.1 200 ±15 Indefinite 9.96 MIN ✻ ±15 50 AGND MAX 15 With Internal REF With External REF With Internal REF At Full-Scale ±5 DAC7742YC ±4 ±3 ±2 ±0.1 ±2 REFERENCE Reference Output REFOUT Impedance REFOUT Voltage Drift REFOUT Voltage Adjustment(3) REFIN Input Range(4) REFIN Input Current REFADJ Input Range Absolute Max Value that can be applied is VCC REFADJ Input Impedance VREF Output Current VREF Impedance 2 MAX ±6 ±5 ±4 TA = 25°C Differential Linearity Error (DNL) Monotonicity Offset Error Offset Error Drift Gain Error DAC7742YB ✻ ✻ ✻ ✻ V Ω ppm/°C mV V nA V kΩ mA Ω DAC7742 www.ti.com SBAS256A ELECTRICAL CHARACTERISTICS (Cont.) All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, Internal reference enabled, unless otherwise noted. DAC7742Y PARAMETER DYNAMIC PERFORMANCE Settling Time to ±0.003% CONDITIONS MIN 20V Output Step RL = 5kΩ, CL = 200pF, with external REFOUT to REFIN filter(5) Digital Feedthrough Output Noise Voltage |IH| < 10µA |IL| < 10µA POWER SUPPLY VDD VCC VSS IDD ICC ISS Power 3 4 MIN Bipolar Operation Unipolar Operation Unloaded Unloaded No Load, Ext. Reference No Load, Int. Reference TEMPERATURE RANGE Specified Performance MAX ✻ ✻ –4 –40 100 4 –2.5 85 100 ✻ ✻ µs ✻ ✻ ✻ ✻ ✻ 150 ✻ nV-s nV/√Hz ✻ V V ✻ V V ✻ ✻ 6 +85 UNITS ✻ ✻ +5.25 +15.75 –11.4 –4.75 MAX ✻ 0.4 +5.0 TYP ✻ ✻ 3.6 +4.75 +11.4 –15.75 –15.75 MIN ✻ ✻ ✻ 0.3 • VDD See Table III IOH = –0.8mA IOL = 1.6mA DAC7742YC TYP ✻ ✻ 0.7 • VDD Input Coding DIGITAL OUTPUT VOH VOL MAX 2 100 at 10kHz DIGITAL INPUT VIH VIL DAC7742YB TYP ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V V V µA mA mA mW mW ✻ °C ✻ ✻ Specifications same as DAC7742Y. NOTES: (1) With minimum VCC/VSS requirements, internal reference enabled. (2) Please refer to the "Theory of Operation" section for more information with respect to output voltage configurations. (3) See Figure 7 for gain and offset adjustment connection diagrams when using the internal reference. (4) The minimum value for REFIN must be equal to the greater of VSS +14V and +4.75V, where +4.75V is the minimum voltage allowed. (5) Reference low-pass filter values: 100kΩ, 1.0µF (See Figure 10). DAC7742 SBAS256A www.ti.com 3 PIN CONFIGURATION REFIN REFADJ REFOUT REFEN RSTSEL R/W CS LDAC RST VDD DGND LQFP NC Top View 48 47 46 45 44 43 42 41 40 39 38 37 NC 1 36 NC VSS 2 35 DB15 VCC 3 34 DB14 VREF 4 33 DB13 ROFFSET 5 32 DB12 AGND 6 AGND 7 30 DB10 RFB2 8 29 DB9 RFB1 9 28 DB8 SJ 10 27 DB7 31 DB11 DAC7742 VOUT 11 26 TEST NC DB0 DB1 DB2 19 20 21 22 23 24 NC 18 NC 17 DB6 16 DB5 15 DB4 14 DB3 13 NC 25 NC NC NC 12 PIN DESCRIPTIONS PIN DESCRIPTION PIN NAME DB8 DESCRIPTION 1 NC No Connection 28 2 VSS Negative Analog Power Supply 29 DB9 Data Bit 9 3 VCC Positive Analog Power Supply 30 DB10 Data Bit 10 4 VREF Buffered Output from REFIN; can be used to drive external devices. Internally, this pin directly drives the DAC's circuitry. 31 DB11 Data Bit 11 32 DB12 Data Bit 12 33 DB13 Data Bit 8 Data Bit 13 Offsetting Resistor 34 DB14 Data Bit 14 Analog Ground (Must be tied to analog ground.) 35 DB15 Data Bit 15 (MSB) 5 ROFFSET 6 AGND 7 AGND Analog Ground (Must be tied to analog ground.) 36 NC No Connection 8 RFB2 Feedback Resistor 2, used to configure DAC output range. 37 DGND Digital Ground 38 VDD Digital Power Supply Feedback Resistor 1, used to configure DAC output range. 39 RST VOUT reset; active LOW, depending on the state of RSTSEL, the DAC register is either reset to midscale or min-scale. 40 LDAC DAC register load control, active LOW. Data is loaded from the input register to the DAC register. 9 4 NAME RFB1 10 SJ 11 VOUT 12 NC No Connection 13 NC No Connection 41 CS Chip Select, Active LOW 14 NC No Connection 42 R/W 15 NC No Connection Enabled by CS, controls data read (HIGH) and write (LOW) from or to the input register. 16 DB0 Data Bit 0 (LSB) 43 RSTSEL 17 DB1 Data Bit 1 18 DB2 Data Bit 2 Reset Select; determines the action of RST. If HIGH, RST will reset the DAC register to midscale. If LOW, RST will reset the DAC register to min-scale. 19 DB3 Data Bit 3 44 REFEN 20 DB4 Data Bit 4 Enables internal +10V reference (REFOUT), active LOW. 21 DB5 Data Bit 5 45 REFOUT Internal Reference Output 22 DB6 Data Bit 6 46 REFADJ 23 NC No Connection 24 NC No Connection Internal Reference Trim. (Acts as a gain adjustment input when the internal reference is used.) 25 NC No Connection 47 REFIN Reference Input 48 NC No Connection 26 TEST 27 DB7 Summing Junction of the Output Amplifier DAC Voltage Output Reserved, Connect to DGND Data Bit 7 DAC7742 www.ti.com SBAS256A TIMING DIAGRAMS DATA WRITE CYCLE tWCS CS tWS tWH tLH tLS R/W tDS Data In DB15-DB0 tDH tDS tDH Data Valid Data Valid LDAC tLWD tS VOUT READ CYCLE RESET TIMING tSS RSTSEL tSH tRCS CS tRDS R/W Data Out DB15-DB0 tRSS RST tRDH tS +FS Data Valid tDZ VOUT (RSTSEL = LOW) Min-Scale –FS tCSD +FS VOUT Mid-Scale (RSTSEL = HIGH) –FS TIMING CHARACTERISTICS DAC7742Y PARAMETER DESCRIPTION READ tRCS tRDS tRDH tDZ tCSD MIN CS LOW for Read R/W HIGH to CS LOW R/W HIGH After CS HIGH CS HIGH to Data Bus High Impedance CS LOW to Data Bus Valid 90 10 10 10 WRITE tWS tWH tWCS tLWD tLS tLH tDS tDH R/W LOW to CS LOW R/W LOW After CS HIGH CS LOW for Write LDAC LOW for Write CS LOW to LDAC HIGH for Direct Update CS LOW After LDAC HIGH Data Valid to CS LOW Data Valid After CS HIGH 10 10 25 20 30 0 0 20 ns ns ns ns ns ns ns ns RESET tRSS tSS tSH RST LOW RSTSEL Valid Before RST LOW RSTSEL Valid After RST HIGH 30 0 10 ns ns ns ANALOG tS Voltage Output Settling Time 70 MAX UNITS 70 100 ns ns ns ns ns 5 DAC7742 SBAS256A TYP www.ti.com µs 5 TYPICAL CHARACTERISTICS TA = +25°C (unless otherwise noted). INL (LSB) 6 4 2 0 –2 –4 –6 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Bipolar Configuration: VOUT = –10V to +10V TA = 85°C, Internal Reference Enabled 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H DNL (LSB) DNL (LSB) INL (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 6 4 2 0 –2 –4 –6 Bipolar Configuration: VOUT = –10V to +10V TA = 25°C, Internal Reference Enabled 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H Digital Input Code Digital Input Code 6 4 2 0 –2 –4 –6 OFFSET ERROR vs TEMPERATURE 5 4 3 2 Bipolar Configuration: VOUT = –10V to +10V TA = –40°C, Internal Reference Enabled Error (mV) DNL (LSB) INL (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H 1 0 –1 –2 –3 –4 –5 –40 10 35 60 85 VCC SUPPLY CURRENT vs DIGITAL INPUT CODE GAIN ERROR vs TEMPERATURE 4.4 0.15 Ext. Ref, Bipolar Mode: VOUT = –10V to +10V 4.3 0.10 Bipolar Configuration: VOUT = –10V to +10V Internal Reference Enabled, TA = 25°C 4.2 Int. Ref, Bipolar Mode: VOUT = –10V to +10V ICC (mA) Error (%) –15 Temperature (°C) Digital Input Code 0.05 4.1 4.0 3.9 0 Int. Ref, Unipolar Mode: VOUT = 0V to +10V Ext. Ref, Unipolar Mode: VOUT = 0V to +10V 3.8 –0.05 –40 –15 10 35 60 3.7 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H 85 Temperature (°C) 6 VOUT = –10V to +10V VOUT = 0V to +10V Digital Input Code DAC7742 www.ti.com SBAS256A TYPICAL CHARACTERISTICS (Cont.) TA = +25°C (unless otherwise noted). VSS SUPPLY CURRENT vs DIGITAL INPUT CODE VCC SUPPLY CURRENT vs DIGITAL INPUT CODE 3.4 –1.50 Bipolar Configuration: VOUT = –10V to +10V External Reference, REFEN = 5V, TA = 25°C 3.3 –1.75 –2.00 ISS (mA) ICC (mA) 3.2 3.1 3.0 –2.25 2.9 –2.50 Bipolar Configuration: VOUT = –10V to +10V TA = 25°C 2.8 –2.75 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H 2.7 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H Digital Input Code Digital Input Code SUPPLY CURRENT vs LOGIC INPUT VOLTAGE SUPPLY CURRENT vs TEMPERATURE 1000 6 5 800 4 ICC 2 IDD (µA) ICC, ISS (mA) 3 Load Current Excluded, VCC = +15V, VSS = –15V Bipolar VOUT Configuration: –10V to +10V 1 0 TA = 25°C, Transition Shown for One Data Input (CS = 5V, R/W = 0) 600 400 –1 ISS –2 200 –3 0 –4 –40 –15 10 35 60 0.0 85 0.5 1.0 1.5 3.5 4.0 4.5 5.0 100 Bipolar Output Configuration Internal Reference Enabled Code = AAAAH 90 80 70 70 60 60 Frequency Frequency 3.0 HISTOGRAM OF VSS CURRENT CONSUMPTION HISTOGRAM OF VCC CURRENT CONSUMPTION 100 80 2.5 VLOGIC (V) Temperature (°C) 90 2.0 50 40 50 40 30 30 20 20 10 10 0 3.000 0 3.500 4.000 4.500 5.000 –3.50 –3.00 –2.50 –2.00 –1.50 ISS (mA) ICC (mA) DAC7742 SBAS256A Bipolar Output Configuration Internal Reference Enabled Code = AAAAH www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) TA = +25°C (unless otherwise noted). POWER-SUPPY REJECTION RATIO vs FREQUENCY (Measured at VOUT) POWER-SUPPY REJECTION RATIO vs FREQUENCY (Measured at VOUT) 10 –10 –20 –10 –20 –30 –40 VSS –50 VCC –60 Bipolar Configuration: ±10V VOUT, Code 0000H –VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p 0 PSRR (dB) 0 PSRR (dB) 10 Bipolar Configuration: ±10V VOUT Code 7FFFH –VSS, VCC = 15V + 1Vp-p VDD = 5V + 0.5Vp-p VSS –30 VCC –40 –50 VDD –60 –70 –70 VDD –80 0.1k 1k 10k 100k 1M –80 0.01k 10M 0.1k 1k Frequency (Hz) 10k 100k Frequency (Hz) 1M 10M INTERNAL REFERENCE OUTPUT vs TEMPERATURE INTERNAL REFERENCE START-UP 15V 10.010 0V 10.005 REFOUT (V) REFOUT (2V/div) VCC (5V/div) 10.015 10V 10.000 9.995 9.990 0V 9.985 –40 Time (2ms/div) –15 10 35 60 85 Temperature (°C) OUTPUT VOLTAGE vs RLOAD REFOUT VOLTAGE vs LOAD 12 11.0 Source Loaded to VCC 8 REFOUT (V) 4 VOUT (V) VCC = +15V 10.5 0 10.0 9.5 –4 Sink 9.0 –8 Loaded to AGND 8.5 –12 0.0 0.1 1.0 10.0 100.0 RLOAD (kΩ) 8 1 10 100 1k REFOUT LOAD (kΩ) DAC7742 www.ti.com SBAS256A TYPICAL CHARACTERISTICS (Cont.) TA = +25°C (unless otherwise noted). POWER-SUPPY REJECTION RATIO vs FREQUENCY (Measured at REFOUT) 10 Internal Reference Enabled –VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p –10 –20 VCC –30 –40 VDD VSS –50 700 600 400 300 200 –70 100 –80 10 100 1k 10k Frequency (Hz) 100k 1M 10M Code FFFFH 0 0.01k 0.1k 1k 10k 100k Frequency (Hz) 1M 10M BROADBAND NOISE OUTPUT NOISE vs FREQUENCY 800 Code 0000H 500 –60 1 Unipolar Configuration, Internal Reference Enabled 800 Output Noise (nV/Hz) 0 PSRR (dB) OUTPUT NOISE vs FREQUENCY 900 Bipolar Configuration: ±10V, Internal Reference Enabled 600 VOUT (V, 50µV/div) Output Noise (nV/rtHz) 700 500 400 Code FFFFH 300 Code 0000H 200 100 Code 7FFFH 0 0.01k 0.1k 1k 10k 100k Frequency (Hz) 1M Internal Reference Enabled Filtered with 1.6Hz Low-Pass Code 0000H, Bipolar ±10V Configuration 10kHz Measurement BW Time (100µs/div) 10M UNIPOLAR FULL-SCALE SETTLING TIME BIPOLAR FULL-SCALE SETTLING TIME Small-Signal Error (150µV/div) Small-Signal Error (300µV/div) Large-Signal Output (5V/div) Large-Signal Output (5V/div) Unipolar Configurtaion: VOUT = 0V to +10V + Full-Scale to Zero-Scale 5kΩ, 200pF Load Bipolar Configurtaion: VOUT = –10V to +10V +Full-Scale to –Full-Scale 5kΩ, 200pF Load Time (2µs/div) Time (2µs/div) DAC7742 SBAS256A www.ti.com 9 TYPICAL CHARACTERISTICS (Cont.) TA = +25°C (unless otherwise noted). BIPOLAR FULL-SCALE SETTLING TIME UNIPOLAR FULL-SCALE SETTLING TIME Large-Signal Output (5V/div) Large-Signal Output (5V/div) Small-Signal Error (150µV/div) Small-Signal Error (300µV/div) Unipolar Configuration: VOUT = 0V to +10V Zero-Scale to +Full-Scale 5kΩ, 200pF Load Bipolar Configuration: VOUT = –10 to +10V –Full-Scale to +Full-Scale 5kΩ, 200pF Load Time (2µs/div) Time (2µs/div) MID-SCALE GLITCH MID-SCALE GLITCH Code 8000H to 7FFFH Bipolar Configuration: ±10V VOUT VOUT (V, 200mV/div) VOUT (V, 200mV/div) Code 7FFFH to 8000H Bipolar Configuration: ±10V VOUT Time (1µs/div) Time (1µs/div) DIGITAL FEEDTHROUGH All Data Bits Toggling (5V/div) VOUT = 7FFFH (100mV/div) CS = 5V Time (200ns/div) 10 DAC7742 www.ti.com SBAS256A THEORY OF OPERATION The digital input is a parallel word made up of the 16-bit DAC code and is loaded into the DAC register using the LDAC input pin. The converter can be powered from ±12V to ±15V dual analog supplies and a +5V logic supply. The device offers a reset function, which immediately sets the DAC output voltage and DAC register to min-scale (code FFFFH) or mid-scale (code 7FFFH). The data I/O and reset functions are discussed in more detail in the following sections. The DAC7742 is a voltage output, 16-bit DAC with a +10V builtin internal reference. The architecture is an R-2R ladder configuration with the three MSBs segmented, followed by an operational amplifier that serves as a buffer, as shown in Figure 1. The output buffer is designed to allow user-configurable output adjustments giving the DAC7742 output voltage ranges of 0V to +10V, –5V to +5V, or –10V to +10V. Please refer to Figures 2, 3, and 4 for pin configuration information. REFADJ REFOUT REFIN ROFFSET VREF RFB2 R/4 Buffer RFB1 +10V Internal Reference R/2 R/2 R/4 SJ R VOUT 2R 2R 2R 2R 2R 2R 2R 2R 2R R/4 VREF AGND FIGURE 1. DAC7742 Architecture. REFEN DB1 REFOUT DB0 REFADJ NC REFIN NC 14 NC NC DB6 DB5 DB4 20 DB3 NC VSS VCC VREF ROFFSET AGND AGND RFB2 RFB1 SJ VOUT NC 2 3 4 5 6 7 8 9 10 11 12 19 21 22 NC 16 17 18 Data Bus 15 DB2 1 VSS DAC7742 24 RSTSEL NC 23 R/W 13 NC 25 TEST 26 DB7 27 DB8 28 DB9 29 DB10 30 42 DB11 31 41 CS 43 DB12 32 40 LDAC 44 DB13 33 39 RST 45 DB14 34 37 38 VDD 46 Control Bus DGND 47 1µF 48 0.1µF NC 36 VDD DB15 35 Data Bus (0V to +10V) 0.1µF 1µF VCC 0.1µF 1µF FIGURE 2. Basic Operation: VOUT = 0V to +10V. DAC7742 SBAS256A www.ti.com 11 REFEN DB1 REFOUT DB0 REFADJ NC REFIN NC 14 NC NC DB6 DB5 DB4 20 DB3 8 NC RFB2 7 12 AGND 6 VOUT AGND 5 11 ROFFSET 4 SJ VREF 9 VCC 3 10 VSS 2 RFB1 NC 19 21 22 NC 16 17 18 Data Bus 15 DB2 1 VSS DAC7742 24 RSTSEL NC 23 R/W 13 NC 25 DB7 27 TEST 26 DB8 28 DB9 29 DB10 30 42 DB11 31 41 CS 43 DB12 32 40 LDAC 44 DB13 33 39 RST 45 DB14 34 37 38 VDD 46 Control Bus DGND 47 1µF 48 0.1µF NC 36 VDD DB15 35 Data Bus (–5V to +5V) 0.1µF 1µF VCC 0.1µF 1µF FIGURE 3. Basic Operation: VOUT = –5V to +5V. REFEN DB1 REFOUT DB0 REFADJ NC REFIN NC 14 NC NC DB6 DB5 DB4 20 DB3 8 19 NC RFB2 7 12 AGND 6 11 AGND VOUT ROFFSET 5 SJ VREF 4 RFB1 VCC 3 9 VSS 2 10 NC 21 22 NC 16 17 18 Data Bus 15 DB2 1 VSS DAC7742 24 RSTSEL NC 23 R/W 13 NC 25 TEST 26 DB7 27 DB8 28 DB9 29 DB10 30 42 DB11 31 41 CS 43 DB12 32 40 LDAC 44 DB13 33 39 RST 45 DB14 34 37 38 VDD 46 Control Bus DGND 47 1µF 48 0.1µF NC 36 VDD DB15 35 Data Bus (–10V to +10V) 0.1µF 1µF VCC 0.1µF 1µF FIGURE 4. Basic Operation: VOUT = –10V to +10V. 12 DAC7742 www.ti.com SBAS256A ANALOG OUTPUTS The output amplifier can swing to within 1.4V of the supply rails, specified over the –40°C to +85°C temperature range. This allows for a ±10V DAC voltage output operation from ±12V supplies with a typical 5% tolerance. When the DAC7742 is configured for a unipolar, 0V to 10V output, a negative voltage supply is required. This is due to internal biasing of the output stage. Please refer to the “Electrical Characteristics” table for more information. The minimum and maximum voltage output values are dependent upon the output configuration implemented and reference voltage applied to the DAC7742. Please note that VSS (the negative power supply) must be in the range of –4.75V to –15.75V for unipolar operation. The voltage on VSS sets several bias points within the converter and is required in all modes of operation. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not ensured. Supply sequence is important in establishing correct startup of the DAC. The digital supply (VDD) needs to establish correct bias conditions before the analog supplies (VCC, VSS) are brought up. If the digital supply cannot be brought up first, it must come up before either analog supply (VCC or VSS), with the preferred sequence of: VSS (device substrate), VDD, and then VCC. REFERENCE INPUTS The DAC7742 provides a built-in +10V voltage reference and on-chip buffer to allow external component reference drive. To use the internal reference, REFEN must be LOW, enabling the reference circuitry of the DAC7742 (as shown in Table I) and the REFOUT pin must be connected to REFIN. This is the input to the on-chip reference buffer. The buffer’s output is provided at the VREF pin. In this configuration, VREF is used to setup the DAC7742 output amplifier into one of three voltage output modes as discussed earlier. VREF can also be used to drive other system components requiring an external reference. The internal reference of the DAC7742 can be disabled when use of an external reference is desired. When using an external reference, the reference input, REFIN, can be any voltage between 4.75V (or VSS + 14V, whichever is greater) and VCC – 1.4V. DIGITAL INTERFACE Table III shows the data format for the DAC7742 and Table II illustrates the basic control logic of the device. The interface consists of a chip select input (CS), read/write control input (R/W), data inputs (DB0-DB15), and a load DAC input (LDAC). An asynchronous reset input (RST) which is active LOW, is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state, depending on the status of the reset select (RSTSEL) signal. The DAC code is provided via a 16-bit parallel interface, as shown in Table II. The input word makes up the DAC code to be loaded into the data input register of the device. The data is latched into the input register on rising CS and is loaded into the DAC register upon reception of a LOW level on the LDAC input. This action updates the analog output, VOUT, to the desired value. LDAC inputs of multiple DAC7742s can be connected when a synchronized update of numerous DAC outputs is desired. Please refer to the timing section for more detailed data I/O information. ANALOG OUTPUT DIGITAL INPUT Unipolar Configuration Bipolar Configuration Complementary Straight Binary Complementary Offset Binary 0xFFFF Zero (0V) –Full-Scale (–VREF or –VREF/2) 0xFFFE Zero + 1LSB –Full-Scale + 1LSB : : : REFEN ACTION 0x7FFF 1/2 Full-Scale Bipolar Zero 1 Internal Reference disabled; REFOUT = High Impedance 0x7FFE 1/2 Full-Scale + 1LSB Bipolar Zero + 1LSB : : : Internal Reference enabled; REFOUT = +10V 0x0000 Full-Scale (VREF – 1LSB) +Full-Scale (+VREF – 1LSB 0 or +VREF/2 – 1LSB) TABLE III. DAC7742 Data Format. TABLE I. REFEN Action. CONTROL STATUS COMMAND R/W CS RST RSTSEL LDAC Input Register DAC Register Mode L L H X H Write Hold Write Data to Input Register X H H X L Hold Write Update DAC Register with Data from Input Register L L H X L Transparent Write Write DAC Register Directly from Data Bus H L H X H, L Read Hold Read Data in Input Register X H H X H Hold Hold No Change X X L L X Reset to Min-Scale Reset to Min-Scale Reset to Input and DAC Register (FFFFH) Min-Scale X X L H X Reset to Mid-Scale Reset to Mid-Scale Reset to Input and DAC Register (7FFFH) Mid-Scale TABLE II. DAC7742 Logic Truth Table. DAC7742 SBAS256A www.ti.com 13 DAC RESET (+VREF) The RST and RSTSEL inputs control the reset of the analog output. The reset command is level triggered by a LOW signal on RST. Once RST is LOW, the DAC output will begin settling to the mid-scale or min-scale code depending on the state of the RSTSEL input. A HIGH value on RSTSEL will cause VOUT to reset to the mid-scale code (7FFFH) and a LOW value will reset VOUT to min-scale (FFFFH). A change in the state of the RSTSEL input while RST is LOW will cause a corresponding change in the reset command selected internally and consequently change the output value of VOUT of the DAC. Note that a valid reset signal also resets the input register of the DAC to the value specified by the state of RSTSEL. + Full-Scale 1LSB Analog Output Digital Input VCC VREF ROFFSET AGND AGND RFB2 RFB1 SJ 4 5 6 7 8 9 10 11 VSS 3 RPOT1 VOUT FIGURE 6. Relationship of Offset and Gain Adjustments for VOUT = –10V to +10V Output Configuration. (Same Theory Applies for VOUT = –5V to +5V.) NC NC Offset Adjust Translates the Line – Full-Scale (–VREF OR –VREF/2) 2 REFIN 18 Input = 0000 H Input = 7FFFH 1 REFADJ Gain Adjust Rotates the Line Full-Scale Range Input = FFFFH circuitry using potentiometers. 17 Full Scale Range Analog Output (+VREF or +VREF/2) + FullScale When calibrating the DAC’s output, offset should be adjusted first to avoid 1st-order interaction of adjustments. In unipolar mode, the DAC7742’s offset is adjusted from code FFFFH and for either bipolar mode, offset adjustments are made at code 7FFFH. Gain adjustment can then be made at code 0000H for each configuration, where the output of the DAC should be at +10V for the 0V to +10V – 1LSB or ±10V output range and +5V – 1LSB for the ±5V output range. Figure 7 shows the generalized external offset and gain adjustment 16 Digital Input FIGURE 5. Relationship of Offset and Gain Adjustments for VOUT = 0V to +10V Output Configuration. respectively. Optional Gain Adjust Input = 0000 H Offset Adjust Translates the Line The architecture of the DAC7742 is designed in such a way as to allow for easily configurable offset and gain calibration using a minimum of external components. The DAC7742 has built-in feedback resistors and output amplifier summing points brought out of the package in order to make the absolute calibration possible. Figures 5 and 6 illustrate the relationship of offset and gain adjustments for the DAC7742 in a unipolar configuration and in a bipolar configuration, REFOUT Input = FFFFH Zero Scale (AGND) GAIN AND OFFSET CALIBRATION 15 Gain Adjust Rotates the Line 1LSB ISJ R1 (Other Connections Omitted for Clarity) RS RPOT2 + VOADJ – Optional Offset Adjust FIGURE 7. Generalized External Calibration Circuitry for Gain and Symmetrical Offset Adjustment. 14 DAC7742 www.ti.com SBAS256A OFFSET ADJUSTMENT Offset adjustment is accomplished by introducing a small current into the summing junction (SJ) of the DAC7742. The voltage at SJ, or VSJ, is dependent on the output configuration of the DAC7742. Table IV shows the required pin strapping for a given configuration and the nominal values of VSJ for each output range. VSJ(1) REFERENCE OUTPUT PIN STRAPPING CONFIGURATION CONFIGURATION ROFFSET RFB1 RFB2 External Reference 0V to +10V –10V to +10V –5V to +5V +5V to VREF to VOUT to VOUT NC NC to VOUT +3.333V to AGND to VOUT to VOUT +2.5V to VREF to VOUT to VOUT 0V to VREF –VREF to VREF NC NC to VOUT –VREF/2 to VREF/2 to AGND to VOUT to VOUT VREF/2 VREF/3 VREF/4 NOTE: (1) Voltage measured at VSJ for a given configuration. TABLE IV. Nominal VSJ vs VOUT and Reference Configuration. The current level required to adjust the DAC7742’s offset can be created by using a potentiometer divider, see Figure 7. Another alternative is to use a unipolar DAC in order to apply a voltage, VOADJ, to the resistor RS. A ±1.2µA current range applied to SJ will ensure offset adjustment coverage of the ±0.1% maximum offset specification of the DAC7742. When in a unipolar configuration (VSJ = 5V), only a single resistor, RS, is needed for symmetrical offset adjustment with a 0V to 10V VOADJ range. When in one of the two bipolar configurations, VSJ is either +3.333v (±10V range) or +2.5V (±5V range), and circuit values chosen to match those given in Table V will provide symmetrical offset adjust. Please refer to Figure 7 for component configuration. OUTPUT RPOT2 CONFIGURATION R1 RS ISJ RANGE NOMINAL OFFSET ADJUSTMENT 0V to +10V –10V to +10V –5V to +5V 0 5k 10k 2.5M 1.5M 1.5M ±2µA ±2.2µA ±1.7µA ±25mV ±55mV ±21mV typ –10V to +10V VOUT Configuration min (75% of typ) 25 typ 0 min (75% of typ) 0V to 10V and –5V to +5V VOUT Configuration –25 –50 –2 –1 2 When the DAC7742’s internal reference is not used, gain adjustments can be made via trimming the external reference applied to the DAC at REFIN. This can be accomplished through using a potentiometer, unipolar DAC, or other means of precision voltage adjustment to control the voltage presented to the DAC7742 by the external reference. Figure 9 and Table VI summarize the range of adjustment of the internal reference via REFADJ. REFOUT ADJUST RANGE Typical REFOUT Adjustment Range 30 Figure 8 illustrates the typical and minimum offset adjustment ranges provided by forcing a current at SJ for a given output voltage configuration. 1 FIGURE 8. Offset Adjustment Transfer Characteristic. 40 TABLE V. Recommended External Component Values for Symmetrical Offset Adjustment (VREF = 10V). 0 ISJ (µA) REFOUT Adjustment (mV) 10k 10k 10k OFFSET ADJUST RANGE 50 Offset Adjustment at VOUT (mV) Internal Reference REFADJ can be driven by a low impedance voltage source such as a unipolar, 0V to +10V DAC or a potentiometer (less than 100kΩ), see Figure 7. Since the input impedance of REFADJ is typically 50kΩ, the smaller the resistance of the potentiometer, the more linear the adjustment will be. A 10kΩ potentiometer is suggested if linearity of the reference adjustment is of concern. 20 10 Minimum REFOUT Adjustment Range 0 –10 –20 –30 GAIN ADJUSTMENT –40 When using the internal reference of the DAC7742, gain adjustment is performed by adjusting the device’s internal reference voltage via the reference adjust pin, REFADJ. The effect of a reference voltage change on the gain of the DAC output can be seen in the generic equation (for unipolar configuration): 0 6 8 10 FIGURE 9. Internal Reference Adjustment Transfer Characteristic. VOLTAGE AT REFADJ REFOUT VOLTAGE REFADJ = 0V REFADJ = 5V or NC(1) REFADJ = 10V 10V + 25mV (min) 10V 10V – 25mV (max) NOTE: "NC" is "Not Connected". TABLE VI. Minimum Internal Reference Adjustment Range. DAC7742 SBAS256A 4 REFADJ (V) (65535 – N) VOUT = VREFIN • 65536 Where N is represented in decimal format and ranges from 0 to 65535. 2 www.ti.com 15 NOISE PERFORMANCE Increased noise performance of the DAC output can be achieved by filtering the voltage reference input to the DAC7742. Figure 10 shows a typical internal reference filter schematic. A low-pass filter applied between the REFOUT and REFIN pins can increase noise immunity at the DAC and output amplifier. The REFOUT pin can source a maximum of 50µA so care should be taken in order to avoid overloading the internal reference output. 46 REFADJ 47 REFIN 48 NC VCC REFOUT 3 45 VSS REFEN 2 (Other Connections Omitted for Clarity) 44 NC 1µF RSTSEL FIGURE 10. Internal Reference Filter. 16 A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC7742 offers separate digital and analog supplies, as it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more important it will become to separate the analog and digital ground and supply planes at the device. Since the DAC7742 has both analog and digital ground pins, return currents can be better controlled and have less effect on the DAC output error. Ideally, AGND would be connected directly to an analog ground plane and DGND to the digital ground plane. The analog ground plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system. 1 100kΩ 43 LAYOUT The voltages applied to VCC and VSS should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. In addition, a 1µF to 10µF bypass capacitor in parallel with a 0.1µF bypass capacitor is strongly recommended for each supply input. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a "Pi" filter made up of inductors and capacitors–all designed to essentially low-pass filter the analog supplies, removing any high frequency noise components. DAC7742 www.ti.com SBAS256A PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DAC7742Y/250 ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7742Y DAC7742YB/250 ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7742Y B DAC7742YC/250 ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7742Y C DAC7742YC/250G4 ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7742Y C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 10-Feb-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7742Y/250 LQFP PT 48 250 180.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 DAC7742YB/250 LQFP PT 48 250 180.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 DAC7742YC/250 LQFP PT 48 250 180.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Feb-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7742Y/250 LQFP PT 48 250 213.0 191.0 55.0 DAC7742YB/250 LQFP PT 48 250 213.0 191.0 55.0 DAC7742YC/250 LQFP PT 48 250 213.0 191.0 55.0 Pack Materials-Page 2 MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 This may also be a thermally enhanced plastic package with leads conected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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