TEMIC IQ83C154T-16 Cmos 0 to 36 mhz single chip 8-bit microcontroller Datasheet

80C154/83C154
CMOS 0 to 36 MHz Single Chip 8–bit Microcontroller
Description
TEMIC’s 80C154 and 83C154 are high performance
CMOS single chip µC. The 83C154 retains all the
features of the 80C52 with extended ROM capacity (16
K bytes), 256 bytes of RAM, 32 I/O lines, a 6-source
2-level interrupts, a full duplex serial port, an on-chip
oscillator and clock circuits, three 16 bit timers with extra
features : 32 bit timer and watchdog functions. Timer 0
and 1 can be configured by program to implement a 32 bit
timer. The watchdog function can be activated either with
timer 0 or timer 1 or both together (32 bit timer).
In addition, the 83C154 has 2 software-selectable modes
of reduced activity for further reduction in power
80C154 : ROMless version of the 83C154µ
80C154/83C154-12 : 0 to 12 MHz
80C154/83C154-16 : 0 to 16 MHz
80C154/83C154-20 : 0 to 20 MHz
80C154/83C154-25 : 0 to 25 MHz
80C154/83C154-30 : 0 to 30 MHz
consumption. In the idle mode the CPU is frozen while
the RAM is saved, and the timers, the serial port and the
interrupt system continue to function. In the power down
mode the RAM is saved and the timers, serial port and
interrupt continue to function when driven by external
clocks. In addition as for the TEMIC 80C51/80C52, the
stop clock mode is also available.
The 80C154 is identical to the 83C154 except that it has
no on-chip ROM. TEMIC’s 80C154 and 83C154 are
manufactured using SCMOS process which allows them
to run from 0 up to 36 MHz with Vcc = 5 V.
80C154/83C154-36 : 0 to 36 MHz
80C154/83C154-L16 : Low power version
VCC : 2.7-5.5 V Freq : 0-16 MHz
For other speed and temperature range availability please consult your
sales office.
Features
Power control modes
256 bytes of RAM
16 Kbytes of ROM (83C154)
32 Programmable I/O lines (programmable impedance)
Three 16 bit timer/counters (including watchdog and 32 bit
timer)
64 K program memory space
64 K data memory space
Fully static design
0.8µ CMOS process
Boolean processor
6 interrupt sources
Programmable serial port
Temperature range : commercial, industrial, automotive,
military
Optional
Secret ROM : Encryption
Secret TAG : Identification number
MATRA MHS
Rev.F (14 Jan. 97)
1
80C154/83C154
Interface
Figure 1. Block Diagram
2
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
80C154/83C154
P0.3/A3
P0.2/A2
P0.1/A1
P0.0/A0
VCC
NC
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
Figure 2. Pin Configuration
P1.5
P0.4/A4
P1.6
P0.5/A5
P1.7
P0.6/A6
RST
P0.7/A7
EA
RxD/P3.0
80C154/83C154
NC
NC
ALE
TxD/P3.1
A11/P2.4
A10/P2.3
A9/P2.2
A8/P2.1
NC
A3/P03
A2/P02
A1/P01
VCC
A0/P 0
P10 /T2
LCC
NC
P11 /T2EX
P12
P13
P14
DIL
A7/P2.0
P2.5/A12
VSS
P2.6/A13
T1/P3.5
XTAL1
P2.7/A14
T0/P3.4
XTAL2
INT1/P3.3
RD/P3.7
PSEN
WR/P3.6
INT0/P3.2
P15
P04 /A4
P16
P05 /A5
P17
P06 /A6
RST
P07 /A7
RxD/P30
EA
80C154/83C154
NC
NC
ALE
TxD/P31
P24 /A12
P23 /A11
P22 /A10
P21 /A9
P20 /A8
NC
V SS
P25 /A13
XTAL1
P26 /A14
T1/P35
XTAL2
P27 /A15
T0/P34
RD/P37
PSEN
INT1/P33
WR/P36
INT0/P32
Flat Pack
Diagrams are for reference only. Package sizes are not to scale
MATRA MHS
Rev.F (14 Jan. 97)
3
80C154/83C154
Pin Description
Vss
Port 2
Circuit Ground Potential.
Port 2 is an 8 bit bi-directional I/O port with internal
pullups. Port 2 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16 bit addresses (MOVX @DPTR). In
this application, it uses strong internal pullups when
emitting 1’s. During accesses to external Data Memory
that use 8 bit addresses (MOVX @Ri), Port 2 emits the
contents of the P2 Special Function Register.
It also receives the high-order address bits and control
signals during program verification in the 83C154. Port
2 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
VCC
Supply voltage during normal, Idle, and Power Down
operation.
Port 0
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0
pins that have 1’s written to them float, and in that state
can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups
when emitting 1’s. Port 0 also outputs the code bytes
during program verification in the 83C154. External
pullups are required during program verification. Port 0
can sink eight LS TTL inputs.
Port 1
Port 1 is an 8 bit bi-directional I/O port with internal
pullups. Port 1 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current (IIL, on the data
sheet) because of the internal pullups.
Port 3
Port 3 is an 8 bit bi-directional I/O port with internal
pullups. Port 3 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the pullups. It also serves the functions
of various special features of the TEMIC 51 Family, as
listed below.
Port Pin
Port 1 also receives the low-order address byte during
program verification. In the 83C154, Port 1 can sink or
source three LS TTL inputs. It can drive CMOS inputs
without external pullups.
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
2 inputs of PORT 1 are also used for timer/counter 2 :
P1.0 [T2] : External clock input for timer/counter 2. P1.1
[T2EX] : A trigger input for timer/counter 2, to be
reloaded or captured causing the timer/counter 2
interrupt.
Alternate Function
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
TD (Timer 0 external input)
T1 (Timer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
RST
A high level on this for two machine cycles while the
oscillator is running resets the device. An internal
pull-down resistor permits Power-On reset using only a
capacitor connected to VCC. As soon as the result is
applied (Vin), PORT 1, 2 and 3 are tied to 1. This
operation is achieved asynchronously even if the
oscillator is not start up.
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MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
ALE
XTAL1
Address Latch Enable output for latching the low byte of
the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of
1/6 the oscillator frequency except during an external
data memory access at which time one ALE pulse is
skipped. ALE can sink or source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
PSEN
XTAL2
Output of the inverting amplifier that forms the oscillator,
and input to the internal clock generator. This pin should
be floated when an external oscillator is used.
Program Store Enable output is the read strobe to external
Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory.
(However, when executing out of external Program
Memory, two activations of PSEN are skipped during
each access to external Data Memory). PSEN is not
activated during fetches from internal Program Memory.
PSEN can sink/source 8 LS TTL inputs. It can drive
CMOS inputs without an external pullup.
EA
When EA is held high, the CPU executed out of internal
Program Memory (unless the Program Counter exceeds
3FFFH). When EA is held low, the CPU executes only out
of external Program Memory. EA must not be floated.
Idle and Power Down Operation
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. The interrupt, serial port, and timer
blocks continue to function only with external clock
(INT0, INT1, T0, T1).
Figure 3. Idle and Power Down Hardware.
MATRA MHS
Rev.F (14 Jan. 97)
Idle Mode operation allows the interrupt, serial port, and
timer blocks to continue to function with internal or
external clocks, while the clock to CPU is gated off. The
special modes are activated by software via the Special
Function Register, PCON. Its hardware address is 87H.
PCON is not bit addressable.
5
80C154/83C154
PCON : Power Control Register
(MSB)
SMOD
(LSB)
HPD
RPD
–
GF1
GF0
PD
IDL
Symbol
Position
Name and Function
SMOD
PCON.7
HPD
PCON.6
Double Baud rate bit. When set to
a 1, the baud rate is doubled when
the serial port is being used in
either modes 1, 2 or 3.
Hard power Down bit. Setting this
bit allows CPU to enter in Power
Down state on an external event
(1 to 0 transition) on bit T1
(p. 3.5) the CPU quit the Hard
Power Down mode when bit T1
p. 3.5) goes high or when reset is
activated.
Recover from Idle or Power Down
bit. When 0 RPD has no effetc.
When 1, RPD permits to exit from
idle or Power Down with any non
enabled interrupt source (except
time 2). In this case the program
start at the next address. When
interrupt is enabled, the
appropriate interrupt routine is
serviced.
General-purpose flag bit.
General-purpose flag bit.
Power Down bit. Setting this bit
activates power down operation.
Idle mode bit. Setting this bit
activates idle mode operation.
RPD
PCON.5
GF1
GF0
PD
PCON.3
PCON.2
PCON.1
IDL
PCON.0
If 1’s are written to PD and IDL at the same time. PD
takes, precedence. The reset value of PCON is
(000X0000).
Idle Mode
The instruction that sets PCON.0 is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety : the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their
data during idle. In the idle mode, the internal clock signal
is gated off to the CPU, but interrupt, timer and serial port
functions are maintained. Table 1 describes the status of
the external pins during Idle mode. There are three ways
to terminate the Idle mode. Activation of any enabled
interrupt will cause PCON.0 to be cleared by hardware,
terminating Idle mode. The interrupt is serviced, and
following RETI, the next instruction to be executed will
be the one following the instruction that wrote 1 to
PCON.0.
6
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
The third way to terminate the Idle mode is the activation
of any disabled interrupt when recover is programmed
(RPD = 1). This will cause PCON.0 to be cleared. No
interrupt is serviced. The next instruction is executed. If
interrupt are disabled and RPD = 0, only a reset can
cancel the Idle mode.
Power Down Mode
The instruction that sets PCON.1 is the last executed prior
to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM and
the Special Function Register is saved during power down
mode. The three ways to terminate the Power Down mode
are the same than the Idle mode. But since the onchip
oscillator is stopped, the external interrupts, timers and
serial port must be sourced by external clocks only, via
INT0, INT1, T0, T1.
In the Power Down mode, VCC may be lowered to
minimize circuit power consumption. Care must be taken
to ensure the voltage is not reduced until the power down
mode is entered, and that the voltage is restored before the
hardware reset is applied which frees the oscillator. Reset
should not be released until the oscillator has restarted
and stabilized.
When using voltage reduction : interrupt, timers and
serial port functions are guaranteed in the VCC
specification limits.
Table 1 describes the status of the external pins while in
the power down mode. It should be noted that if the power
down mode is activated while in external program
memory, the port data that is held in the Special Function
Register P2 is restored to Port 2. If the port switches from
0 to 1, the port pin is held high during the power down
mode by the strong pullup, T1, shown in figure 4.
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
Table 1. Status of the external pins during idle and power down modes.
MODE
PROGRAM MEMORY
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
1
Port Data
Port Data
Port Data
Port Data
Idle
External
1
1
Floating
Port Data
Address
Port Data
Power Down
Internal
0
0
Port Data
Port Data
Port Data
Port Data
Power Down
External
0
0
Floating
Port Data
Port Data
Port Data
Figure 4. I/O Buffers in the 83C154 (Ports 1, 2, 3).
Stop Clock Mode
Due to static design, the TEMIC 83C154 clock speed can
be reduced until 0 MHz without any data loss in memory
or registers. This mode allows step by step utilization, and
permits to reduce system power consumption by bringing
the clock frequency down to any value. At 0 MHz, the
power consumption is the same as in the Power Down
Mode.
I/O Ports
The I/O drives for P1, P2, P3 of the 83C154 are
impedance programmable. The I/O buffers for Ports 1, 2
and 3 are implemented as shown in figure 4.
When the port latch contains 0, all pFETS in figure 4 are
off while the nFET is turned on. When the port latch
makes a 0-to-1 transition, the nFET turns off. The strong
pullup pFET, T1, turns on for two oscillator periods,
pulling the output high very rapidly. As the output line is
drawn high, pFET T3 turns on through the inverter to
supply the IOH source current. This inverter and T3 form
a latch which holds the 1 and is supported by T2. When
Port 2 is used as an address port, for access to external
program of data memory, any address bit that contains a
1 will have his strong pullup turned on for the entire
duration of the external memory access.
When an I/O pin on Ports 1, 2, or 3 is used as an input, the
user should be aware that the external circuit must sink
current during the logical 1-to-0 transition. The
MATRA MHS
Rev.F (14 Jan. 97)
maximum sink current is specified as ITL under the D.C.
Specifications. When the input goes below
approximately 2 V, T3 turns off to save ICC current. Note,
when returning to a logical 1, T2 is the only internal
pullup that is on. This will result in a slow rise time if the
user’s circuit does not force the input line high.
The input impedance of Port 1, 2, 2 are programmable
through the register IOCON. The ALF bit (IOCON0) set
all of the Port 1, 2, 3 floating when a Power Down mode
occurs. The P1HZ, P2HZ, P3HZ bits (IOCON1,
IOCON2, IOCON3) set respectively the Ports P1, P2, P3
in floating state. The IZC (IOCON4) allows to choose
input impedance of all ports (P1, P2, P3). When IZC = 0,
T2 and T3 pullup of I/O ports are active ; the internal input
impedance is approximately 10 K. When IZC = 1 only T2
pull-up is active. The T3 pull-up is turned off by IZC. The
internal impedance is approximately 100 K.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output respectively,
of an inverting amplifier which is configured for use as an
on-chip oscillator, as shown in figure 5. Either a quartz
crystal or ceramic resonator may be used.
Figure 5. Crystal Oscillator.
To drive the device from an external clock source,
XTAL1 should be driven while XTAL2 is left
unconnected as shown in figure 6. There are no
requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data Sheet
must be observed.
7
80C154/83C154
Figure 6. External Drive Configuration.
Hardware Description
Same as for the 80C51, plus a third timer/counter :
Timer/Event Counter 2
Timer 2 is a 16 bit timer/counter like Timers 0 and 1, it
can operate either as a timer or as an event counter. This
is selected by bit C/T2 in the Special Function Register
T2CON (Figure 1). It has three operating modes :
“capture”, “autoload” and “baud rate generator”, which
are selected by bits in T2CON as shown in Table 2.
EXEN2 = 0, then when Timer 2 rolls over it does not only
set TF2 but also causes the Timer 2 register to be reloaded
with the 16 bit value in registers RCAP2L and RCAP2H,
which are preset by software. If EXEN2 = 1, then Timer
2 still does the above, but with the added feature that a
1-to-0 transition at external input T2EX will also trigger
the 16 bit reload and set EXF2.
The auto-reload mode is illustrated in Figure 8.
Figure 7. Timer 2 in Capture Mode.
Table 2.Timer 2 Operating Modes.
RCLK +
TCLK
CP/RL2
TR2
0
0
1
X
0
1
X
X
1
1
1
0
MODE
16 bit auto-reload
16 bit capture
baud rate generator
(off)
In the capture mode there are two options which are
selected by bit EXEN2 in T2CON; If EXEN2 = 0, then
Timer 2 is a 16 bit timer or counter which upon
overflowing sets bit TF2, the Timer 2 overflow bit, which
can be used to generate an interrupt. If EXEN2 = 1, then
Timer 2 still does the above, but with the added feature
that a 1-to-0 transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 and TH2, to
be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit
EXF2 in T2CON to be set, and EXF2, like TF2, can
generate an interrupt.
Figure 8. Timer 2 in Auto-Reload Mode.
The capture mode is illustrated in Figure 7.
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON.If
8
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
(MSB)
(LSB)
EXF2
TF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
The baud rate generator mode is selected by : RCLK = 1 and/or TCLK = 1.
Symbol
Position
Name and Significance
TF2
T2CON.7
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK = 1 OR TCLK = 1.
EXF2
T2CON.6
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software.
RCLK
T2CON.5
Receive clock flag. When set, causes the serial port to use Timer2 overflow pulses for its
receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the
receive clock.
TCLK
T2CON.4
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for
its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for
the transmit clock.
EXEN2
T2CON.3
Timer 2 external enable flag. When set, allows capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2
T2CON.1
Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2
T2CON.0
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN 2 = 1. When cleared, auto reloads will occur either with Timer 2 overflows or
negative transition at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this
bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
Timer Functions
In fact, timer 0 & 1 can be connected by a software
instruction to implement a 32 bit timer function. Timer 0
(mode 3) or timer 1 (mode 0, 1, 2) or a 32 bit timer
consisting of timer 0 + timer 1 can be employed in the
watchdog mode, in which case a CPU reset is generated
upon a TF1 flag.
Figure 9.
Watchdog timer
The internal pull-up resistances at ports 1~3 can be set to
a ten times increased value simply by software.
32 Bit Mode and Watching Mode
32 bit timer [IOCON bit 6 (T32) = 1]
The 83C154 has two supplementary modes. They are
accessed by bits WDT and T32 of register IOCON. Figure
10 showns how IOCON must be programmed in order to
have access to these functions
MATRA MHS
Rev.F (14 Jan. 97)
9
80C154/83C154
(MSB)
(LSB)
WDT
T32
SERR
IZC
P3HZ
P2HZ
P1HZ
ALF
Symbol
Position
Name and Significance
T32
IOCON.6
–
–
If T32 = 1 and if C/T0 = 0, T1 and T0 are programmed as a 32 bit TIMER.
If T32 = 1 and if C/T0 = 1, T1 and T0 are programmed as a 32 bit COUNTER.
WDT
IOCON.7
–
If WDT = 1 and according to the mode selected by TMOD, an 8 bit or 32 bit
WATCHDOG is configured from TIMERS 0 and 1.
32 Bit Mode
T32 = 1 enables access to this mode. As shown in
figure 11, this 32 bit mode consists in cascading
TIMER 0 for the LSBs and TIMER 1 for the MSBs
Figure 10.32 Bit Timer/counter.
T32 = 1 starts the timer/counter and T32 = 0 stops it.
It should be noted that as soon as T32 = 0. TIMERs 0 and
1 assume the configuration specified by register TMOD.
Moreover, if TR0 = 1 or if TR1 = 1, the content of the
TIMERs evolves. Consequently, in 32 bit mode, if the
TIMER/COUNTER muste be stopped (T32 = 0), TR0
and TR1 must be set to 0.
32 Bit Timer
Figure 12 illustrates the 32 bit TIMER mode.
Figure 11. 32 Bit Timer Configuration.
In this mode, T32 = 1 and C/T0 = 0, the 32 bit timer
is incremented on each S3P1 state of each machine
cycle. An overflow of TIMER 0 (TF0 has not been set
to 1) increments TIMER 1 and the overflow of the
32 bit TIMER is signalled by setting TF1 (S5P1) to 1.
10
The following formula should be used to calculate the
required frequency :
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
32 Bit Counter
Figure 13 illustrates the 32 bit COUNTER mode.
Figure 12. 32 Bit Counter Configuration.
In this mode, T32 = 0 and C/T0 = 1. Before it can
make an increment, the 83C154µ must detect two
transitions on its T0 input. As shown in figure 14,
input T0 is sampled on each S5P2 state of every
machine cycle or, in other words, every OSC ÷ 12.
Figure 13. Counter Incrementation Condition.
The counter will only evolve if a level 1 is detected
during state S5P2 of cycle Ci and if a level 0 is
detected during state S5P2 of cycle Ci + n.
Consequently, the minimal period of signal fEXT
admissible by the counter must be greater than or
equal to two machine cycles. The following formula
should be used to calculate the operating frequency.
Figure 14. The Different Watchdog Configurations.
Watchdog Mode
WDT = 1 enables access to this mode. As shown in
figure 15, all the modes of TIMERS 0 and 1, of which
the overflows act on TF1 (TF1 = 1), activate the
WATCHDOG Mode.
MATRA MHS
Rev.F (14 Jan. 97)
11
80C154/83C154
If C/T = 0, the WATCHDOG is a TIMER that is
incremented every machine cycle. If C/T = 1, the
WATCHDOG is a counter that is incremented by an
external signal of which the frequency cannot exceed
OSC ÷ 24.
The overflow of the TIMER/COUNTER is signalled
by raising flag TF1 to 1. The reset of the 83C154 is
executed during the next machine cycle and lasts for
the next 5 machine cycles. The results of this reset are
identical to those of a hardware reset. The internal
RAM is not affected and the special register assume
the values shown in Table 3.
As there are no precautions for protecting bit WDT
from spurious writing in the IOCON register, special
care must be taken when writing the program. In
particular, the user should use the IOCON register bit
handling instructions :
– SETB and CLR x
in preference to the byte handling instructions :
– MOV IOCON, # XXH, ORL IOCON, #XXH,
– ANL IOCON, #XXH
Table 3. Content of the SFRS after a reset triggered
by the watchdog.
In the power-down mode, the oscillator is turned off
and the 83C154’s activity is frozen. However, if an
external clock is connected to one of the two inputs,
T1/T0, TIMER/COUNTERS 0 and 1 can continue to
operate.
In this case, counting becomes asychronous and the
maximum, admissible frequency of the signal is
OSC : 24.
The overflow of either counter TF0 or TF1 causes an
interrupt to be serviced or forces a reset if the counter
is in the WATCHDOG MODE (T32 = ICON.7 = 1).
REGISTER
PC
ACC
B
PSW
SP
DPTR
P0-P3
IP
IE
TMOD
TCON
T2CON
TH0
TL0
TH1
TL1
TH2
TL2
RCAP2H
RCAP2L
SCON
SBUF
IOCON
PCON
12
CONTENT
000H
00H
00H
00H
07H
0000H
0FFH
0X000000B
0X000000B
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Indeterminate
00H
000X0000B
External Counting in Power-down Mode
(PD = PCON.1 = 1)
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
83C154 with Secret ROM
83C154 with Secret TAG
TEMIC offers 83C154 with the encrypted secret ROM
option to secure the ROM code contained in the 83C154
microcontrollers.
TEMIC offers special 64-bit identifier called “SECRET
TAG” on the microcontroller chip.
The clear reading of the program contained in the ROM
is made impossible due to an encryption through several
random keys implemented during the manufacturing
process.
The keys used to do such encryption are selected
randomwise and are definitely different from one
microcontroller to another.
This encryption is activated during the following phases :
– Everytime a byte is addressed during a verify of the
ROM content, a byte of the encryption array is
selected.
– MOVC instructions executed from external program
memory are disabled when fetching code bytes from
internal memory.
– EA is sampled and latched on reset, thus all state
modification are disabled.
The Secret Tag option is available on both ROMless and
masked microcontrollers.
The Secret Tag feature allows serialization of each
microcontroller for identification of a specific
equipment. A unique number per device is implemented
in the chip during manufacturing process. The serial
number is a 64-bit binary value which is contained and
addressable in the Special Function Registers (SFR) area.
This Secret Tag option can be read-out by a software
routine and thus enables the user to do an individual
identity check per device. This routine is implemented
inside the microcontroller ROM memory in case of
masked version which can be kept secret (and then the
value of the Secret Tag also) by using a ROM Encryption.
For further information, please refer to the application
note (ANM031) available upon request.
For further information please refer to the application
note (ANM053) available upon request.
MATRA MHS
Rev.F (14 Jan. 97)
13
80C154/83C154
Electrical Characteristics
Absolute Maximum Ratings*
* Notice
Ambiant Temperature Under Bias :
C = commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
I = industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W**
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
Stresses at or above those listed under “ Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
DC Parameters
TA = 0°C to 70°C ; Vcc = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz
TA = –40°C + 85°C ; Vcc = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz
SYMBOL
VIL
Input Low Voltage
MIN
MAX
UNIT
– 0.5
0.2 Vcc – 0.1
V
0.2 Vcc + 1.4
Vcc + 0.5
V
0.7 Vcc
Vcc + 0.5
V
TEST CONDITIONS
VIH
Input High Voltage (Except XTAL and RST)
VIH1
Input High Voltage (for XTAL and RST)
VOL
Output Low Voltage (Port 1, 2 and 3)
0.3
0.45
1.0
V
V
V
IOL = 100 µA
IOL = 1.6 mA (note 2)
IOL = 3.5 mA
VOL1
Output Low Voltage (Port 0, ALE, PSEN)
0.3
0.45
1.0
V
V
V
IOL = 200 µA
IOL = 3.2 mA (note 2)
IOL = 7.0 mA
VOH
Output High Voltage Port 1, 2 and 3
Vcc – 0.3
V
IOH = – 10 µA
Vcc – 0.7
V
IOH = – 30 µA
Vcc – 1.5
V
IOH = – 60 µA
VCC = 5 V ± 10 %
Vcc – 0.3
V
IOH = – 200 µA
Vcc – 0.7
V
IOH = – 3.2 mA
Vcc – 1.5
V
IOH = – 7.0 mA
VCC = 5 V ± 10 %
– 50
µA
Vin = 0.45 V
VOH1
Output High Voltage (Port 0, ALE, PSEN)
IIL
Logical 0 Input Current (Ports 1, 2 and 3)
ILI
Input leakage Current
+/– 10
µA
0.45 < Vin < Vcc
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
– 650
µA
Vin = 2.0 V
IPD
Power Down Current
Vcc = 2.0 V to 5.5 V (note 1)
RRST
14
PARAMETER
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
ICC
Power Supply Current
Freq = 1 MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
Freq ≥ 12 MHz Icc op = 1.3 Freq (MHz) + 4.5 mA
Icc idle = 0.36 Freq (MHz) + 2.7 mA
50
50
µA
200
KOhm
10
pF
1.8
1
10
4
mA
mA
mA
mA
fc = 1 MHz, Ta = 25_C
Vcc = 5.5 V
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
Absolute Maximum Ratings*
* Notice
Ambient Temperature Under Bias :
A = Automotive . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
Stresses at or above those listed under “ Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
DC Parameters
TA = –40°C + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz
SYMBOL
PARAMETER
MIN
MAX
UNIT
– 0.5
0.2 Vcc – 0.1
V
0.2 Vcc + 1.4
Vcc + 0.5
V
0.7 Vcc
Vcc + 0.5
V
TEST CONDITIONS
VIL
Input Low Voltage
VIH
Input High Voltage (Except XTAL and RST)
VIH1
Input High Voltage (for XTAL and RST)
VOL
Output Low Voltage (Port 1, 2 and 3)
0.3
0.45
1.0
V
IOL = 100 µA
IOL = 1.6 mA (note 2)
IOL = 3.5 mA
VOL1
Output Low Voltage (Port 0, ALE, PSEN)
0.3
0.45
1.0
V
IOL = 200 µA
IOL = 3.2 mA (note 2)
IOL = 7.0 mA
VOH
Output High Voltage Port 1, 2 and 3
Vcc – 0.3
V
IOH = – 10 µA
Vcc – 0.7
V
IOH = – 30 µA
Vcc – 1.5
V
IOH = – 60 µA
VCC = 5 V ± 10 %
Vcc – 0.3
V
IOH = – 200 µA
Vcc – 0.7
V
IOH = – 3.2 mA
Vcc – 1.5
V
IOH = – 7.0 mA
VCC = 5 V ± 10 %
VOH1
Output High Voltage (Port 0, ALE, PSEN)
IIL
Logical 0 Input Current (Ports 1, 2 and 3)
– 50
µA
Vin = 0.45 V
ILI
Input leakage Current
±10
µA
0.45 < Vin < Vcc
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
– 750
µA
Vin = 2.0 V
IPD
Power Down Current
75
µA
Vcc = 2.0 V to 5.5 V (note 1)
200
KOhm
10
pF
1.8
1
10
4
mA
mA
mA
mA
RRST
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
ICC
Power Supply Current
Freq = 1 MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
Freq ≥ 12 MHz Icc op = 1.3 Freq (MHz) + 4.5 mA
Icc idle = 0.36 Freq (MHz) + 2.7 mA
MATRA MHS
Rev.F (14 Jan. 97)
50
fc = 1 MHz, Ta = 25_C
Vcc = 5.5 V
15
80C154/83C154
Absolute Maximum Ratings*
* Notice
Ambient Temperature Under Bias :
M = Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
Stresses at or above those listed under “ Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
DC Parameters
TA = –55°C + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz
SYMBOL
MIN
MAX
UNIT
– 0.5
0.2 Vcc – 0.1
V
0.2 Vcc + 1.4
Vcc + 0.5
V
0.7 Vcc
Vcc + 0.5
V
TEST CONDITIONS
VIL
Input Low Voltage
VIH
Input High Voltage (Except XTAL and RST)
VIH1
Input High Voltage (for XTAL and RST)
VOL
Output Low Voltage (Port 1, 2 and 3)
0.45
V
IOL = 1.6 mA (note 2)
VOL1
Output Low Voltage (Port 0, ALE, PSEN)
0.45
V
IOL = 3.2 mA (note 2)
VOH
Output High Voltage (Port 1, 2, 3)
2.4
V
IOH = – 60 µA
Vcc = 5 V ± 10 %
0.75 Vcc
V
IOH = – 25 µA
0.9 Vcc
V
IOH = – 10 µA
2.4
V
IOH = – 400 µA
Vcc = 5 V ± 10 %
0.75 Vcc
V
IOH = – 150 µA
0.9 Vcc
V
IOH = – 40 µA
VOH1
Output High Voltage
(Port 0 in External Bus Mode, ALE, PEN)
IIL
Logical 0 Input Current (Ports 1, 2 and 3)
– 75
µA
Vin = 0.45 V
ILI
Input leakage Current
±10
µA
0.45 < Vin < Vcc
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
– 750
µA
Vin = 2.0 V
IPD
Power Down Current
75
µA
Vcc = 2.0 V to 5.5 V (note 1)
200
KOh
m
10
pF
1.8
1
10
4
mA
mA
mA
mA
RRST
16
PARAMETER
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
ICC
Power Supply Current
Freq = 1 MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
Freq ≥ 12 MHz Icc op = 1.3 Freq (MHz) + 4.5 mA
Icc idle = 0.36 Freq (MHz) + 2.7 mA
50
fc = 1 MHz, Ta = 25_C
Vcc = 5.5 V
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
Absolute Maximum Ratings*
* Notice
Ambient Temperature Under Bias :
C = Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
I = Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
Stresses at or above those listed under “ Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
DC Parameters
TA = 0°C to 70°C ; Vcc = 2.7 V to 5.5 V ; Vss = 0 V ; F = 0 to 16 MHz
TA = –40°C to 85°C ; Vcc = 2.7 V to 5.5 V
SYMBOL
PARAMETER
MIN
MAX
UNIT
– 0.5
0.2 VCC – 0.1
V
TEST CONDITIONS
VIL
Input Low Voltage
VIH
Input High Voltage (Except XTAL and RST)
0.2 VCC
+ 1.4 V
VCC + 0.5
V
VIH1
Input High Voltage to XTAL1
0.7 VCC
VCC + 0.5
V
VIH2
Input High Voltage to RST for Reset
0.7 VCC
VCC + 0.5
V
VPD
Power Down Voltage to Vcc in PD Mode
2.0
6.0
V
VOL
Output Low Voltage (Ports 1, 2, 3)
0.45
V
IOL = 0.8 mA (note 2)
VOL1
Output Low Voltage Port 0, ALE, PSEN
0.45
V
IOL = 1.6 mA (note 2)
VOH
Output High Voltage Ports 1, 2, 3
0.9 Vcc
V
IOH = – 10 µA
VOH1
Output High Voltage (Port 0 in External Bus
Mode), ALE, PSEN
0.9 Vcc
V
IOH = – 40 µA
IIL
Logical 0 Input Current Ports 1, 2, 3
– 50
µA
Vin = 0.45 V
ILI
Input Leakage Current
± 10
µA
0.45 < Vin < VCC
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
– 650
µA
Vin = 2.0 V
IPD
Power Down Current
50
µA
VCC = 2 V to 5.5 V (note 1)
200
kΩ
10
pF
RRST
CIO
RST Pulldown Resistor
50
Capacitance of I/O Buffer
fc = 1 MHz, TA = 25_C
Maximum Icc (mA)
OPERATING (NOTE 1)
IDLE (NOTE 1)
FREQUENCY/Vcc
2.7 V
3V
3.3 V
5.5 V
2.7 V
3V
3.3 V
5.5 V
1 MHz
0.8 mA
1 mA
1.1 mA
1.8 mA
400 µA
500 µA
600 µA
1 mA
6 MHz
4 mA
5 mA
6 mA
10 mA
1.5 mA
1.7 mA
2 mA
4 mA
12 MHz
8 mA
10 mA
12 mA
2.5 mA
3 mA
3.5 mA
16 MHz
10 mA
12 mA
14 mA
3 mA
3.8 mA
4.5 mA
Freq > 12 MHz (Vcc = 5.5 V)
MATRA MHS
Rev.F (14 Jan. 97)
Icc (mA) = 1.3 × Freq (MHz) + 4.5
Icc Idle (mA) = 0.36 × Freq (MHz) + 2.7
17
80C154/83C154
Note 1 : ICC is measured with all output pins
disconnected ;
XTAL1
driven
with
TCLCH,
TCHCL = 5 ns, VIL = VSS + .5 V, VIH = VCC –.5 V ;
XTAL2 N.C. ; EA = RST = Port 0 = VCC. ICC would be
slighty higher if a crystal oscillator used.
Figure 15. ICC Test Condition, Idle Mode.
All other pins are disconnected.
Idle ICC is measured with all otput pins disconnected ;
XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL =
VSS + 5 V, VIH = VCC -.5 V ; XTAL2 N.C ; Port
0 = VCC ; EA = RST = VSS.
Power Down ICC is measured with all output pins
disconnected ; EA = PORT 0 = VCC ; XTAL2 N.C. ;
RST = VSS.
Note 2 : Capacitance loading on Ports 0 and 2 may cause
spurious noise pulses to be superimposed on the VOLS of
ALE and Ports 1 and 3. The noise is due to external bus
capacitance discharging into the Port 0 and Port 2 pins
when these pins make 1 to 0 transitions during bus
operations. In the worst cases (capacitive loading 100
pF), the noise pulse on the ALE line may exceed 0.45 V
may exceed 0,45 V with maxi VOL peak 0.6 V A Schmitt
Trigger use is not necessary.
Figure 16. ICC Test Condition, Active Mode.
All other pins are disconnected.
Figure 17. ICC Test Condition, Power Down Mode.
All other pins are disconnected.
Figure 18. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
18
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
Explanation of the AC Symbol
Each timing symbol has 5 characters. The first character
is always a “T” (stands for time). The other characters,
depending on their positions, stand for the name of a
signal or the logical status of that signal. The following
is a list of all the characters and what they stand for.
Example :
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
A : Address.
C : Clock.
D : Input data.
H : Logic level HIGH
I : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P : PSEN.
Q : Output data.
R : READ signal.
T : Time.
V : Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z : Float.
AC Parameters
TA = 0 to + 70°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz
TA = –55° + 125°C ; Vss = 0 V ; 2.7 V < Vcc < 5.5 V ; F = 0 to 16 MHz
TA = –55° + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz
(Load Capacitance for PORT 0, ALE and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF)
External Program Memory Characteristics
16 MHz
SYMBOL
PARAMETER
20 MHz
25 MHz
30 MHz
36 MHz
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
TLHLL
ALE Pulse Width
110
90
70
60
50
TAVLL
Address valid to ALE
40
30
20
15
10
TLLAX
Address Hold After ALE
35
35
35
35
35
TLLIV
ALE to valid instr in
185
170
130
100
80
TLLPL
ALE to PSEN
45
40
30
25
20
TPLPH
PSEN pulse Width
165
130
100
80
75
TPLIV
PSEN to valid instr in
TPXIX
Input instr Hold After PSEN
TPXIZ
Input instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid instr in
230
210
170
130
90
TPLAZ
PSEN low to Address Float
10
10
8
6
5
125
0
110
0
50
55
85
0
45
50
65
0
35
40
50
0
30
35
25
30
External Program Memory Read Cycle
TAVIV
MATRA MHS
Rev.F (14 Jan. 97)
19
80C154/83C154
External Data Memory Characteristics
16 MHz
SYMBOL
PARAMETER
20 MHz
25 MHz
30 MHz
36 MHz
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
TRLRH
RD pulse Width
340
270
210
180
120
TWLWH
WR pulse Width
340
270
210
180
120
85
TLLAX
Address Hold After ALE
TRLDV
RD to Valid in
85
TRHDX
Data hold after RD
TRHDZ
Data float after RD
90
90
80
70
50
TLLDV
ALE to Valid Data In
435
370
350
235
170
TAVDV
Address to Valid Data IN
480
400
300
260
190
240
0
70
210
0
250
135
55
175
0
ALE to WR or RD
150
Address to WR or RD
180
180
140
115
75
TQVWX
Data valid to WR transition
35
35
30
20
15
TQVWH
Data Setup to WR transition
380
325
250
215
170
TWHQX
Data Hold after WR
40
35
30
20
15
TRLAZ
RD low to Address Float
TWHLH
RD or WR high to ALE high
90
0
35
60
130
90
0
TLLWL
35
120
0
110
TAVWL
0
170
35
135
0
25
45
115
70
0
20
40
100
0
20
40
External Data Memory Write Cycle
TAVWL
TQVWX
External Data Memory Read Cycle
20
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
Serial Port Timing – Shift Register Mode
16 MHz
SYMBOL
PARAMETER
20 MHz
25 MHz
30 MHz
36 MHz
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
TXLXL
Serial Port Clock Cycle Time
750
600
480
400
330
TQVXH
Output Data Setup to Clock Rising
Edge
563
480
380
300
220
TXHQX
Output Data Hold after Clock Rising
Edge
63
90
65
50
45
TXHDX
Input Data Hold after Clock Rising
Edge
0
0
0
0
0
TXHDV
Clock Rising Edge to Input Data Valid
563
450
350
300
250
Shift Register Timing Waveforms
MATRA MHS
Rev.F (14 Jan. 97)
21
80C154/83C154
External Clock Drive Characteristics (XTAL1)
SYMBOL
PARAMETER
FCLCL
Oscillator Frequency
TCLCL
Oscillator period
TCHCX
MIN
MAX
UNIT
36
MHz
27.8
ns
High Time
5
ns
TCLCX
Low Time
5
ns
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
ns
External Clock Drive Waveforms
AC Testing Input/Output Waveforms
AC inputs during testing are driven at Vcc – 0.5 for a logic “1” and 0.45 V for a logic “0”. Timing measurements are
made at VIH min for a logic “1” and VIL max for a logic “0”.
Float Waveforms
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to
float when a 100 mV change from the loaded VOH/VOL level occurs. Iol/IoH ≥ ± 20 mA.
22
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are
incorporated in the AC specifications.
MATRA MHS
Rev.F (14 Jan. 97)
23
80C154/83C154
Ordering Information
I
Temperature Range
blank : Commercial
I
: Industrial
A
: Automotive
M
: Military
83C154C
Part Number
83C154 Rom 16 K × 8
80C154 External ROM
83C154C Secret ROM version
83C154T Secret Tag version
–12
–16
–20
–25
–30
–36
–L16
Package Type
P: PDIL 40
S: PLCC 44
F1: PQFP 44 (Foot print 13.9 mm)
F2: PQFP 44 (Foot print 12.3 mm)
V: VQFP (1.4 mm)
T: TQFP (1.0 mm)
D: CDIL 40
Q: CQFP 44
R: LCC 44
Customer Rom Code
24
: 12 MHz version
: 16 MHz version
: 20 MHz version
: 25 MHz version
: 30 MHz version
: 36 MHz version
: Low Power
(Vcc : 2.7-5.5 V
Freq : 0-16 MHz)
R : Tape and Reel
D : Dry Pack
Flow
/883: MIL 883 Compliant
P883: MIL 883 Compliant
with PIND test.
MATRA MHS
Rev.F (14 Jan. 97)