DRV
DRV101
101
DRV
10 1
SBVS008B – JANUARY 1998 – REVISED MAY 2009
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PWM SOLENOID/VALVE DRIVER
FEATURES
DESCRIPTION
● HIGH OUTPUT DRIVE: 2.3A
● WIDE SUPPLY RANGE: +9V to +60V
● COMPLETE FUNCTION
PWM Output
Internal 24kHz Oscillator
Digital Control Input
Adjustable Delay and Duty Cycle
Over/Under Current Indicator
● FULLY PROTECTED
Thermal Shutdown with Indicator
Internal Current Limit
● PACKAGES: 7-Lead TO-220 and 7-Lead
Surface-Mount DDPAK
The DRV101 is a low-side power switch employing a
pulse-width modulated (PWM) output. Its rugged design
is optimized for driving electromechanical devices such
as valves, solenoids, relays, actuators, and positioners.
The DRV101 is also ideal for driving thermal devices
such as heaters and lamps. PWM operation conserves
power and reduces heat rise, resulting in higher
reliability. In addition, adjustable PWM allows fine
control of the power delivered to the load. Time from
dc output to PWM output is externally adjustable.
The DRV101 can be set to provide a strong initial
closure, automatically switching to a soft hold mode for
power savings. Duty cycle can be controlled by a
resistor, analog voltage, or digital-to-analog converter
for versatility. A flag output indicates thermal shutdown
and over/under current limit. A wide supply range
allows use with a variety of actuators.
The DRV101 is available in a 7-lead staggered
TO-220 package and a 7-lead surface-mount DDPAK
plastic power package. It is specified over the extended
industrial temperature range of –40°C to +85°C.
APPLICATIONS
● ELECTROMECHANICAL DRIVERS:
Solenoids
Positioners
Actuators
High Power Relays/Contactors
Valves
Clutch/Brake
● FLUID AND GAS FLOW SYSTEMS
● INDUSTRIAL CONTROL
● FACTORY AUTOMATION
● PART HANDLERS
● PHOTOGRAPHIC PROCESSING
● ELECTRICAL HEATERS
● MOTOR SPEED CONTROL
● SOLENOID/COIL PROTECTORS
● MEDICAL ANALYZERS
Input
On
7
5
Load
Thermal Shutdown
Over/Under Current
24kHz
Oscillator
1
6
Out
PWM
(TTL-Compatible)
Off
VS (+9V to +60V)
Flag
Gnd
Delay
4
2
Delay
Adjust
(electrically
connected to
tab)
3
Duty Cycle Adjust
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 1998-2009, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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SPECIFICATIONS
At TC = +25°C, VS = +24V, Load = 100Ω || 1000pF, and 4.99kΩ Flag pullup to +5V, unless otherwise noted.
DRV101T, F
PARAMETER
OUTPUT
Output Saturation Voltage, Sink
Current Limit
Under-Scale Current(1)
Leakage Current
DIGITAL CONTROL INPUT(2)
VCTR Low (output disabled)
VCTR High (output enabled)
ICTR Low (output disabled)
ICTR High (output enabled)
Propagation Delay
DELAY TO PWM(3)
Delay Equation(4)
Delay Time
Minimum Delay Time(5)
DUTY CYCLE ADJUST
Duty Cycle Range
Duty Cycle Accuracy
vs Supply Voltage
Nonlinearity(6)
DYNAMIC RESPONSE
Output Voltage Rise Time
Output Voltage Fall Time
Oscillator Frequency
FLAG
Normal Operation
Fault(7)
Sink Current
Under-Current Flag: Set
Reset
Over-Current Flag: Set
Reset
COMMENTS
MIN
TYP
MAX
UNITS
1.9
+0.8
+0.2
2.3
23
±0.01
+1
+0.3
3
V
V
A
mA
mA
IO = 1A
IO = 0.1A
Output Transistor Off, VS = VO = +60V
0
+2.2
VCTR = 0V
VCTR = +5V
On-to-Off and Off-to-On
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance, θJC
7-Lead DDPAK, 7-Lead TO-220
Thermal Resistance, θJA
7-Lead DDPAK, 7-Lead TO-220
+1.2
+5.5
–80
20
2
V
V
µA
µA
µs
dc to PWM Mode
CD = 0.1µF
CD = 0
Delay to PWM ≈ CD • 106 (CD in F)
80
95
110
15
50% Duty Cycle, RPWM = 28.7kΩ
50% Duty Cycle, VS = VO = +9V to +60V
10% to 80% Duty Cycle
VO = 10% to 90% of VS
VO = 90% to 10% of VS
19
20kΩ Pull-Up to +5V, IO < 1.5A
Sinking 1mA
VFLAG = 0.4V
+4
THERMAL SHUTDOWN
Junction Temperature
Shutdown
Reset from Shutdown
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
±1
10 to 90
±2
±1
2
±5
±5
%
%
%
% FSR
1
0.1
24
2.5
2.5
29
µs
µs
kHz
+4.9
+0.2
2
4
2
2
2
+0.8
+24
+9
3.5
–40
–55
–65
No Heat Sink
V
V
mA
µs
µs
µs
µs
°C
°C
+165
+150
IO = 0
s
ms
µs
+60
5
V
V
mA
+85
+125
+150
°C
°C
°C
3
°C/W
65
°C/W
NOTES:(1) Under-scale current for TC < 100°C—see Under-Scale Current vs Temperature typical performance curve. (2) Logic High enables output (normal
operation). (3) Constant dc output to PWM (pulse-width modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust Pin
low corresponds to an infinite (continuous) delay. (5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) VIN at pin 3 to percent of duty cycle
at pin 6. (7) A fault results from over-temperature, over-current, or under-current conditions.
2
DRV101
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SBVS008B
ABSOLUTE MAXIMUM RATINGS(1)
CONNECTION DIAGRAMS
Top Front View
TO-220, DDPAK
7-Lead
Stagger-Formed
TO-220
1 2 3 4 5 6 7
7-Lead
DDPAK
Surface-Mount
PWM
VS
Delay Gnd
PWM
VS
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) Vapor-phase or IR reflow techniques are recommended for soldering the DRV101F surface-mount package. Wave soldering
is not recommended due to excessive thermal shock and “shadowing” of
nearby devices.
ELECTROSTATIC
DISCHARGE SENSITIVITY
1 2 3 4 5 6 7
In
In
Supply Voltage, VS .............................................................................. 60V
Input Voltage .......................................................................... –0.2V to VS
PWM Adjust Input .................................................................. –0.2V to VS
Delay Adjust Input ................................................ –0.2V to VS (24V max)
Operating Temperature Range ...................................... –40°C to +125°C
Storage Temperature Range ......................................... –65°C to +150°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s)(2) ........................................... +300°C
Flag
Out
Flag
Delay Gnd Out
NOTE: Tabs are electrically connected to ground (pin 4).
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet.
DRV101
SBVS008B
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3
PIN DESCRIPTIONS
PIN #
NAME
DESCRIPTION
Pin 1
Input
The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above
the typical switching threshold, 1.7V. Below this level, the output is disabled. With no connection to the pin, the input level rises
to 3.4V. Input current is 20µA when driven high and 80µA with the input low. The input may be momentarily driven to the power
supply (VS) without damage.
Pin 2
Delay Adjust
This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results
in a delay of approximately 15µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less
than 3µs by tying the pin to 5V. This pin connects internally to a 3µA current source from VS and to a 3V threshold comparator.
When the pin voltage is below 3V, the output device is 100% on. The PWM oscillator is not synchronized to the Input (pin 1),
so the first pulse may be extended by any portion of the programmed duty cycle.
Pin 3
Duty Cycle Adjust
(PWM)
Internally, this pin connects to the input of a comparator and a 19kΩ resistor to ground. It is driven by a 200µA current source
from VS. The voltage at this node linearly sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage,
or output of a D/A converter. The active voltage range is from 0.75V to 3.7V to facilitate the use of single-supply control
electronics. At 0.75V (or RPWM = 3.5kΩ), duty cycle is near 90%. Swing to ground should be limited to no lower than 0.1V. PWM
frequency is a constant 24kHz.
Pin 4
Ground
This pin is electrically connected to the package tab. It must be connected to system ground for the DRV101 to function. It
carries the 3.5mA quiescent current plus the load current when the device is on.
Pin 5
VS
This is the power supply pin. Operating range is +9V to +60V.
Pin 6
Out
The output is the collector of a power npn with the emitter connected to ground. Low power dissipation in the DRV101 is attained
by the low saturation voltage and the fast switching transitions. Fall time is less than 75ns, rise time depends on load
impedance. Base drive to the power device is limited with light loads to control turn-off delay. The response of this circuit causes
the brief dip in saturation voltage after turn on. A flyback diode is needed with inductive loads to conduct the load current during
the off cycle. The external diode should be selected for low forward voltage. The internal clamp diode provides protection but
shouuld not be used to conduct load currents greater than 0.5A.
Pin 7
Flag
Normally high (active low), the Flag signals either an over-temperature, over-current, or under-current fault. The over/undercurrent flags are true only when the output is on (constant dc output or the “on” portion of PWM mode). A thermal fault (thermal
shutdown) occurs when the die surface reaches approximately 165°C and latches until the die cools to 150°C. Its output
requires a pull-up resistor. It can typically sink two milliamps, sufficient to drive a low-current LED.
LOGIC BLOCK DIAGRAM
VS (+9V to +60V)
Flag
7
5
Load
Over/Under Current
6
Out
Thermal
Shutdown
Input
1
PWM
On
Off
4
Gnd
Delay
2
CD
4
Schottky Power
Rectifier
3
RPWM
DRV101
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SBVS008B
TYPICAL PERFORMANCE CURVES
At TC = +25°C and VS = +24V, unless otherwise noted.
DUTY CYCLE and DUTY CYCLE ERROR vs VOLTAGE
90
DUTY CYCLE vs TEMPERATURE
8
100
Load = 1A
RPWM = 6.04kΩ
6
Duty Cycle (%)
70
4
60
2
Error
50
0
40
–2
30
–4
20
–6
10
–8
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
80
Duty Cycle (%)
Duty Cycle
Duty Cycle Error (%)
80
60
RPWM = 30.1kΩ
RPWM = 100kΩ
40
RPWM = 301kΩ
20
RPWM = 750kΩ
0
4.0
–75
–50
–25
VPWM (V)
25
50
75
100
125
100
125
CURRENT LIMIT vs TEMPERATURE
OUTPUT SATURATION VOLTAGE vs TEMPERATURE
2.6
2.5
VS = +9V to +60V
2.0
2.4
IO = 2A
Effect of
Current-Limit
Current Limit (mA)
Saturation Voltage (V)
0
Temperature (°C)
1.5
IO = 1.5A
1.0
IO = 1A
0.5
IO = 0.5A
2.2
2.0
1.8
IO = 0.1A
1.6
0
–75
–50
–25
0
25
50
75
100
–75
125
–50
–25
QUIESCENT CURRENT vs TEMPERATURE
25
50
75
UNDER-SCALE CURRENT vs TEMPERATURE
3.9
30
VS = +9V
3.7
Under-Scale Current (mA)
VS = +60V
Quiescent Current (mA)
0
Temperature (°C)
Temperature (°C)
VS = +24V
3.5
VS = +9V
3.3
3.1
25
VS = +24V
20
15
Lines represent maximum current
before under-current Flag occurs.
Under-current Flag may not
occur for case temperature
above 100°C.
10
5
VS = +60V
0
–75
–50
–25
0
25
50
75
100
125
–75
Temperature (°C)
–25
0
25
50
75
100
125
Temperature (°C)
DRV101
SBVS008B
–50
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5
TYPICAL PERFORMANCE CURVES
(CONT)
At TC = +25°C and VS = +24V, unless otherwise noted.
FLAG OPERATION
OVER-CURRENT LIMIT
(VS = +60V, CD = 110pF, RPWM = 750kΩ)
FLAG OPERATION
UNDER-CURRENT
(VS = +24V, CD = 110pF, RPWM = 6.04kΩ)
4V
Onset of
current limit
40V
VIN
VOUT
60V
20V
No Load
2V
0
Flag only on during constant output
or “ON” portion of PWM mode
0
Flag only set
during constant
output mode or
“ON” portion of
PWM mode
2V
4V
VFLAG
VFLAG
4V
2V
0
0
Constant Output
PWM Mode
25µs/div
50µs/div
DC TO PWM MODE
DRIVING INDUCTIVE LOAD
(VS = +60V, CD = 110pF, RPWM = 301kΩ)
DUTY CYCLE UNDERSHOOT
Load = 1A
30V
VOUT
VOUT
60V
40V
Non-optimized Layout
30V
See Duty Cycle Undershoot
curve for detail
1A
VOUT
0V
IGND
10V
0
20V
2A
20V
0
20V
10V
Clean Layout
0
Inductive load ramp current
1µs/div
50µs/div
TYPICAL SOLENOID CURRENT WAVEFORM
(VS = +24V)
OSCILLATOR FREQUENCY vs TEMPERATURE
1A
Solenoid
Motion
Period
{
0.5A
PWM Mode
0
Oscillator Frequency (kHz)
24.2
24.0
VS = +9V
23.8
23.6
VS = +60V
Solenoid Closure
23.4
–75 –55 –35
25ms/div
–15
5
25
45
65
85
105 125
Temperature (°C)
6
DRV101
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SBVS008B
TYPICAL PERFORMANCE CURVES
(CONT)
At TC = +25°C and VS = +24V, unless otherwise noted.
MINIMUM DELAY TO PWM vs TEMPERATURE
NOMINAL DELAY TIME TO PWM vs TEMPERATURE
22
104
20
102
VS = +9V
V
VSS == +24V
+24V
100
19
98
Delay (ms)
Delay (µs)
CD = 0.1µF
No connection to
Delay Adjust pin
(CD = 0)
21
18
17
16
VS = +60V
VS = +24V
VS = +60V
96
94
92
15
VS = +9V
90
14
88
–75
–50
–25
0
25
50
75
100
125
–75
Temperature (°C)
–25
0
25
50
75
100
125
Temperature (°C)
DRV101
SBVS008B
–50
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7
BASIC OPERATION
by a resistor, analog voltage, or D/A converter. Figure 1b
provides an example timing diagram with the Delay Adjust
pin connected to 0.1µF and duty cycle set for 25%. See the
“Delay Adjust” and “Duty Cycle Adjust” text for equations
and further explanation.
The DRV101 is a low-side, bipolar power switch employing
a pulse-width modulated (PWM) output for driving electromechanical and thermal devices. Its design is optimized for
two types of applications; a two-state driver (open/close) for
loads such as solenoids and actuators, and a linear driver for
valves, positioners, heaters, and lamps. Its wide supply
range, adjustable delay to PWM mode, and adjustable duty
cycle make it suitable for a wide range of applications.
Figure 1 shows the basic circuit connections to operate the
DRV101. A 0.1µF bypass capacitor is shown connected to
the power supply pin.
Ground (pin 4) is electrically connected to the package tab.
This pin must be connected to system ground for the
DRV101 to function. This serves as the load current path to
ground, as well as the DRV101 reference ground.
The load (solenoid, valve, etc.) is connected between the
supply (pin 5) and output (pin 6). For an inductive load, an
external diode across the output is required as shown in
Figure 1a. The diode serves to maintain the hold force during
PWM operation. For remotely located loads, the external
diode should be placed close to the DRV101 (Figure 1a). The
internal clamp diode between the output and ground should
not be used to carry load current.
The Input (pin 1) is compatible with standard TTL levels.
Input voltages between +2.2V and +5.5V turn the device
output on, while pulling the pin low (0V to +1.2V), shuts the
DRV101 output off. Input current is typically 80µA.
Delay Adjust (pin 2) and Duty Cycle Adjust (pin 3) allow
external adjustment of the PWM output signal. The Delay
Adjust pin can be left floating for minimum delay to PWM
mode (typically 15µs) or a capacitor can be used to set the
delay time. Duty cycle of the PWM output can be controlled
The Flag (pin 7) provides fault status for under-current,
over-current, and thermal shutdown conditions. This pin is
active low with pin voltage typically +0.3V during a fault
condition. A small value capacitor may be needed between
Flag and ground for noisy applications.
Basic Circuit Connections
VS
0.1µF
Flag
7
5
(1)
Load
Thermal Shutdown
Over/Under Current
6
24kHz
Oscillator
(a)
Input
1
Out
PWM
(TTL-Compatible)
Gnd
Delay
On
4
Off
2
CD
(electrically
connected to
tab)
3
Delay
Adjust
RPWM
Duty Cycle Adjust
NOTE: (1) External flyback diode required for inductive loads to conduct load current during the off cycle.
For remotely located loads, diode should be placed close to the DRV101.
Motorola MSRS1100T3 (1A, 100V), MBRS360T3 (3A, 60V)
Simplified Timing Diagram
CD = 0.1µF (95ms constant dc output before PWM)
RPWM = 130kΩ
•••
+2.2V to +5.5V
INPUT
0V to +1.2V
(b)
VS
OUTPUT
•••
CD = 0.1µF
95ms
0
tON
tON ≈ 10.4µs
tP ≈ 41.6µs (1/24kHz)
t
Duty Cycle = ON = 25%
tP
tP
Initial dc Output
(set by value
of CD)
RPWM = 130kΩ
PWM Mode
(resistor or voltage
controlled)
FIGURE 1. Basic Circuit Connections and Timing Diagram.
8
DRV101
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SBVS008B
APPLICATIONS INFORMATION
POWER SUPPLY
The DRV101 operates from a single +9V to +60V supply
with excellent performance. Most behavior remains unchanged throughout the full operating voltage range. Parameters which vary significantly with operating voltage are
shown in the Typical Performance Curves.
ADJUSTABLE DUTY CYCLE
The DRV101’s externally adjustable duty cycle provides an
accurate means of controlling power delivered to the load.
Duty cycle can be set from 10% to 100% with an external
resistor, analog voltage, or the output of a D/A converter.
Reduced duty cycle results in reduced power dissipation.
This keeps the DRV101 and load cooler, resulting in increased reliability for both devices. PWM frequency is a
constant 24kHz.
ADJUSTABLE INITIAL 100% DUTY CYCLE
Resistor Controlled Duty Cycle
A unique feature of the DRV101 is its ability to provide an
initial constant dc output (100% duty cycle) and then switch
to PWM mode to save power. This function is particularly
useful when driving solenoids which have a much higher
pull-in current requirement than hold requirement.
Duty cycle is easily programmed with a resistor (RPWM)
connected between the Duty Cycle Adjust pin and ground.
Increased resistor values correspond to decreased duty cycles.
Table II provides resistor values for typical duty cycles.
Resistor values for additional duty cycles can be obtained
from Figure 3. For reference purposes, the equation for
calculating RPWM is included in Figure 3.
The duration of this constant dc output (before PWM output
begins) can be externally controlled with a capacitor connected from Delay Adjust (pin 2) to ground according to the
following equation:
DUTY CYCLE
RESISTOR(1)
RPWM (kΩ)
VOLTAGE(2)
VPWM (V)
10
20
30
40
50
60
70
80
90
976
205
84.5
46.4
28.7
18.2
11.8
7.50
4.87
3.7
3.4
3.0
2.6
2.2
1.75
1.35
1.00
0.75
Delay Time ≈ CD • 106
(time in seconds, CD in Farads)
Leaving the Delay Adjust pin open results in a constant
output time of approximately 15µs. The duration of this
initial output can be reduced to less than 3µs by connecting
the pin to 5V. Table I provides examples of desired “delay”
times (constant output before PWM mode) and the appropriate capacitor values or pin connection.
CONSTANT OUTPUT DURATION
CD
3µs
15µs
100µs
1ms
100ms
Pin connected to 5V
Pin open
100pF
1nF
0.1µF
NOTES: (1) Resistor values listed are nearest 1% standard values. (2) Do not
drive pin below 0.1V. For additional values, see “Duty Cycle vs Voltage” typical
performance curve.
TABLE II. Duty Cycle Adjust. TA= +25°C, VS = +24V.
1000
TABLE I. Delay Adjust Pin Connections.
The internal Delay Adjust circuitry is composed of a 3µA
current source and a 3V comparator as shown in Figure 2.
Thus, when the pin voltage is less than 3V, the output device
is 100% on (dc output mode).
RPWM (kΩ)
100
10
1
10
20
DRV101
VS
40
60
80
100
Duty Cycle (%)
3V Reference
RPWM = [ a + b (DC) + c (DC)2 + d (DC)3 + e (DC)4]–1
where: a = 2.4711 x 10–6
b = –5.2095 x 10–7
c = 4.4576 x 10–8
Comparator
3µA
d = –7.6427 x 10–10
e = 6.8039 x 10–12
DC = duty cycle in %
For 50% duty cycle:
RPWM = [2.4711 x 10–6 + (–5.2095 x 10–7) (50) + (4.4576 x 10–8) (50)2
+ (–7.6427 x 10–10) (50)3 + (6.8039 x 10–12) (50)4]–1
2
Delay Adjust
CD
= 28.7kΩ
FIGURE 2. Simplified Circuit Model of the Delay Adjust Pin.
FIGURE 3. RPWM vs Duty Cycle.
DRV101
SBVS008B
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9
Voltage Controlled Duty Cycle
STATUS FLAG
Duty cycle can also be programmed with an analog voltage,
VPWM. With VPWM ≈ 0.75V, duty cycle is near 90%. Increasing this voltage results in decreased duty cycles. Table II
provides VPWM values for typical duty cycles. See the “Duty
Cycle vs Voltage” Typical Performance Curve for additional duty cycles.
Flag (pin 7) provides fault indication for under-current,
over-current, and thermal shutdown conditions. During a
fault condition, Flag output is driven low (pin voltage
typically drops to 0.3V). A pull-up resistor, as shown in
Figure 6, is required to interface with standard logic. A small
value capacitor may be needed between Flag and ground in
noisy applications.
The Duty Cycle Adjust pin should not be driven below 0.1V.
If the voltage source used can go between 0.1V and ground,
a series resistor between the voltage source and the Duty
Cycle Adjust pin (Figure 4) is required to limit swing. If the
pin is driven below 0.1V, the output will be unpredictable.
VS
Figure 6 gives an example of a non-latching fault monitoring
circuit, while Figure 7 provides a latching version. The Flag
pin can sink several milliamps, sufficent to drive external
logic circuitry or an LED (Figure 8) to indicate when a fault
has occurred. In addition, the Flag pin can be used to turn off
other DRV101’s in a system for chain fault protection.
5
DRV101
6
+5V
Out
5kΩ
Pull-Up
PWM
TTL or HCT
4
VPWM 3
Flag
D/A
Converter
(or analog
voltage)
1kΩ(1)
7
Thermal Shutdown
Over/Under Current
6
Out
NOTE: (1) Required if voltage source can go below 0.1V.
FIGURE 4. Using a Voltage to Program Duty Cycle.
4
DRV101
The DRV101’s internal 24kHz oscillator sets the PWM
period. This frequency is not externally adjustable. Duty
Cycle Adjust (pin 3) is internally driven by a 200µA current
source and connects to the input of a comparator and a 19kΩ
resistor as shown in Figure 5. The DRV101’s PWM control
design is inherently monotonic. That is, a decreased voltage
(or resistor value) always produces an increased duty cycle.
FIGURE 6. Non-Latching Fault Monitoring Circuit.
+5V
74XX76A
VS
3.8V
f = 24kHz
Flag
Q
Flag
Q
Flag Reset
20kΩ
J
CLR
CLK
(1)
0.7V
GND
K
VS
Comparator
200µA
Flag
7
Thermal Shutdown
Over/Under Current
19kΩ
6
Out
DRV101
3
Duty Cycle
Adjust
DRV101
Resistor or
Voltage Source(1)
4
NOTE: (1) Small capacitor (10pF) may be required in noisy environments.
NOTE: (1) Do not drive pin below 0.1V.
FIGURE 5. Simplified Circuit Model of the Duty Cycle
Adjust Pin.
10
FIGURE 7. Latching Fault Monitoring Circuit.
DRV101
www.ti.com
SBVS008B
An under-current fault occurs when the output current is
below the under-scale current threshold (typically 23mA).
For example, this function indicates when the load is disconnected. Again, the flag output is not latched, so an undercurrent condition during PWM mode will produce a flag
output that is modulated by the PWM waveform. An initial,
brief under-current flag normally appears driving inductive
loads and may be avoided by adding a parallel resistor
sufficient to move the initial current above the under-current
threshold. An under-current flag may not appear for case
temperatures above 100°C. Avoid adding capacitance to pin
6 (Out) as it may cause momentary current limiting.
+5V
5kΩ
(LED)
HLMP-Q156
Flag
7
Thermal Shutdown
Over/Under Current
6
Out
Over-Temperature Fault
4
DRV101
A thermal fault occurs when the die reaches approximately
165°C, producing a similar effect as pulling the input low.
Internal shutdown circuitry disables the output and resets the
Delay Adjust pin. The Flag is latched in the low state (fault
condition) until the die has cooled to approximately 150°C.
A thermal fault can occur in any mode of operation. Recovery from thermal fault will start in delay mode (constant dc
output).
FIGURE 8. LED to Indicate Fault Condition.
Over/Under Current Fault
An over-current fault occurs when the output current is
greater than approximately 2.3A. The status flag is not
latched. Since current during PWM mode is switched on and
off, the flag output will be modulated with PWM timing (see
flag waveforms in the Typical Performance Curves).
PACKAGE MOUNTING
Figure 9 provides recommended PCB layouts for both the
TO-220 and DDPAK power packages. The tab of both
packages is electrically connected to ground (pin 4). It may
be desirable to isolate the tab of TO-220 package from its
mounting surface with a mica (or other film) insulator (see
7-Lead DDPAK(1)
KTW Package(2)
7-Lead TO-220
KVT Package(2)
0.45
0.04
0.2
0.05
0.085
0.15
0.335
0.51
0.05
0.035
0.105
Mean dimensions in inches. Refer to end of data sheet
for tolerances and detailed package drawings.
NOTES: (1) For improved thermal performance increase footprint area.
See Figure 11, Thermal Resistance vs Circuit Board Copper Area.
(2) Refer to the mechanical drawings at the end of this document.
FIGURE 9. TO-220 and DDPAK Solder Footprints.
DRV101
SBVS008B
www.ti.com
11
THERMAL RESISTANCE
vs ALUMINUM PLATE AREA
Aluminum Plate Area
Thermal Resistance θJA (°C/W)
18
Vertically Mounted
in Free Air
Flat, Rectangular
Aluminum Plate
16
14
0.030in Al
12
0.050in Al
10
Aluminum
Plate Thickness
0.062in Al
8
0
1
2
3
4
5
6
7
Optional mica or film insulator
for electrical isolation. Adds
DRV101
approximately 1°C/W.
TO-220 Package
8
Aluminum Plate Area (inches2)
FIGURE 10. TO-220 Thermal Resistance vs Aluminum Plate Area.
THERMAL RESISTANCE vs
CIRCUIT BOARD COPPER AREA
Thermal Resistance, θJA (°C/W)
50
DRV101
DDPAK
Surface-Mount Package
1oz. copper
40
Circuit Board Copper Area
30
20
10
0
0
1
2
3
4
DRV101
DDPAK
Surface-Mount Package
5
Copper Area (inches2)
FIGURE 11. DDPAK Thermal Resistance vs Circuit Board Copper Area.
Figure 10). For lowest overall thermal resistance, it is best to
isolate the entire heat sink/DRV101 structure from the
mounting surface rather than to use an insulator between the
semiconductor and heat sink.
For best thermal performance, the tab of the DDPAK surface-mount version should be soldered directly to a circuit
board copper area. Increasing the copper area improves heat
dissipation. Figure 11 shows typical thermal resistance from
junction-to-ambient as a function of the copper area.
POWER DISSIPATION
Power dissipation depends on power supply, signal, and load
conditions. Power dissipation is equal to the product of
output current times the voltage across the conducting output transistor times the duty cycle. Power dissipation can be
minimized by using the lowest possible duty cycle necessary
to assure the required hold force.
Application Bulletin AB-039 explains how to calculate or
measure power dissipation with unusual signals and loads.
THERMAL PROTECTION
Power dissipated in the DRV101 will cause the junction
temperature to rise. The DRV101 has thermal shutdown
circuitry that protects the device from damage. The thermal
12
protection circuitry disables the output when the junction
temperature reaches approximately +165°C, allowing the
device to cool. When the junction temperature cools to
approximately +150°C, the output circuitry is again enabled.
Depending on load and signal conditions, the thermal protection circuit may cycle on and off. This limits the dissipation
of the amplifier but may have an undesirable effect on the
load.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an inadequate heat
sink. For reliable operation, junction temperature should be
limited to +125°C, maximum. To estimate the margin of
safety in a complete design (including heat sink), increase
the ambient temperature until the thermal protection is
triggered. Use worst-case load and signal conditions. For
good reliability, thermal protection should trigger more than
40°C above the maximum expected ambient condition of
your application. This produces a junction temperature of
125°C at the maximum expected ambient condition.
The internal protection circuitry of the DRV101 was designed to protect against overload conditions. It was not
intended to replace proper heat sinking. Continuously running the DRV101 into thermal shutdown will degrade reliability.
DRV101
www.ti.com
SBVS008B
HEAT SINKING
Heat Sink Selection Example
Most applications will not require a heat sink to assure that
the maximum operating junction temperature (125°C) is not
exceeded. However, junction temperature should be kept as
low as possible for increased reliability. Junction temperature can be determined according to the equation:
A TO-220 package is dissipating 5 Watts. The maximum
expected ambient temperature is 35°C. Find the proper heat
sink to keep the junction temperature below 125°C.
TJ =
TA =
PD =
θJC =
θCH =
θHA =
θJA =
TJ = TA + PDθJA
(1)
where, θJA = θJC + θCH + θHA
(2)
Junction Temperature (°C)
Ambient Temperature (°C)
Power Dissipated (W)
Junction-to-Case Thermal Resistance (°C/W)
Case-to-Heat Sink Thermal Resistance (°C/W)
Heat Sink-to-Ambient Thermal Resistance (°C/W)
Junction-to-Air Thermal Resistance (°C/W)
Figure 12 shows maximum power dissipation versus ambient temperature with and without the use of a heat sink.
Using a heat sink significantly increases the maximum
power dissipation at a given ambient temperature as shown.
Power Dissipation (Watts)
TO-220 with Thermalloy
6030B Heat Sink
θJA = 16.7°C/W
8
PD = (TJ (max) – TA) / θ JA
TJ (max) = 125°C
With infinite heat sink
( θJA = 3°C/W),
max PD = 33W
at TA = 25°C
6
DDPAK
θ JA = 26°C/W
(3 in2 one oz
copper mounting pad)
4
DDPAK or TO-220
θ JA = 65°C/W (no heat sink)
0
25
50
75
100
(3)
θ HA =
TJ – TA
– (θ JC + θ CH )
PD
θ HA =
125° C – 35° C
– (3° C/ W + 1° C/ W ) = 14° C/ W
5W
(4)
Another variable to consider is natural convection versus
forced convection air flow. Forced-air cooling by a small fan
can lower θCA (θCH + θHA) dramatically. Heat sink manufacturers provide thermal data for both of these cases. For
additional information on determining heat sink requirements, consult Application Bulletin AB-038.
2
0
TJ = TA + PD(θJC + θCH + θHA)
TJ, TA, and PD are given. θJC is provided in the specification
table, 3°C/W. θCH can be obtained from the heat sink
manufacturer. Its value depends on heat sink size, area, and
material used. Semiconductor package type, mounting screw
torque, insulating material used (if any), and thermal
joint compound used (if any) also affect θCH. A typical θCH
for a TO-220 mounted package is 1°C/W. Now we can solve
for θHA:
To maintain junction temperature below 125°C, the heat
sink selected must have a θHA less than 14°C/W. In other
words, the heat sink temperature rise above ambient must be
less than 70°C (14°C/W x 5W). For example, at 5 Watts
Thermalloy model number 6030B has a heat sink
temperature rise of 66°C above ambient (θHA = 66°C/5W =
13.2°C/W), which is below the 70°C required in this example. Figure 12 shows power dissipation versus ambient
temperature for a TO-220 package with a 6030B heat sink.
MAXIMUM POWER DISSIPATION
vs AMBIENT TEMPERATURE
10
Combining Equations 1 and 2 gives:
125
As mentioned earlier, once a heat sink has been selected, the
complete design should be tested under worst-case load and
signal conditions to ensure proper thermal protection.
Ambient Temperature (°C)
FIGURE 12. Maximum Power Dissipation vs Ambient
Temperature.
The difficulty in selecting the heat sink required lies in
determining the power dissipated by the DRV101. For dc
output into a purely resistive load, power dissipation is simply
the load current times the voltage developed across the
conducting output transistor times the duty cycle. Other loads
are not as simple. Consult Application Bulletin AB-039 for
further insight on calculating power dissipation. Once power
dissipation for an application is known, the proper heat sink
can be selected.
DRV101
SBVS008B
www.ti.com
13
APPLICATION CIRCUITS
Pinch Valve
+5V
Flexible Tube
5kΩ
Flag
VS (+9V to +60V)
Plunger
7
5
Thermal Shutdown
Over/Under Current
Out
24kHz
Oscillator
Microprocessor
TTL Control Input
1
Solenoid Coil
6
Can drive most types
of solenoid-actuated
valves and actuators
PWM
Gnd
On
Delay
4
DRV101
Off
2
Delay
Adjust
3
CD RPWM
Duty Cycle Adjust(1)
(10% to 100%)
NOTE: (1) Duty cycle can be programmed by
a resistor, analog voltage, or D/A converter.
Do not drive below 0.1V.
FIGURE 13. Fluid Flow Control System.
VS
VS
Brighter light results in
increased duty cycle
5
(1)
Coil
DRV101
5
Lamp
DRV101
6
6
Input
(On/Off)
1
On/Off
4
4
3
100Ω
Aimed at
ambient
light
Cadmium Sulfide
Optical Detector
(Clairex CL70SHL
or CLSP5M)
λ
Duty Cycle Adjust
4-20mA
187Ω
10kΩ
NOTE: (1) Rectifier diode required for inductive
loads to conduct load current during the off cycle.
FIGURE 14. Instrument Light Dimmer Circuit.
14
FIGURE 15. 4-20mA Input to PWM Output.
DRV101
www.ti.com
SBVS008B
Higher temperature results in lower duty cycle
(a)
VS
Heating Element
Thermistor
5
DRV101
6
1
R1
On/Off
4
R2
3
Duty Cycle
Adjust
10µF
(b)
VS
REF200
0.1µF
7, 8
Heating
Element
5
DRV101
100µA
100µA
1
2
6
1
On/Off
4
2
3
2µF Film
NC
0.1µF VS
7
1kΩ
Duty Cycle
Adjust
6
2
OPA134
10MΩ
3
4
10kΩ
4.7V
Temperature
Control
or
Thermistor
5kΩ at +25°C
IN4148(1)
Integrator improves accuracy
NOTE: (1) Or any common silicon diode suited
to the mechanical mounting requirements.
20kΩ
FIGURE 16. Temperature Controller.
DRV101
SBVS008B
www.ti.com
15
+12V
dc Tachometer Coupled to Motor
5
M
DRV101
T
6
Input
(On/Off)
1
4
3 Duty Cycle
Speed Control(1)
R1
R2
NOTE: (1) Select R1/R2 ratio based on tachometer output voltage.
FIGURE 17. Constant Speed Motor Control.
+40V
5
M
DC
Motor
6
Open circuit will
provide 3.4V
“on” signal
DRV101
1
4
2
40kΩ
Speed Control Input
0V to +10V
+15V
3 Duty Cycle
Adjust
Delay Adjust
0.5µF
1kΩ
+15V
22kΩ
470kΩ
1nF
100kΩ
Frequency In
2N2222
T
VOUT
One-Shot
47kΩ
10kΩ
AC
Tachometer
VFC32
Coupled to Motor
–15V
5nF
NP0
FIGURE 18. DC Motor Speed Control Using AC Tachometer.
16
DRV101
www.ti.com
SBVS008B
Only one DRV101 is turned
on at sequence time
Phase 2
Stepper
Logic In
DRV101
+VS
M
Phase 1
Stepper
Logic In
DRV101
Phase 3
Stepper
Logic In
DRV101
FIGURE 19. Three-Phase Stepper Motor Driver Provides High-Stepping Torque.
VS
5
Lamp
DRV101
VS = +9V to +60V
6
R1
1
R2
Select R1 and R2 to divide
down VS to 5.5V max.
For example: with VS = 60V
R1 = 11kΩ, R2 = 1kΩ
VIN =
1kΩ
• 60V = 5V
1kΩ + 11kΩ
4
3
R3
4.87kΩ
C1
20µF
Duty Cycle Adjust
after soft start
+
4.3V
DIN5229
Sets start-up
duty cycle
R4
4.87kΩ
FIGURE 20. Soft-Start Circuit for Incandescent Lamps and Other Sensitive Loads.
DRV101
SBVS008B
www.ti.com
17
+12V
5
20Ω
(10W)
DRV101
P-Channel
MOSFET
IRF4905
6
12V
70A
Load
4
FIGURE 21. High Power, High-Side Driver.
+12V
1.4kΩ
12Ω
(20W)
5
1
Load
DRV101
N-Channel
MOSFET
IRFZ48N
6
1kΩ
12V
50A
Out
4
2
3
CD(1)
RPWM(2)
NOTES: (1) CD controls “OFF” time (turn-on delay). (2) Duty cycle is inverted.
FIGURE 22. High Power, Time Delay, Low-Side Driver.
VS
+12V
Load
120Ω
(2W)
750Ω
5
2N3725A
DRV101
6
2N3725A
480V
27A
N-Channel
IGBT
IRGPC50F
MPSA56
4
NOTE: Duty cycle is inverted. For example, to achieve 25% duty cycle, program 75%.
FIGURE 23. Very High Power, Low-Side Driver.
18
DRV101
www.ti.com
SBVS008B
+170V
0.1µF
2.7kΩ
200Ω
5
2N3725A
DRV101
+5V
1
6
6
+
DCP010512
12V
–
2
5
MPSA56
1
P-Channel
MOSFET
IRF9640
0.1µF
Control
In
4
2kΩ
4N32
Optocoupler
2
CD
Load
3
RPWM
FIGURE 24. Isolated High-Side Driver.
DRV101
SBVS008B
www.ti.com
19
Revision History
DATE
REVISION
5/09
B
PAGE
SECTION
1
Front Page
11
Package Mounting
DESCRIPTION
Updated front page appearance.
Changed Figure 9 to show TI package designator.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
20
DRV101
www.ti.com
SBVS008B
PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
DRV101F
OBSOLETE
DDPAK/
TO-263
KTW
7
DRV101F/500
ACTIVE
DDPAK/
TO-263
KTW
7
DRV101FKTWT
ACTIVE
DDPAK/
TO-263
KTW
DRV101FKTWTG3
ACTIVE
DDPAK/
TO-263
DRV101T
ACTIVE
DRV101TG3
ACTIVE
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TBD
Call TI
Call TI
500
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
DRV101F
7
50
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
DRV101F
KTW
7
50
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
DRV101F
TO-220
KVT
7
50
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
DRV101T
TO-220
KVT
7
50
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
DRV101T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DRV101F/500
DDPAK/
TO-263
KTW
7
500
330.0
24.4
DRV101FKTWT
DDPAK/
TO-263
KTW
7
50
330.0
24.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.95
16.5
5.15
16.0
24.0
Q2
10.6
15.6
4.9
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV101F/500
DDPAK/TO-263
KTW
7
500
346.0
346.0
41.0
DRV101FKTWT
DDPAK/TO-263
KTW
7
50
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MPSF015 – AUGUST 2001
KTW (R-PSFM-G7)
PLASTIC FLANGE-MOUNT
0.410 (10,41)
0.385 (9,78)
0.304 (7,72)
–A–
0.006
–B–
0.303 (7,70)
0.297 (7,54)
0.0625 (1,587) H
0.055 (1,40)
0.0585 (1,485)
0.300 (7,62)
0.064 (1,63)
0.045 (1,14)
0.252 (6,40)
0.056 (1,42)
0.187 (4,75)
0.370 (9,40)
0.179 (4,55)
0.330 (8,38)
H
0.296 (7,52)
A
0.605 (15,37)
0.595 (15,11)
0.012 (0,305)
C
0.000 (0,00)
0.019 (0,48)
0.104 (2,64)
0.096 (2,44)
H
0.017 (0,43)
0.050 (1,27)
C
C
F
0.034 (0,86)
0.022 (0,57)
0.010 (0,25) M
B
0.026 (0,66)
0.014 (0,36)
0°~3°
AM C M
0.183 (4,65)
0.170 (4,32)
4201284/A 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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