Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DRV8839 SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 DRV8839 Low-Voltage Dual ½-H-Bridge Driver IC 1 Features 3 Description • The DRV8839 provides a versatile power driver solution for cameras, consumer products, toys, and other low-voltage or battery-powered applications. The device has two independent ½-H-bridge drivers and can drive one DC motor or one winding of a stepper motor, as well as other devices like solenoids. The output stages use N-channel power MOSFETs configured as ½-H-bridges. An internal charge pump generates needed gate-drive voltages. 1 • • • • • • Dual ½-H-Bridge Motor Driver – Drives a DC Motor or One Winding of a Stepper Motor, or Other Loads – Low MOSFET ON-Resistance: HS + LS 280 mΩ 1.8-A Maximum Drive Current Separate Motor and Logic Supply Pins: – 0-V to 11-V Motor-Operating Supply-Voltage – 1.8-V to 7-V Logic Supply-Voltage Separate Motor and Logic Supply Pins Individual ½-H-Bridge Control Input Interface Low-Power Sleep Mode With 120-nA Maximum Combined Supply Current 2.00-mm × 3.00-mm 12-Pin WSON Package The DRV8839 has independent input and enable pins for each ½-H-bridge which allow independent control of each output. Internal shutdown functions are provided for overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature. 2 Applications • The DRV8839 can supply up to 1.8-A of output current. It operates on a motor power supply voltage from 0 V to 11 V and a device power supply voltage of 1.8 V to 7 V. Battery-Powered: – DSLR Lenses – Consumer Products – Toys – Robotics – Cameras – Medical Devices The DRV8839 is packaged in a 12-pin, 2.00-mm × 3.00-mm WSON package (Eco-friendly: RoHS and no Sb/Br). Device Information(1) PART NUMBER DRV8839 PACKAGE WSON (12) BODY SIZE (NOM) 2.00 mm × 3.00 mm (1) For all available packages, see the Orderable Addendum at the end of the datasheet. Simplified Schematic VCC = 1.8 V to 7 V VM = 0 V to 11 V Controller PWM nSLEEP nFAULT DRV8839 Brushed DC Motor or ½ Stepper Motor Driver 1.8A BDC 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8839 SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 7 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ............................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 9 7.4 Device Functional Modes.......................................... 9 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Application .................................................. 12 9 Power Supply Recommendations...................... 14 9.1 Bulk Capacitance .................................................... 14 10 Layout................................................................... 15 10.1 Layout Guidelines ................................................. 15 10.2 Layout Example .................................................... 15 10.3 Thermal Considerations ........................................ 15 11 Device and Documentation Support ................. 17 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 17 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (January 2014) to Revision B • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Original (January 2013) to Revision A Page • Changed Features bullet ........................................................................................................................................................ 1 • Changed motor supply voltage range in Description section ................................................................................................. 1 • Changed Motor power supply voltage range in Recommended Operating Conditions ........................................................ 4 • Added tOCR and tDEAD parameters to Electrical Characteristics .............................................................................................. 5 • Added paragraph to Power Supplies and Input Pins section ............................................................................................... 14 2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 DRV8839 www.ti.com SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 5 Pin Configuration and Functions DSS Package 12-Pin WSON Top View VM VM OUT1 OUT2 GND GND 1 12 2 11 3 GND Thermal Pad 4 10 9 5 8 6 7 VCC nSLEEP IN1 EN1 IN2 EN2 Pin Functions PIN NAME NO. I/O (1) EXTERNAL COMPONENTS OR CONNECTIONS DESCRIPTION POWER AND GROUND GND 5, 6 — Device ground VCC 12 — Device supply Bypass to GND with a 0.1-μF, 6.3-V ceramic capacitor VM 1, 2 — Motor supply Bypass to GND with a 0.1-μF, 16-V ceramic capacitor EN1 9 I Enable 1 Logic high enables OUT1 Internal pulldown resistor EN2 7 I Enable 2 Logic high enables OUT2 Internal pulldown resistor IN1 10 I Input 1 Logic input controls OUT1 Internal pulldown resistor IN2 8 I Input 2 Logic input controls OUT2 Internal pulldown resistor nSLEEP 11 I Sleep mode input Logic low puts device in low-power sleep mode Logic high for normal operation Internal pulldown resistor OUT1 3 O Output 1 OUT2 4 O Output 2 2, 5 — No connection CONTROL OUTPUT Connect to motor winding NO CONNECT NC (1) No connection to these pins Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 3 DRV8839 SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Power supply voltage, VM –0.3 12 V Power supply voltage, VCC –0.3 7 V Digital input pin voltage –0.5 7 V Internally limited A Peak motor drive output current TJ Operating junction temperature –40 150 °C Tstg Storage temperature –60 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions TA = 25°C (unless otherwise noted) MIN VCC Device power supply voltage VM NOM MAX UNIT 1.8 7 V Motor power supply voltage 0 11 V VIN Logic level input voltage 0 5.5 V IOUT H-bridge output current 0 1.8 A fPWM Externally applied PWM frequency 0 250 kHz (1) (1) Power dissipation and thermal limits must be observed. 6.4 Thermal Information DRV8839 THERMAL METRIC (1) DSS (WSON) UNIT 12 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 20 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 °C/W (1) 4 50.4 °C/W 58 °C/W 19.9 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 DRV8839 www.ti.com SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 6.5 Electrical Characteristics TA = 25°C, VM = 5 V, VCC = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT No PWM 40 100 µA 50 kHz PWM 0.8 1.5 mA nSLEEP = 0 V 30 95 nA No PWM 300 500 µA 50 kHz PWM 0.7 1.5 mA 5 25 nA POWER SUPPLY IVM VM operating supply current IVMQ VM sleep mode supply current IVCC VCC operating supply current IVCCQ VCC sleep mode supply current nSLEEP = 0 V VUVLO VCC undervoltage lockout voltage VCC rising 1.8 VCC falling 1.7 V LOGIC-LEVEL INPUTS VIL Input low voltage VIH Input high voltage 0.31 × VCC 0.34 × VCC 0.39 × VCC 0.43 × VCC VHYS Input hysteresis 0.08 × VCC IIL Input low current VIN = 0 IIH Input high current VIN = 3.3 V RPD Pulldown resistance –5 V V V μA 5 μA 50 100 kΩ H-BRIDGE FETS RDS(ON) HS + LS FET on resistance IOFF OFF-state leakage current I O = 800 mA, TJ = 25°C 280 330 mΩ ±200 nA PROTECTION CIRCUITS IOCP Overcurrent protection trip level tOCR Overcurrent protection retry time tDEAD Output dead time tTSD Thermal shutdown temperature 6.6 Timing Requirements 1.9 3.5 A 1 ms 100 Die temperature 150 ns 160 180 °C MIN (1) TA = 25°C, VM = 5 V, VCC = 3 V, RL = 20 Ω (1) MAX UNIT 1 t1 Output enable time 120 ns 2 t2 Output disable time 120 ns 3 t3 Delay time, INx high to OUTx high 120 ns 4 t4 Delay time, INx low to OUTx low 120 ns 5 t5 Output rise time 50 150 ns 6 t6 Output fall time 50 150 ns Not production tested – ensured by design Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 5 DRV8839 SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 www.ti.com INx ENx 3 1 2 4 OUTx OUTx z z 80% 80% 20% 20% 5 6 Figure 1. Timing Requirements 6 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 DRV8839 www.ti.com SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 6.7 Typical Characteristics 1.6 6000 VVM = 1.8 V, VVCC = 1.8 V VVM = 2 V, VVCC = 2 V VVM = 3.5 V, VVCC = 3.5 V VVM = 7 V, VVCC = 7 V 1.2 -40qC 25qC 85qC 125qC 5500 5000 4500 4000 IVMQ (nA) RDS(ON) (HS+LS) (:) 1.4 1 0.8 3500 3000 2500 2000 0.6 1500 1000 0.4 500 0.2 -40 0 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 110 125 1 2 3 Figure 2. RDS(ON) HS + LS vs Temperature 6 7 VVM (V) 8 9 10 11 D002 1000 -40qC 25qC 85qC 125qC 500 450 400 -40qC 25qC 85qC 125qC 900 800 700 350 IVM (uA) IVCCQ (nA) 5 Figure 3. IVMQ vs VVM 550 300 250 200 600 500 400 300 150 100 200 50 100 0 1.5 4 D001 0 2 2.5 3 3.5 4 4.5 VVCC (V) 5 5.5 6 6.5 7 1 2 3 4 5 D003 Figure 4. IVCCQ vs VVCC 6 7 VVM (V) 8 9 10 11 D004 Figure 5. IVM vs VVM (No PWM) 650 -40qC 25qC 85qC 125qC 600 550 IVCC (PA) 500 450 400 350 300 250 200 150 1.5 2 2.5 3 3.5 4 4.5 VVCC (V) 5 5.5 6 6.5 7 D005 Figure 6. IVCC vs VVCC (No PWM) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 7 DRV8839 SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The DRV8839 is an integrated motor driver solution used for brushed motor control. The device integrates two independent ½ H-bridge, and can drive one motor in both directions or two motors in one direction. The output driver block for each ½ H-bridge consists of N-channel power MOSFETs. An internal charge pump generates the gate drive voltages. Protection features include overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature protection. The DRV8839 allows separation of the motor voltage and logic voltage if desired. If VM and VCC are less than 7 V, the two voltages may be connected. The control interface of the DRV8839 uses INx and ENx to control each ½ H-bridge separately. 7.2 Functional Block Diagram 0 to 11V VM VM VM Drives DC motor or 1/2 Stepper 1.8 to 7V VCC Gate Drive Charge Pump OCP OUT1 Step Motor VCC DCM VM Logic IN1 OUT2 Gate Drive OCP EN1 IN2 OverTemp EN2 Osc nSLEEP GND 8 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 DRV8839 www.ti.com SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 7.3 Feature Description 7.3.1 Protection Circuits The DRV8839 is fully protected against undervoltage, overcurrent, and overtemperature events. 7.3.1.1 Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge disables. After approximately 1 ms, the bridge will be re-enabled automatically. Overcurrent conditions on both high-side and low-side devices; a short to ground, supply, or across the motor winding result in an overcurrent shutdown. 7.3.1.2 Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge disables. Operation automatically resumes once the die temperature has fallen to a safe level. 7.3.1.3 Undervoltage Lockout (UVLO) If at any time the voltage on the VCC pin falls below the undervoltage lockout threshold voltage, all circuitry in the device disables and internal logic resets. Operation resumes when VCC rises above the UVLO threshold. Table 1. Device Protection FAULT CONDITION ERROR REPORT INTERNAL CIRCUITS H-BRIDGE RECOVERY VCC undervoltage (UVLO) VCC < VUVLO None Disabled Disabled VCC > VUVLO Overcurrent (OCP) IOUT > IOCP None Disabled Operating tOCR Thermal shutdown (TSD) TJ > TTSD None Disabled Operating TJ < TTSD – THYS 7.4 Device Functional Modes The DRV8839 is active when the nSLEEP pin is set to a logic high. When in sleep mode, the ½ H-bridge FETs are disabled (High-Z). Table 2. Device Operating Modes OPERATING MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Operating nSLEEP high Operating Operating Sleep mode nSLEEP low Disabled Disabled Fault encountered Any fault condition met Disabled See Table 1 7.4.1 Bridge Control The DRV8839 is controlled using separate enable and input pins for each ½-H-bridge. The following table shows the logic for the DRV8839: Table 3. Bridge Control ENx INx OUTx 0 X Z 1 0 L 1 1 H Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 9 DRV8839 SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 www.ti.com 7.4.2 Sleep Mode If the nSLEEP pin reaches a logic-low state, the DRV8839 enters a low-power sleep mode. In this state all unnecessary internal circuitry powers down. 7.4.3 Motor Connections If a single DC motor connects to the DRV8839, it is connected between the OUT1 and OUT2 pins as shown in Figure 7: OUT1 DCM OUT2 Figure 7. Single DC Motor Connection Motor operation is controlled as follows: Table 4. Single DC Motor Operation (1) (2) 10 EN1 EN2 IN1 IN2 OUT1 0 X X X Z OUT2 See (2) Z (1) MOTOR OPERATION Off (coast) X 0 X X See 1 1 0 0 L L Off (coast) Brake 1 1 0 1 L H Reverse 1 1 1 0 H L Forward 1 1 1 1 H H Brake State depends on EN2 and IN2, but does not affect motor operation because OUT1 is tri-stated. State depends on EN1 and IN1, but does not affect motor operation because OUT2 is tri-stated. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 DRV8839 www.ti.com SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 Two DC motors can be connected to the DRV8839. In this mode, it is not possible to reverse the direction of the motors; they turn only in one direction. The connections are shown in Figure 8: OUT1 DCM OUT2 DCM Figure 8. Dual DC Motor Connection Motor operation is controlled as follows: Table 5. Dual DC Motor Operation ENx INx OUTx MOTOR OPERATION 0 X Z Off (coast) 1 0 L Brake 1 1 H Forward Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 11 DRV8839 SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DRV8839 is used in one control applications. 8.2 Typical Application The following design is a common application of the DRV8839. VM VM VCC OUT1 10 µF BDC 0.1 µF VCC OUT2 IN1 EN1 IN2 Controller EN2 nSLEEP GND PPAD Figure 9. Typical Application Schematic 8.2.1 Design Requirements The design requirements are shown in Table 6. Table 6. Design Requirements DESIGN PARAMETER 12 REFERENCE EXAMPLE VALUE Motor voltage VM 5V Motor RMS current IRMS 0.3 A Motor startup current ISTART 0.6 A Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 DRV8839 www.ti.com SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 8.2.2 Detailed Design Procedure The following design procedure can be used to configure the DRV8839 in a brushed motor application. 8.2.2.1 Motor Voltage The appropriate motor voltage depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. 8.2.2.2 Low-Power Operation When entering sleep mode, TI recommends setting all inputs as a logic low to minimize system power. 8.2.2.3 Application Curves The following scope captures show a typical motor startup and running. Channel 1 is VM, Channel 2 is IN1, Channel 3 is IN2, and Channel 4 is motor current. the motor used is a NMB Technologies, PPN7PA12C1. Figure 10. Motor Startup With VCC = 3.3 V, VM = 5 V Figure 11. Motor Running With VCC = 3.3 V, VM = 5 V Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 13 DRV8839 SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 www.ti.com 9 Power Supply Recommendations The input pins can drive within their recommended operating conditions with or without the VCC and VM power supplies present. No leakage current path exists to the supply. There is a weak pulldown resistor (approximately 100 kΩ) to ground on each input pin. VCC and VM can be applied and removed in any order. When VCC is removed, the device enters a low-power state and draws very little current from VM. If the supply voltage is between 1.8 V and 7 V, VCC and VM can connect together. The VM voltage supply does not have any undervoltage lockout protection (UVLO), so as long as VCC > 1.8 V, the internal device logic remains active. This means that the VM pin voltage may drop to 0 V, however, the load may not be sufficiently driven at low VM voltages. 9.1 Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The required amount of local capacitance depends on a variety of factors, including: • The highest current required by the motor system • The power supply’s capacitance and ability to source current • The amount of parasitic inductance between the power supply and motor system • The acceptable voltage ripple • The type of motor used (brushed DC, brushless DC, stepper) • The motor braking method Power Supply Parasitic Wire Inductance Motor Drive System VM + ± + Motor Driver GND Local Bulk Capacitor IC Bypass Capacitor Figure 12. Bulk Capacitance 14 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 DRV8839 www.ti.com SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 10 Layout 10.1 Layout Guidelines The VCC pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1-μF rated for VCC. This capacitor should be placed as close to the VCC pin as possible with a thick trace or ground plane connection to the device GND pin. The VCC pin must be bypassed to ground using an appropriate bulk capacitor. This component may be an electrolytic and should be located close to the DRV8839. 10.2 Layout Example 10 µF 2.2 µF VM VCC VM nSLEEP OUT1 IN1 OUT2 EN1 GND IN2 GND EN2 Figure 13. Layout Recommendation 10.3 Thermal Considerations The DRV8839 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device disables until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. 10.3.1 Power Dissipation The power dissipation of the DRV8839 is a function of RMS motor current and the each output’s FET resistance (RDS(ON)) as seen in Equation 1: Power ≈ IRMS² × (High-Side RDS(ON) + Low-Side RDS(ON) (1) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 15 DRV8839 SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 www.ti.com Thermal Considerations (continued) For this example, VVM = 1.8 V, VVCC = 1.8 V, the ambient temperature is 35°C, and the junction temperature reaches 65°C. At 65°C, the sum of RDS(ON) is about 1 Ω. With an example motor current of 0.8 A, the dissipated power in the form of heat will be 0.8 A² × 1 Ω = 0.64 W. The temperature that the DRV8839 reaches will depend on the thermal resistance to the air and PCB. It is important to solder the device PowerPAD to the PCB ground plane, with vias to the top and bottom board layers, in order dissipate heat into the PCB and reduce the device temperature. In the example used here, the DRV8839 had an effective thermal resistance RθJA of 47°C/W, and as seen in Equation 2: TJ = TA + (PD × RθJA) = 35°C + (0.64 W × 47°C/W) = 65°C 16 Submit Documentation Feedback (2) Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 DRV8839 www.ti.com SLVSBN4B – JANUARY 2013 – REVISED DECEMBER 2015 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • PowerPAD™ Thermally Enhanced Package Application report SLMA002 • PowerPAD™ Made Easy SLMA004 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DRV8839 17 PACKAGE OPTION ADDENDUM www.ti.com 28-Oct-2014 PACKAGING INFORMATION Orderable Device Status (1) DRV8839DSSR ACTIVE Package Type Package Pins Package Drawing Qty WSON DSS 12 3000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Op Temp (°C) Device Marking (4/5) -40 to 85 8839 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Oct-2014 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8839DSSR Package Package Pins Type Drawing WSON DSS 12 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 180.0 8.4 Pack Materials-Page 1 2.25 B0 (mm) K0 (mm) P1 (mm) 3.25 1.05 4.0 W Pin1 (mm) Quadrant 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8839DSSR WSON DSS 12 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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