ALSC AS8C803601 Three chip enables for simple depth expansion Datasheet

256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™ Feature
3.3V I/O, Burst Counter
Pipelined Outputs
AS8C803601
AS8C801801
Address and control signals are applied to the SRAM during one clock
cycle,
and two cycles later the associated data cycle occurs, be it read or write.
256K x 36, 512K x 18 memory configurations
◆
The AS8C803601/801801 contain data I/O, address and control signal
Supports high performance system speed - 150MHz
registers. Output enable is the only asynchronous signal and can be
(3.8ns Clock-to-Data Access)
◆
ZBTTM Feature - No dead cycles between write and read cycles used to disable the outputsat any given time.
◆ Internally synchronized output buffer enable eliminates the
A Clock Enable(CEN) pin allows operation of the to AS8C803601/ 801801
be suspended as long as necessary. All synchronous inputs are ignored when
need to control OE
◆
(CEN)is high and the internal device registers will hold their previous values.
Single R/W (READ/WRITE) control pin
◆
There are three chip enable pins (CE1, CE2, CE2) that allow the user
Positive clock-edge triggered address, data, and control
to
deselect
the device when desired. If anyone of these three are not asserted
signal registers for fully pipelined applications
◆
when ADV/LD is low, no new memoryoperation can be initiated. However,
4-word burst capability (interleaved or linear)
◆ Individual byte write (BW1 - BW4) control (May tie active)
any pending data transfers (reads or writes) will be completed. The data bus
◆
will tri-state two cycles after chip is deselected or a write is initiated.
Three chip enables for simple depth expansion
◆
TheAS8C803601/801801 have an on-chip burst counter. In the burst
3.3V power supply (±5%)
◆
mode,the AS8C803601/801801 can provide fourcycles of data for a single
3.3V I/O Supply (V DDQ)
◆
address presented to the SRAM. The order of the burst sequence is
Power down controlled by ZZ input
◆
defined by the LBO input pin. The LBO pin selects between linear and
Packaged in a JEDEC standard 100-pin plastic thin quad
interleaved burst sequence. The ADV/LD signal is used to load a new
flatpack (TQFP).
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
Description
The AS8C803601/801801 SRAM utilize IDT's latest high-performance
The AS8C803601/801801 are3.3V high-speed 9,437,184 bit
CMOS process, andare packaged ina JEDEC Standard 14mm x 20mm 100(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus pin thin plastic quad flatpack (TQFP) .
cycles when turning the bus around between reads and writes, or writes and
TM
reads. Thus, they have been given the name ZBT
, or Zero Bus Turnaround.
Features
◆
Pin Description Summary
A0-A18
Address Inputs
Input
Synchronous
CE1, CE2, CE2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/W
Read/Write S ignal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/LD
Advance burst address / Load new address
Input
Synchronous
LBO
Linear / In terleaved B urst Order
Input
Static
ZZ
Sleep Mode
Input
Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O
Synchronous
VDD, V DDQ
Core P ower, I/ O Power
Supply
Static
VSS
Ground
Supply
Static
5304 tbl 01
SEPTEMBER 2010
1
DSC-5304/07
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial Temperature Range
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A 0-A 18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK, ADV/LD lo w, CEN low, and true chip e nables.
ADV/LD
Advance / Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/ LD
is sampled hig h then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/LD is s ampled high.
R/W
Read / Write
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
CEN
Clock Enable
I
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous
inputs, including clock are ignored and outputs re main unchanged. The effect of CEN
sampled high on the device outp uts is as if the low to hig h clock transition did not occur.
For normal operation, CEN must be s ampled low at rising edge of clock.
BW1-BW4
Individual B yte
Write E nables
I
LOW
Synchro nous byte write enables. Each 9-bit byte has its own active low byte write enable.
On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write
signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate
byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if
always doing write to the entire 36-bit word.
CE1, CE2
Chip E nables
I
LOW
Synchronous active low c hip e nable. CE1 an d CE2 are used with CE2 to e nable the AS8C
803601/ 801801 (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD lo w at the
rising edge of clock, initiates a deselect cycle. The ZBTTM has a two cycle deselect, i.e.,
the data bus will tri-state two clock cycles after deselect is initiated.
CE2
Chip Enable
I
HIGH
Synchrono us active high c hip e nable. CE 2 is used with CE1 and CE2 to enable the chip.
CE2 has inverted po larity but otherwise identical to CE1 and CE2.
CLK
Clock
I
N/A
This i s the c lock input to theAS8C803601/801801. Except for OE, all timing references for the
device are made with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Inp ut/Output
I/O
N/A
Synchro nous data i nput/output (I/O) p ins. B oth the d ata i nput path and d ata output p ath a re
registered and triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is selected.
When LBO is low the Line ar burst sequence is selected. LBO i s a static input and it m ust
not change during device operation.
OE
Output Enable
I
LOW
Asynchronous o utput e nable. OEm ust b e lo w to read data fromtheAS8C803601/801801.When
OE is high the I/O pins are in a high-impedance state. OE does not need to be actively
controlled for read and write cycles. In no rmal operation, OE can be tied low.
ZZ
Sleep Mode
I
N/A
Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
AS8C803601/801801 to its lowest p ower consumption level.Data retention is guaranteed in
Sleep Mode.
V DD
Power Supply
N/A
N/A
3.3V core power supply.
VDDQ
Power Supply
N/A
N/A
3.3V I/O Supply.
V SS
Ground
N/A
N/A
Ground.
5304tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial and Industrial Temperatur e Ranges
Functional Block Diagram
LBO
Address A [0:18]
512x18 BIT
MEMORY ARRAY
D
Q
Address
D
Q
Control
CE1, CE2, CE2
R/W
Input Register
CEN
ADV/LD
BWx
D
DI
Q
DO
Control Logic
Clk
Mux
Sel
D
Clk
Clock
Output Register
Q
Gate
OE
5304 drw 01
Data I/O [0:15],
I/O P[1:2]
6.42
3
,
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
512x18 BIT
MEMORY ARRAY
Address A [0:18]
D
Q
Address
D
Q
Control
CE1, CE2, CE2
R/W
Input Register
CEN
ADV/LD
BWx
D
DI
Q
DO
Control Logic
Clk
Mux
Sel
D
Clk
Clock
Output Register
Q
Gate
OE
5304 drw 01
Data I/O [0:15],
I/O P[1:2]
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Core S upply Voltage
3.135
3.3
3.465
V
VDDQ
I/O S upply Voltage
3.135
3.3
3.465
V
VSS
Supply Voltage
0
0
0
V
VIH
Input High Voltage - Inputs
2.0
____
VDD+0.3
V
VIH
Input High Voltage - I/O
2.0
____
VDDQ+0.3
V
VIL
Input L ow V oltage
-0.3(1)
____
0.8
V
NOTES:
1. VIL (min.) = –1.0V for pulse width less than t
5304 tbl 04
CYC /2,
once per cycle.
6.42
4
,
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial and Industrial Temperatur e Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Ambient
Temperature(1)
VSS
VDD
V DDQ
Commercial
0° C to +70° C
0V
3.3V±5%
3.3V±5%
Industrial
-40°C to +85°C
0V
3.3V±5%
3.3V±5%
5304 tbl 05
NOTES:
1. During production testing, the case temperature equals the ambient temperature
.
CE2
BW4
BW3
BW2
BW1
CE2
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
NC(2)
A17
A8
A9
A6
A7
CE1
Pin Configuration - 256K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD(1)
VDD
VDD(1)
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VDD(1)
VDD
ZZ
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
A5
A4
A3
A2
A1
A0
DNU(3)
DNU(3)
VSS
VDD
DNU(3)
DNU(3)
A10
A11
A12
A13
A14
A15
A16
5304 drw 02
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage≥isVIH.
2. Pin 84 is reserved for a future 16M.
3. DNU= Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The
current die revision allows these pins to be left unconnected, tied LOW (V
6.42
5
SS),
or tied HIGH (V
DD).
,
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
CE2
NC
NC
BW2
BW1
CE2
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
NC(2)
A18
A8
A9
A6
A7
CE1
Pin Configuration - 512K x 18
Symbol
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
2
79
3
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VDD(1)
VDD
VDD(1)
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
4
78
77
5
6
76
75
7
74
8
73
9
10
72
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
24
58
57
25
56
26
55
27
54
28
53
29
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD(1)
VDD
ZZ
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
52
51
30
,
A11
A12
A13
A14
A15
A16
A17
LBO
A5
A4
A3
A2
A1
A0
DNU(3)
DNU(3)
VSS
VDD
DNU(3)
DNU(3)
100 TQFP Capacitance(1)
CI/O
I/O Capacitance
VTERM(3,6)
Terminal Voltage with
Respect to GND
-0.5 to V DD
V
VTERM(4,6)
Terminal Voltage with
Respect to GND
-0.5 to V DD +0.5
V
VTERM(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
V
Commercial
Operating Temperature
-0 to +70
o
C
-40 to + 85
o
C
TBIAS
Temperature
Under B ias
-55 to + 125
o
C
TSTG
Storage
Temperature
-55 to + 125
o
C
PT
Power Di ssipation
2.0
IOUT
DC Output Cu rrent
50
Max.
Unit
Symbol
VIN = 3dV
5
pF
CIN
Input Capacitance
VOUT = 3dV
7
pF
CI/O
I/O Capacitance
5304 t bl 07
119 BGA Capacitance
CIN
Input Capacitance
CI/O
I/O Capacitance
mA
Conditions
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
Parameter(1)
Conditions
Max.
Unit
VIN = 3 dV
TBD
pF
VOUT = 3 dV
TBD
pF
5304 t bl 0 7b
(TA = +25° C, f = 1.0MHz)
Parameter(1)
W
(TA = +25° C, f = 1.0MHz)
Conditions
(1)
Symbol
(7)
165 fBGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Input Capacitance
V
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V DDQ during power
supply ramp up.
7. During production testing, the case temperature equals T A.
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to V
DD as long as
the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU= Do not use. Pins 38, 39, 42 and 43 are reserved for respective
JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows
these pins to be left unconnected, tied LOW (V SS), or tied HIGH (V DD).
CIN
-0.5 to +4.6
5304 tbl 06
Top View
100 TQFP
Parameter(1)
Unit
Terminal Voltage with
Respect to GND
Industrial
Operating Temperature
5304 drw 02a
Commercial &
Industrial
VTERM(2)
TA
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Symbol
Rating
pF
5304 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
6
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial Temperatur e Range
Synchronous Truth Table(1)
CEN
R/W
Chip(5)
Enable
ADV/LD
BWx
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(2 cycles l ater)
L
L
Select
L
Valid
External
X
LOAD WRITE
D(7)
L
H
Select
L
X
External
X
LOAD READ
Q(7)
L
X
X
H
Valid
Internal
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)(2)
D(7)
L
X
X
H
X
Internal
LOAD RE AD /
BURST RE AD
BURST RE AD
(Advance burst counter)(2)
Q(7)
L
X
Deselect
L
X
X
X
DESELECT o r STOP (3)
HiZ
L
X
X
H
X
X
DESELECT / NOOP
NOOP
HiZ
H
X
X
X
X
X
X
SUSPEND(4)
Previous Value
5304 tbl 08
NOTES:
1. L = V IL, H = V IH, X = Don’t Care.
2. When ADV/ LD signal is sampled high, the internal burst counter is incremented. The R/ W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/
W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either ( CE1, or CE2 is sampled high or CE 2 is sampled low) and ADV/ LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/Os
remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE 2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
OPERATION
R/W
BW 1
BW 2
BW 3(3)
BW 4(3)
H
X
X
X
X
L
L
L
L
L
L
L
H
H
H
WRITE BYTE 2 (I/O[8:15], I/OP2)(2)
L
H
L
H
H
WRITE BYTE 3 (I/O[16:23], I/OP3)(2,3)
L
H
H
L
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4)
L
H
H
H
L
NO
L
H
H
H
H
READ
WRITE ALL BYTES
WRITE BYTE 1 (I/O[0:7], I/OP1)
RITE
(2)
W
5304 tbl 09
NOTES:
1. L = V IL, H = V IH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
7
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial Temperature Range
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth A ddress (1)
1
1
1
0
0
1
0
0
5304 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
Fourth A ddress (1)
1
1
0
0
0
1
1
0
5304 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
A29
A30
A31
A32
A33
A34
A35
A36
A37
C29
C30
C31
C32
C33
C34
C35
C36
C37
D/Q27
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
CLOCK
(2)
ADDRESS
(A0 - A17)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
I/O [0:31], I/O P[1:4]
5304 drw 03
NOTES:
1. This assumes CEN, CE1, CE 2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
88
,
99AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial Temperatur e Range
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
Cycle
Address
R/W
ADV/LD
CE (1)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Load read
n+1
X
X
H
X
L
X
X
X
Burst read
n+2
A1
H
L
L
L
X
L
Q0
Load read
n+3
X
X
L
H
L
X
L
Q0+1
n+4
X
X
H
X
L
X
L
Q1
NOOP
n+5
A2
H
L
L
L
X
X
Z
Load read
n+6
X
X
H
X
L
X
X
Z
Burst read
n+7
X
X
L
H
L
X
L
Q2
Deselect o r STOP
n+8
A3
L
L
L
L
L
L
Q2+1
Load write
n+9
X
X
H
X
L
L
X
Z
Burst write
n+10
A4
L
L
L
L
L
X
D3
Load write
n+11
X
X
L
H
L
X
X
D3+1
n+12
X
X
H
X
L
X
X
D4
NOOP
n+13
A5
L
L
L
L
L
X
Z
Load write
n+14
A6
H
L
L
L
X
X
Z
Load read
n+15
A7
L
L
L
L
L
X
D5
Load write
n+16
X
X
H
X
L
L
L
Q6
Burst write
n+17
A8
H
L
L
L
X
X
D7
Load read
n+18
X
X
H
X
L
X
X
D7+1
Burst read
n+19
A9
L
L
L
L
L
L
Q8
Load write
Deselect o r STOP
Deselect o r STOP
5304tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Read Operation(1)
Cycle
Address
R/W
ADV/LD
CE (2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
X
Clock
n+2
X
X
X
X
X
X
L
Q0
Contents of Address A 0 Re ad Out
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
9
S
etup alid
S
V
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Burst Read
Commercial Temperature Range
Operation(1)
Cycle
Address
R/W
ADV/LD
CE (2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
H
X
L
X
X
X
Clock Setup Valid, Advance Counter
n+2
X
X
H
X
L
X
L
Q0
Address A 0 Read Out, Inc. Count
n+3
X
X
H
X
L
X
L
Q0+1
Address A 0+1 Read O ut, Inc . Co unt
n+4
X
X
H
X
L
X
L
Q0+2
Address A 0+2 Read Out, Inc . Co unt
n+5
A1
H
L
L
L
X
L
Q0+3
Address A 0+3 Re ad Out, Load A 1
n+6
X
X
H
X
L
X
L
Q0
Address A 0 Read Out, Inc. Count
n+7
X
X
H
X
L
X
L
Q1
Address A 1 Read Out, Inc. Count
n+8
A2
H
L
L
L
X
L
Q1+1
Address A 1+1 Read Out, Lo ad A 2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
Write Operation(1)
Cycle
Address
R/W
ADV/LD
CE (2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
X
Clock S etup Valid
n+2
X
X
X
X
L
X
X
D0
Write to Address A0
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
Burst Write Operation(1)
Cycle
Address
R/W
ADV/LD
CE (2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
H
X
L
L
X
X
Clock S etup Valid, Inc. Count
n+2
X
X
H
X
L
L
X
D0
Address A 0 Write, Inc. Count
n+3
X
X
H
X
L
L
X
D0+1
Address A 0+1 Write, Inc. Count
n+4
X
X
H
X
L
L
X
D0+2
Address A 0+2 Write, Inc. Count
n+5
A1
L
L
L
L
L
X
D0+3
Address A 0+3 Write, Load A 1
n+6
X
X
H
X
L
L
X
D0
Address A 0 Write, Inc. Count
n+7
X
X
H
X
L
L
X
D1
Address A 1 Write, Inc. Count
n+8
A2
L
L
L
L
L
X
D1+1
Address A 1+1 Write, Load A 2
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
10 10
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial Temperatur e Range
(1)
Read Operation with Clock Enable Used
Cycle
Address
R/W
ADV/LD
CE (2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
X
X
H
X
X
X
Clock n+1 I gnored
n+2
A1
H
L
L
L
X
X
X
Clock
n+3
X
X
X
X
H
X
L
Q0
Clock Ignored, Data Q 0 is on the bus.
n+4
X
X
X
X
H
X
L
Q0
Clock Ignored, Data Q 0 is on the bus.
n+5
A2
H
L
L
L
X
L
Q0
Address A 0 Read o ut (bus trans.)
n+6
A3
H
L
L
L
X
L
Q1
Address A 1 R ead o ut (bus trans.)
n+7
A4
H
L
L
L
X
L
Q2
Ad dress A2 Read o ut (bus trans.)
V alid
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
Write Operation with Clock Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE (2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup.
n+1
X
X
X
X
H
X
X
X
Clock n+ 1 Ignored.
n+2
A1
L
L
L
L
L
X
X
Clock Valid.
n+3
X
X
X
X
H
X
X
X
Clock Ignored.
n+4
X
X
X
X
H
X
X
X
Clock Ignored.
n+5
A2
L
L
L
L
L
X
D0
Write Data D 0
n+6
A3
L
L
L
L
L
X
D1
Write Data D 1
n+7
A4
L
L
L
L
L
X
D2
Write Data D 2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
11
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial Temperature Range
Read Operation with Chip Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE (2)
CEN
BWx
OE
I/O(3)
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
?
Deselected.
n+2
A0
H
L
L
L
X
X
Z
Address and Control meet setup
n+3
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+4
A1
H
L
L
L
X
L
Q0
Address A 0 Read o ut. Load A 1.
n+5
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+6
X
X
L
H
L
X
L
Q1
Address A 1 Re ad o ut. De selected.
n+7
A2
H
L
L
L
X
X
Z
Address and control meet setup.
n+8
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+9
X
X
L
H
L
X
L
Q2
Address A 2 Read out. Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE (2)
CEN
BWx
OE
I/O(3)
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
?
Deselected.
n+2
A0
L
L
L
L
L
X
Z
Address and Control meet setup
n+3
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+4
A1
L
L
L
L
L
X
D0
Address D0 Write in. Load A 1.
n+5
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+6
X
X
L
H
L
X
X
D1
Address D1 Write in. Deselected.
n+7
A2
L
L
L
L
L
X
Z
Address and control meet setup.
n+8
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+9
X
X
L
H
L
X
X
D2
Address D2 Write in. Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
12
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial Temperature Range
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Industrial Temperature Range)
150MHz
Symbol
Parameter
133MHz
100MHz
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
6.7
____
7.5
____
10
____
ns
(1)
150
____
133
____
100
MHz
2.2
____
3.2
____
ns
____
ns
Clock Frequency
____
(2)
tCH
Clock High Pulse Width
2.0
____
tCL(2)
Clock Low Pulse Width
2.0
____
2.2
____
3.2
tF
Output Parameters
tCD
Clock High to Valid Data
____
3.8.
____
4.2
____
5
ns
tCDC
1.5
____
1.5
____
ns
1.5
____
1.5
____
ns
Clock High to Data Change
1.5
____
(3,4,5)
Clock H igh to Ou tput A ctive
1.5
____
(3,4,5)
tCHZ
Clock High to Data High-Z
1.5
3
1.5
3
1.5
3.3
ns
tOE
Output Enable Access Time
____
3.8
____
4.2
____
5
ns
0
____
0
____
0
____
ns
____
3.8
____
4.2
____
5
ns
tCLZ
tOLZ
Output Enable Low to Data Active
tOHZ(3,4)
Output Enable High to Data High-Z
(3,4)
Set Up Times
tSE
Clock E nable S etup Ti me
1.5
____
1.7
____
2.0
____
ns
tSA
Address Setup Time
1.5
____
1.7
____
2.0
____
ns
tSD
Data In S etup Time
1.5
____
1.7
____
2.0
____
ns
tSW
Read/Write (R/ W) S etup Time
1.5
____
1.7
____
2.0
____
ns
tSADV
Advance/Load (ADV/LD) S etup Time
1.5
____
1.7
____
2.0
____
ns
tSC
Chip Enable/Select Setup Time
1.5
____
1.7
____
2.0
____
ns
tSB
Byte Write E nable (BWx) Setup Time
1.5
____
1.7
____
2.0
____
ns
tHE
Clock E nable Hold Time
0.5
____
0.5
____
0.5
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
ns
tHD
Data In H old Time
0.5
____
0.5
____
0.5
____
ns
tHW
Read/Write (R/ W) Ho ld Time
0.5
____
0.5
____
0.5
____
ns
tHADV
Advance/Load (ADV/LD) H old Time
0.5
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
0.5
____
ns
tHB
Byte Write E nable (BWx) Hold Time
0.5
____
0.5
____
0.5
____
ns
Hold T imes
5304 tbl 24
NOTES:
1. tF = 1/t CYC.
2. Measured as HIGH above 0.6V DDQ and LOW below 0.4V DDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that t CHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than
tCHZ ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
13
14
DATAOUT
OE
BW1 - BW4
CE1, CE2
(2)
ADDRESS
R/W
CEN
CLK
A1
tSADV
tHA
tHW
tHE
tCLZ
tHC
Pipeline
Read
tSC
A2
tSA
tSW
tSE
tCD
Pipeline
Read
Q(A1)
tHADV
tCH
tCYC
tCDC
tCL
Q(A
2)
O1(A2)
,
O2(A2)
Q(A
2+1)
Q(A2+2)
(CEN high, eliminates
current L-H clock edge)
Burst Pipeline Read
tCD
Q(A2+2)
tCDC
Q(A2+3)
tCHZ
Q(A
O1(A2)
2)
5304 drw 06
(Burst Wraps around
to initial state)
tCYC
CLK
tCH
tSE
tCL
tHE
CEN
tSADV
tHADV
ADV/LD
tSW
tHW
R/W
tSA
A1
ADDRESS
tHA
A2
tSC
CE1, CE2
tHC
(2)
tSB
tHB
BW1 - BW4
OE
tSD
DATAIN
(CEN high, eliminates
current L-H clock edge)
tHD
D(A1)
Pipeline
Write
D(A2)
D(A2+1)
tSD
tHD
D(A2+2)
(Burst Wraps around
to initial state)
D(A2+3)
D(A2)
Burst Pipeline Write
Pipeline
Write
5304 drw 07
.
CLK
tCH
tSE
tCL
tHE
CEN
tSADV
tHADV
ADV/LD
tSW
tHW
R/W
tSA
A1
ADDRESS
tHA
A2
A3
A5
A4
A6
A7
D(A4)
D(A5)
A8
A9
tSC
tHC
CE1, CE2(2)
tSB
tHB
BW1 - BW4
OE
tSD tHD
D(A2)
DATAIN
Write
tCHZ
tCD
Write
tCLZ
Read
Q(A6)
Q(A3)
Q(A1)
DATAOUT
tCDC
Read
Q(A7)
Read
5304 drw 08
,
NOTES:
1. Q (A1) represents the first output from the external address A 1. D (A2) represents the input data to the SRAM corresponding to address A 2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE 2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of Combined Read and Write Cycles(1,2,3)
tCYC
,
tCYC
CLK
tCH
tSE
tCL
tHE
CEN
tSADV
tHADV
ADV/LD
tSW
tHW
R/W
tSA
ADDRESS
A1
tHA
A2
tSC
A4
A3
A5
tHC
CE1, CE2(2)
tSB
BW1 - BW4
tHB
B(A2)
OE
tSD tHD
DATAIN
tCHZ
tCDC
tCD
Q(A1)
DATAOUT
D(A2)
Q(A1)
Q(A3)
tCLZ
5304 drw 09
DATAOUT
DATAIN
OE
BW1 - BW4
CE1, CE2
(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
A1
tSADV
tHW
tHE
tSC
tCLZ
tCD
tHC
tHA
A2
tSA
tSW
tSE
Q(A1)
tHADV
tCH
tCYC
tCDC
tCHZ
tHB
Q(A2)
tSB
A3
tCL
D(A3)
tSD tHD
A4
Q(A4)
A5
5304 drw 10
,
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
19
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT™
Commercial Temperatur e Range
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
Valid
DATAOUT
,
NOTE:
1. A read operation is assumed to be in progress.
5304 drw 11
2
25
ORDERING INFORMATION
Alliance
Organization
VCC
Range
AS8C803601-QC150N
256K x 36
3.1 - 3.4V
100 pin TQFP
Comercial 0 - 70C
150
AS8C801801-QC150N
512K x 18
3.1 - 3.4V
100 pin TQFP
Comercial 0 - 70C
150
Package
Speed
Mhz
Operating Temp
1. EMLSI Memory
2. Device Type
3. Density
4. Function
5. Technology
6. Operating Voltage
11. Power
10. Speed
9. Package
8. Version
7. Organization
PART NUMBERING SYSTEM
Device
AS8C
Sync.
SRAM prefix
80 = 8M
Conf.
18= x18
36 = x36
Mode
01= ZBT
00 = Pipelined
25 = Flow- Thru
Package
Q = 100 Pin TQFP
Operating Temp
0 ~ 70C
N
Speed
150MHz
N= Leadfree
ORDERING INFORMATION
Alliance
VCC
Range
Organization
AS6C8016A -55ZIN
512K x 16
AS6C8016A -55BIN
Package
2.7 - 5.5V
512K x 16
2.7 - 5.5V
Speed
ns
Operating Temp
44pin TSOP II
Industrial ~ -40 C - 85 C
55
48ball FBGA
Industrial ~ -40 C - 85 C
55
PART NUMBERING SYSTEM
AS6C
8016
-55
Device Number
low power
SRAM prefix
®
Alliance Memory, Inc.
551 Taylor way, suite#1
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS8C803601/801801
Document Version: v. 1.0
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any
time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any
product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or
warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's
Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in
life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of
Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all
claims arising from such use.
80 = 8M
16 = x16
Access
Time
X
X
Package Option
Temperature Range
Z - 44pin TSOP
I = Industrial
B = 48ball TFBGA
(-40 to + 85 C)
N
N = Lead Free
RoHS
compliant part