GS1881, GS4881, GS4981 Monolithic Video Sync Separators DATA SHEET FEATURES DESCRIPTION • noise tolerant odd/even flag, back porch and horizontal sync pulse The GS1881, GS4881 and GS4981 are general purpose sync separators for use in a wide variety of video applications. The devices extract the timing information from composite video signals with scan rates from 15 to 130 kHz. • fast recovery from impulse noise • excellent temperature stability • 0.5 V to 4 Vpp input signal amplitude with 5 V supply • well-controlled clamp discharge current and slicing level • programmable horizontal scan rate (up to 130 kHz) • composite, vertical, back porch, odd/even (GS1881, GS4881), horizontal (GS4981) outputs • predictable vertical output pulse width with default trigger for non-standard video signals • 5 V to 12 V supply voltage range • pin compatible with LM1881 sync separator SELECTION CHART APPLICATION CHOOSE DEVICE: Direct LM1881 Replacement with Improved Performance GS1881 New Applications Substitution for LM1881 GS4881 New Applications Requiring Horizontal Sync Output GS4981 The GS1881 is a drop-in replacement for the industry standard LM1881 with much improved performance. The device generates composite sync, vertical sync, back porch and odd/even field signals. The GS4881 is identical to the GS1881 but features a noise immune back porch pulse which maintains a constant H rate during the vertical interval. The GS4981 is identical to the GS4881, except that it provides horizontal sync in place of the odd/even output. All three devices feature a self-adjusting windowing circuit for noise immunity, which synchronizes to H rate. This windowing c i r c u i t d e t e r m i n e s t h e o d d o r e v e n f i e l d in the GS1881 and GS4881, gates the back porch pulse in the GS4881 and GS4981, and generates the horizontal sync output in the GS4981. The devices feature an improved input stage which ensures that the input signal is sliced at a predictable point due to well-controlled input clamp discharge current and sync slicing level. A missing pulse detector enables the devices to recover quickly from impulse noise disturbances by temporarily increasing the clamp discharge current by roughly ten times. The input stage will operate with signals from 0.5 to 4 volts peak to peak with a 5 volt supply. The GS1881, GS4881 and GS4981 also feature a predictable vertical output pulse width with a default trigger for non-standard video signals. All three are available in commercial and industrial temperature ranges and are packaged in both DIP and SOIC. PIN CONNECTIONS GS4981 GS1881, GS4881 COMPOSITE SYNC OUT 8 1 V COMPOSITE SYNC OUT 1 8 V COMPOSITE VIDEO IN 2 7 HORIZONTAL VERTICAL SYNC OUT 3 6 R SET GROUND 4 5 BACK PORCH cc COMPOSITE VIDEO IN 2 7 ODD/EVEN VERTICAL SYNC OUT 3 6 RSET GROUND 4 5 BACK PORCH 8 PIN DIP 8 PIN SOIC cc 8 PIN DIP 8 PIN SOIC Patent No. 5,432,559 Document No. 520 - 23 - 03 Revision Date: October 1995 GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-2055 Japan Branch: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3247-8838 fax (03) 3247-8839 (VCC= 5 V, R SET = 680 kΩ, TA = 25° C, unless otherwise specified) GS1881 ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS Supply Voltage Supply Current Outputs at Logic 1 MIN TYP MAX UNITS 4.5 5 13.2 V VCC = 5 V - 4.6 6.5 mA V CC = 12 V - 5.0 7.0 mA VCC = 5 V 0.5 - 4 Vp-p Charge 500 650 850 µA 9 11 13 µA 65 95 115 µA 64 95 130 µs Video Input (Pin 2) (a) Signal Level (b) Clamp Current Discharge - normal - Nosync flag raised (c) Delay to raising of Nosync flag Video input held high (d) Sync Tip Clamp Voltage - 1.55 - V 70 77 84 mV See Note 1 1.14 1.24 1.34 V Composite Sync Out (Pin 1) See Note 2 40 60 80 ns Delay from Video CL = 15p Back Porch Pulse Out (Pin 5) CL = 15p 400 500 650 ns 2.0 2.5 3.2 µs Sync Slice Level Relative to sync tip clamp voltage RSET Pin Reference Voltage (Pin 6) (a) Delay from Rising Edge of Sync (b) Pulse Width Vertical Sync Out (Pin 3) (a) Pulse Width Serrations during vertical interval 197.7 197.7 197.7 µs (b) Default Starting Time No serrations during the vertical interval 48 65 82 µs Horizontal Scan Rate Modified R SET 15 - 130 kHz 4.2 4.6 - V 11.2 11.6 - V Logic Outputs I OH = 40 µA (a) V OH V CC = 5 V V CC = 12 V I OH = 1.6 mA VCC = 5 V 2.4 3.4 - V VCC = 12 V 9.4 10.4 - V - 0.3 0.6 V I OL = -1.6 mA (b) V OL Note 1: When placing the RSET resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6. Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge. ORDERING INFORMATION Part Number Package Type Temperature Range GS1881 - CDA 8 PDIP 0° to 70° C GS1881 - CKA 8 SOIC 0° to 70° C GS1881 - CTA 8 TAPE 0° to 70° C GS1881 - IDA 8 PDIP -25° to 85° C GS1881 - IKA 8 SOIC -25° to 85° C ELECTROSTATIC GS1881 - ITA 8 TAPE -25° to 85° C DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION CAUTION SENSITIVE DEVICES 520 - 23 - 03 2 (VCC= 5 V, RSET = 680 kΩ, TA = 25° C, unless otherwise specified) GS4881 ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS Supply Voltage Supply Current Outputs at Logic 1 MIN TYP MAX UNITS 4.5 5 13.2 V VCC = 5 V - 4.6 6.5 mA VCC = 12 V - 5.0 7.0 mA VCC = 5 V 0.5 - 4 Vp-p Charge 500 650 850 µA 9 11 13 µA 65 95 115 µA 64 95 130 µs Video Input (Pin 2) (a) Signal Level (b) Clamp Current Discharge - normal - Nosync flag raised (c) Delay to raising of Nosync flag Video input held high (d) Sync Tip Clamp Voltage - 1.55 - V 70 77 84 mV See Note 1 1.14 1.24 1.34 V Composite Sync Out (Pin 1) See Note 2 40 60 80 ns Delay from Video CL = 15p Back Porch Pulse Out (Pin 5) CL = 15p 400 500 650 ns 2.0 2.5 3.2 µs H H H 197.7 197.7 197.7 Sync Slice Level Relative to sync tip clamp voltage RSET Pin Reference Voltage (Pin 6) (a) Delay from Rising Edge of Sync (b) Pulse Width (c) Occurence Rate Vertical Sync Out (Pin 3) (a) Pulse Width Serrations during vertical interval µs (b) Default Starting Time No serrations during the vertical interval 48 65 82 µs Horizontal Scan Rate Modified R SET 15 - 130 kHz 4.2 4.6 - V Logic Outputs (a) VOH I OH = 40 µA V CC = 5 V 11.2 11.6 - V I OH = 1.6 mA VCC = 5 V 2.4 3.4 - V V CC = 12 V 9.4 10.4 - V - 0.3 0.6 V VCC = 12 V I OL = -1.6 mA (b) VOL Note 1: When placing the RSET resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6. Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge. ORDERING INFORMATION Part Number Package Type Temperature Range GS4881 - CDA 8 PDIP 0° to 70° C GS4881 - CKA 8 SOIC 0° to 70° C GS4881 - CTA 8 TAPE 0° to 70° C GS4881 - IDA 8 PDIP -25° to 85° C GS4881 - IKA 8 SOIC -25° to 85° C GS4881 - ITA 8 TAPE -25° to 85° C 3 520 - 23 - 03 (VCC= 5 V, RSET = 680 kΩ, TA = 25° C, unless otherwise specified) GS4981 ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS Supply Voltage Supply Current Outputs at Logic 1 MIN TYP MAX UNITS 4.5 5 13.2 V VCC = 5 V - 4.6 6.5 mA VCC = 12 V - 5.0 7.0 mA Video Input (Pin 2) (a) Signal Level VCC = 5 V 0.5 - 4 Vp-p (b) Clamp Current Charge 500 650 850 µA 9 11 13 µA 65 95 115 µA 64 95 130 µs - 1.55 - V Discharge - normal - Nosync flag raised (c) Delay to raising of Nosync flag Video input held high (d) Sync Tip Clamp Voltage Sync Slice Level Relative to sync tip clamp voltage 70 77 84 mV RSET Pin Reference Voltage (Pin 6) See Note 1 1.14 1.24 1.34 V Composite Sync Out (Pin 1) See Note 2 40 60 80 ns Delay from Video CL = 15p Back Porch Pulse Out (Pin 5) CL = 15p 400 500 650 ns 2.0 2.5 3.2 µs H H H 197.7 197.7 197.7 µs 48 65 82 µs 90 190 290 ns 5.0 7.0 9.0 µs 15 - 130 kHz 4.2 4.6 - V (a) Delay from Rising Edge of Sync (b) Pulse Width (c) Occurence Rate Vertical Sync Out (Pin 3) (a) Pulse Width Serrations during vertical interval (b) Default Starting Time No serrations during the vertical interval Horizontal Sync Out (Pin 7) CL = 15p (a) Delay from Video (b) Pulse Width Horizontal Scan Rate Modified RSET Logic Outputs (a) V OH I OH = 40 µA V CC = 5 V 11.2 11.6 - V I OH = 1.6 mA VCC = 5 V 2.4 3.4 - V Note 3 VCC = 12 V 9.4 10.4 - V - 0.3 0.6 V VCC = 12 V I OL = -1.6 mA (b) V OL Note 1: When placing the RSET resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6. Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge. Note 3: Applies only to composite sync, vertical sync, and back porch outputs. Horizontal sync has a passive 10 kΩ pull-up to V CC ORDERING INFORMATION Part Number Package Type Temperature Range GS4981 - CDA 8 PDIP 0° to 70° C GS4981 - CKA 8 SOIC 0° to 70° C GS4981 - CTA 8 TAPE 0° to 70° C GS4981 - IDA 8 PDIP -25° to 85° C GS4981 - IKA 8 SOIC -25° to 85° C GS4981 - ITA 8 TAPE -25° to 85° C 520 - 23 - 03 4 . TYPICAL PERFORMANCE CHARACTERISTICS (VS = 5V, TA = 25° C unless otherwise shown) 700 VERTICAL DEFAULT TIME (µs) 70 600 RSET (kΩ) 500 400 300 200 100 60 50 40 30 20 10 0 0 15 35 55 75 95 115 135 0 100 200 SCAN RATE (kHz) 600 700 3000 600 2500 BACK PORCH WIDTH (ns) BACK PORCH DELAY (ns) 500 Fig. 2 Vertical Sync Default Starting Time vs RSET 700 500 400 300 200 100 0 100 200 300 400 500 600 2000 1500 1000 500 0 700 0 100 200 RSET (kΩ) 300 400 500 600 700 RSET (kΩ) Fig. 4 Back Porch Width vs RSET Fig. 3 Back Porch Delay vs RSET 8000 110 100 NOSYNC DELAY TIME (µs) 7000 HORIZONTAL WIDTH (µs) 400 RSET (kΩ) Fig. 1 RSET vs Scan Rate 0 300 6000 5000 4000 3000 2000 1000 90 80 70 60 50 40 30 20 10 0 0 0 100 200 300 400 500 600 0 700 RSET (kΩ) 100 200 300 400 500 600 700 RSET (kΩ) Fig. 5 Horizontal Width vs RSET Fig. 6 Nosync Delay Time vs RSET 5 520 - 23 - 03 TEMPERATURE CHARACTERISTICS (VS = 5V, RSET = 680 kΩ unless otherwise shown) Commercial Temperature Range (0 - 70 °C) 850 8 CLAMPING CURRENT (µA) COMPOSITE SYNC DELAY VARIATION (ns) 10 6 4 2 0 -2 740 650 550 450 -4 -6 350 -25 -15 -5 5 15 25 35 45 55 65 75 85 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) TEMPERATURE (°C) Fig. 8 Clamping Current vs Temperature Fig. 7 Composite Sync Delay Variation vs Temperature 125 BACK PORCH WIDTH VARIATION (ns) BACK PORCH DELAY VARIATION (ns) 30 20 10 0 -10 -20 100 75 50 25 0 -25 -50 -75 100 -125 -25 -15 -5 5 15 25 35 45 55 65 75 85 -25 -15 -5 5 TEMPERATURE (°C) Fig. 9 Back Porch Delay Variation vs Temperature HORIZONTAL WIDTH VARIATION (ns) HORIZONTAL DELAY VARIATION (ns) 35 45 55 65 75 85 75 85 600 20 15 10 5 0 -25 -15 -5 5 15 25 35 45 55 65 75 500 400 300 200 100 0 -100 -200 -300 -25 85 TEMPERATURE (°C) -15 -5 5 15 25 35 45 55 65 TEMPERATURE (°C) Fig. 11 Horizontal Delay Variation vs Temperature 520 - 23 - 03 25 Fig. 10 Back Porch Width Variation vs Temperature 25 -5 15 TEMPERATURE (°C) Fig. 12 Horizontal Width Variation vs Temperature 6 CIRCUIT DESPCRIPTION BACK PORCH OUTPUT (pin 5) The block diagrams for the GS1881, GS4881 and GS4981, are shown in Figures 17 through 19, with timing diagrams for the devices shown in Figure 20. In an NTSC composite video signal, horizontal sync pulses are followed by the back porch interval. The device generates a negative going pulse on pin 5 during this time. It is delayed typically 500 ns from the rising edge of sync and has a typical width of 2.5 µs. Both of these times are set by the external RSET resistor. When stimulated by a composite input signal, the GS1881 and GS4881 sync separators output composite sync, vertical sync, back porch, and odd/even field information. The GS4981 substitutes the odd/even output of the GS4881 with a horizontal output. An external resistor on pin 6 is used to define internal currents allowing the devices to accommodate horizontal scan rates from 15 kHz to 130 kHz. During the pre-equalizing, vertical sync, and post-equalizing periods, composite sync doubles in frequency. The GS4881 and GS4981 maintain the back porch output at the horizontal rate due to Back Porch Enable (BPEN), generated by the internal windowing circuit, which forces back porch to be asserted at the horizontal rate. This gating circuit is also the reason for the excellent impulse noise immunity of the back porch output as shown in Figure 14. COMPOSITE VIDEO INPUT (pin 2) and COMPOSITE SYNC OUTPUT (pin 1) Composite video is AC coupled via an external coupling capacitor to pin 2. The device clamps the sync tip of the input video to 1.5 V ( Vclamp ) and then slices at 77 mV above the clamp voltage ( V slice ). The resultant signal, provided at pin 1, is a reproduction of the input signal with the active video portion removed. As Vclamp and Vslice are supply and input signal independent, for 0.5 V p-p signals (sync height of 143 mV) slicing will occur at just above the 50% point and for 2 V p-p signals (sync height of 572 mV) slicing will occur at approximately 13% of sync height. Video Input Impulse Noise Back Porch Output GS4881 GS4981 The video signal path and composite sync slicing circuitry have been optimized and compensated to achieve a low propagation delay that is stable over temperature. The typical delay is 60 ns with less than 3 ns drift over the commercial temperature range. Fig. 14 Back Porch Noise Immunity The typical input clamp discharge current is 11 µA. This current is optimal under normal operating circumstances but needs to be increased when the clamp is trying to recover from negative going impulse noise. The device improves the recovery time by raising a NOSYNC flag when there has not been a sync pulse for approximately 11/2 horizontal lines. When this flag is raised the discharge current is increased by 85 µA so that the recovery time is sped up by nearly 10 times. Figure 13 shows a comparison between the recovery times with and without the increased discharge current. The GS1881 does not gate the Back Porch which allows for total pin compatibility with the LM1881. VERTICAL SYNC OUTPUT (pin 3) VIDEO INPUT IMPULSE NOISE COMPOSITE SYNC RECOVERY TIME without INCREASED DISCHARGE CURRENT (LM1881) RECOVERY TIME T1 COMPOSITE SYNC RECOVERY TIME with INCREASED DISCHARGE CURRENT (GS1881, GS4881, GS4981) The vertical sync interval is detected by integrating the composite sync pulses. The first broad vertical sync pulse causes an internal capacitor to charge past a fixed threshold and raises an internal vertical flag. Once the vertical flag is raised, the positive edge of the next serration clocks out the vertical output. When the vertical sync interval ends, the first post equalizing pulse is unable to charge the capacitor sufficiently, causing the internal vertical flag to go high. The rising edge of the second post-equalizing pulse then clocks out the high flag to end the vertical sync pulse. The vertical output is clocked in and out and therefore is a fixed width of 197.7 µs (3H + 4.7 µs + 2.3 µs). In the case of a non-standard vertical interval that has no serrations, a second internal capacitor is charged and clocks the vertical pulse out after typically 65 µs. In this case the end of the vertical pulse will still be the rising edge of the second post-equalizing pulse. As the vertical detector is designed as a true integrator, it provides improved noise immunity. RECOVERY TIME T1 / 10 Fig. 13 Impulse Noise: Recovery Time Comparison 7 520 - 23 - 03 ODD/EVEN FIELD OUTPUT (pin 7 GS1881, GS4881) HORIZONTAL OUTPUT (pin 7 GS4981) NTSC PAL and SECAM composite video standards are interlaced video schemes and therefore have odd and even fields. For odd fields the first broad vertical sync pulse is coincident with the start of horizontal, while for even fields the first broad vertical sync pulse starts in the middle of a horizontal line. Therefore by comparing the vertical sync with an internally generated horizontal sync the odd/even field information is determined. This output is clocked out by the falling edge of vertical sync. The odd/even output is low during even fields and high during odd fields. This method of detecting odd and even fields is very noise tolerant. As mentioned above, the odd/even field output of the GS1881 and GS4881 is generated by comparing vertical sync with an internal horizontal sync signal. This horizontal sync signal is a true horizontal signal (i.e. maintained during the vertical interval) and is outputted on pin 7 for the GS4981. A delay of 190 ns from the video input and a width of 6.5 µs are typically characteristics for this signal. The windowing circuit which generates horizontal provides excellent impulse noise immunity as shown in Figure 16. This output buffer is an open collector stage with an internal 10 kΩ pull up resistor. Noise during the pre-equalizing pulses does not affect the output since the field decision is made at the beginning of the vertical interval. This noise immunity is displayed in Figure 15 in which an extra pre-equalizing pulse has been added to the video input with no negative effect on the odd/even field information. Video Input Impulse Noise Video Input Horizontal Output Impulse Noise Odd/Even Output Even Fig. 16 Horizontal Output Odd Fig. 15 Odd/Even Output 520 - 23 - 03 8 C SYNC COMPOSITE SYNC OUTPUT (Pin 1) - VIDEO INPUT (Pin 2) - + V SLICE HORIZONTAL + + V CLAMP 11µ D Q D G Q CLK Q WINDOWING CIRCUIT Q ODD / EVEN OUTPUT (Pin 7) 85µ NOSYNC VCC (Pin 8) D VOLTAGE REGULATOR VERTICAL DETECTOR VERTICAL SYNC OUTPUT (PIN 3) Q CLK Q 1.2V R_SET (Pin 6) BACK PORCH OUTPUT (Pin 5) BACK PORCH DETECTOR TIMING CURRENTS Fig. 17 GS1881 Block Diagram COMPOSITE SYNC OUTPUT (Pin 1) C SYNC - VIDEO INPUT (Pin 2) V SLICE + HORIZONTAL + V CLAMP 11µ + D Q D G Q CLK Q WINDOWING CIRCUIT Q ODD / EVEN OUTPUT (Pin 7) 85µ NOSYNC B PEN VCC (Pin 8) D VOLTAGE REGULATOR VERTICAL DETECTOR TIMING CURRENTS VERTICAL SYNC OUTPUT (PIN 3) CLK Q BACK PORCH OUTPUT (Pin 5) 1.2V R_SET (Pin 6) Q BACK PORCH DETECTOR Fig. 18 GS4881 Block Diagram 9 520 - 23 - 03 COMPOSITE SYNC OUTPUT (Pin 1) C SYNC - VIDEO INPUT (Pin 2) - + V1 + 10k + V2 HORIZONTAL OUTPUT (Pin 7) WINDOWING CIRCUIT 85µ 11µ NOSYNC B PEN VCC (Pin 8) D VOLTAGE REGULATOR VERTICAL DETECTOR VERTICAL SYNC OUTPUT (PIN 3) Q CLK Q BACK PORCH OUTPUT (Pin 5) 1.2V R_SET (Pin 6) BACK PORCH DETECTOR TIMING CURRENTS Fig. 19 GS4981 Block Diagram 525 1 2 3 4 5 6 COMPOSITE VIDEO INPUT COMPOSITE SYNC OUTPUT GS1881, GS4881, GS4981 BACK PORCH OUTPUT GS4881, GS4981 BACK PORCH OUTPUT GS1881 HORIZONTAL OUTPUT GS4981 VERTICAL SYNC OUTPUT GS1881, GS4881, GS4981 ODD/EVEN OUTPUT GS1881, GS4881 600ns 2.5µs COMPOSITE VIDEO INPUT BACK PORCH OUTPUT 500ns 2.5µs Fig. 20 GS1881, GS4881, GS4981 Video Sync Separator Timing Diagram 520 - 23 - 03 10 7 8 APPLICATION NOTES (1) Choosing the Appropriate Input Coupling Capacitor to Optimize Slicing Level and Hum Rejection 137 SLICING LEVEL (mV) 127 The video designer can adjust the slicing level by choosing the value of the input coupling capacitor. The relationship between slicing level and input coupling capacitor is described by the following equation. ∆VSLICE = where: IDIS CC ∆T = VDROOP 117 107 97 87 77 0.01 0.02 IDIS = clamp discharge current = 11 µA ∆T = TLINE - TSYNC = (63.5 µs - 4.7 µs) 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 INPUT COUPLING CAPACITOR (µF) CC = input coupling capacitor Fig. 21 Slicing Level vs Input Coupling Capacitor Figure 21 is a graphical representation of this equation and photographs 1 and 2 show the input video waveforms for 0.1 µF and 0.01 µF input capacitors respectively. The advantage in choosing a smaller input coupling capacitor, is increased hum rejection as the following analyses illustrates. CH1 CH2 CH1 8 VIDEO 2 CH2 0.1µF 6 75Ω 4 680k 0.1µ Test Circuit 1 Photograph 1 CH1 CH1 CH2 8 VIDEO 2 CH2 0.01µF 75Ω 6 4 680k 0.1µ Test Circuit 2 Photograph 2 11 520 - 23 - 03 verifying that there is enough clamping current The interfering hum component is defined by: ∆Vt = 29.4 mV + 29.4 mV = 58.8 mV vHUM(t) = V P cos(2π ƒ HUMt) where: VP = Peak voltage of AC hum ( 58.8 mV ) = 275 µA ... i = 0.022 µ 4.7 µ ƒHUM = Frequency of hum (50 Hz or 60 Hz) which is less than 650 µA. The maximum rate of change of this hum signal occurs at the zero crossing points and is: (2) FIltering dvHUM π 3π t=2, 2 dt = ± V P2 π ƒHUM In order to keep the input to output delay small and temperature stable, no chrominance filtering is done within the device. External filtering may be necessary if the input signal contains large chrominance components (less than 77 mV from sync tip) or has significant amounts of high frequency noise. This filter can be a simple low pass RC network constructed by a resistance (R S) in series with the source and a capacitor (Cƒ) to ground. A single pole low pass filter having a corner frequency of approximately 500 kHz will provide ample bandwidth for passing sync pulses with almost 18 dB attenuation at 3.58 MHz. Care should be taken in choosing the value of the series resistor in the filter since the source resistance seen by the sync separator affects its performance. Since the horizontal scan period is much faster than the period of the interference ( 63.5 µs << 1/ƒHUM) a good approximation is to assume that the maximum line to line voltage change resulting from the interfering hum is: ∆V HUM = ± V P2 π ƒHUM TLINE where: TLINE = 63.5 µs The total line to line voltage change (∆VT) can then be calculated by adding the hum component (∆VHUM ) and the droop component (VDROOP). This calculation results in two cases: ∆VT As the source resistance rises, the video input sync tip starts to be clipped due to the clamping current during the sync. This clamping current is relatively large due to the non-symmetric duty cycle of video. To a good approximation the amount of sync clamp current can be calculated as follows: ∆VT Case A Case B ( ICLAMP ∆VT = ∆VHUM + VDROOP AVG ... ICLAMP VDROOP >∆ VHUM. VDROOP is increased by decreasing the input VCLIP = ( ICLAMP ) (RS) AVG coupling capacitor value. Therefore the video designer can = (137.6 µ) (RS) increase hum rejection by decreasing the value of this capacitor. The following is a numerical example: ... VDROOP = = 137.6 µA AVG This clamp current flows in the source resistance causing a voltage drop equal to : The only way to compensate for ∆VT in case B is to make = 0.022 µF c (4.7 µs) = (11 µA) (63. 5 µs - 4.7 µs) ICLAMP To correct for ∆VT in case A, the input stage must be able to charge the input capacitor ∆VT volts in 4.7 µs. This is not a constraint as the typical clamping current of 650 µA can accomplish this for practical values of coupling capacitor. choosing C ) (TSYNC) = (IDIS) (TLINE - TSYNC) AVG ICLAMP VIDEO INPUT 11 (63.5 µ - 4.7 µ) = 29.4 mV 0.022 RS - the maximum amount of 60 Hz hum that could be rejected would be when: 75Ω 8 2 + VCLIP CC Cƒ 4 ∆VDROOP = ∆VHUM = VP 2πƒHUM TLINE ... VP = ∆VDROOP 2 π ƒHUM TLINE 2 π(60) (63.5 µ) 520 - 23 - 03 Fig. 22 Simple Chrominance Filtering 29.4mV = =1.23vPEAK HUM 12 6 680k 0.1µ Photograph 3 shows the amount of sync clipping for a 560 Ω source resistor. A graph of V CLIP versus R S is shown in Figure 23, and Figure 24 shows the corresponding capacitor value for a particular series resistor to provide a corner frequency of 500 kHz. Another way to minimize the amount of attenuation is to control the source resistance seen by the sync separator by using a PNP emitter follower (Figure 25). A PNP emitter follower works well to drive the sync separator, and does not require much DC current because the transistor provides the current when it is needed during sync. Figure 26 is a typical application circuit that minimizes sync tip clipping. In applications where signal levels are small the amount of attenuation should be minimized. It follows from Figure 23 and Figure 24 that in order to minimize attenuation a small series resistor and a larger capacitor to ground should be chosen. This however, increases the capacitive loading of the signal source. CH1 CH2 CH1 8 VIDEO 2 560Ω 0.1µF CH2 6 75Ω 4 680k 0.1µ Test Circuit 3 100 10 90 9 80 8 70 7 60 6 Cƒ (nF) VCLIP (mV) Photograph 3 50 40 5 4 30 3 20 2 10 1 0 0 0 100 200 300 400 500 600 0 700 100 200 300 500 600 700 Fig. 24 Cƒ vs Series Resistor Fig. 23 V CLIP vs Series Resistor VCC VCC 5.6k 5.6k VIDEO INPUT 8 VIDEO INPUT 2 8 2 5.6k CC CC FILTER 400 SERIES RESISTOR (Ω) SERIES RESISTOR (Ω) 4 4 6 680k 75Ω 75Ω 0.1µ 6 680k 56p 0.1µ -5V -5V Fig. 25 PNP Emitter Follower Buffer Fig. 26 Typical NTSC Application Circuit 13 520 - 23 - 03 (3) Deriving Odd/Even Using the GS4981 Odd/even field information can be derived using the vertical and horizontal outputs from the GS4981 along with an external positive edge D flip/flop. The horizontal output is used as the D input and the vertical output as the clock, as shown in Figure 27. At the start of an odd field the vertical output ends in the middle of the horizontal line and a high will be latched. At the start of an even field, the vertical output ends near the beginning of the horizontal line and since the horizontal output is low, a low will be latched. This timing sequence is shown in Figure 28. GS4981 COMPOSITE SYNC OUTPUT 1 VCC 5 - 12V 8 0.1µF D FLIP/FLOP COMPOSITE VIDEO INPUT 2 7 VERTICAL SYNC OUTPUT 3 6 680kΩ 5 4 Q Q CLK R SET 0.1µF D V HORIZONTAL ODD/EVEN OUTPUT BACK PORCH OUTPUT Fig. 27 Derivation of Odd/Even with GS4981 START OF ODD FIELD 525 1 2 3 4 5 6 7 8 COMPOSITE VIDEO INPUT HORIZONTAL OUTPUT GS4981 VERTICAL SYNC OUTPUT GS4981 ODD/EVEN OUTPUT START OF EVEN FIELD 263 264 265 266 267 268 269 270 COMPOSITE VIDEO INPUT HORIZONTAL GS4981 VERTICAL SYNC OUTPUT GS4981 ODD/EVEN OUTPUT Fig. 28 Timing Diagram DOCUMENT IDENTIFICATION PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale. ADVANCE INFORMATION NOTE This product is in development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale. PRELIMINARY The product is in a preproduction phase and specifications are subject to change without notice. REVISION NOTES DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. The only change from 520-23-02 to 520-23-03 is that the document has been upgraded to a full DATA SHEET. It is no longer Preliminary. Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright March 1991 Gennum Corporation. All rights reserved. 520 - 23 - 03 14 Printed in Canada.