ON MC74VHCT14ADR2G Hex schmitt inverter Datasheet

MC74VHCT14A
Hex Schmitt Inverter
The MC74VHCT14A is an advanced high speed CMOS Schmitt
inverter fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
Pin configuration and function are the same as the
MC74VHCT04A, but the inputs have hysteresis and, with its Schmitt
trigger function, the VHCT14A can be used as a line receiver which
will receive slow input signals.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT14A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
•
•
•
•
•
•
•
•
•
•
•
High Speed: tPD = 5.5 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: 60 FETs or 15 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 7
1
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
VHCT14AG
AWLYWW
1
14
VHCT
14A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
1
A
= Assembly Location
WL, L = Wafer Lot
Y, YY = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Outputs
A
Y
L
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Publication Order Number:
MC74VHCT14A/D
MC74VHCT14A
A1
A2
A3
1
2
3
4
5
6
9
8
11
10
Y1
Y2
Y3
VCC
A6
Y6
A5
Y5
A4
Y4
14
13
12
11
10
9
8
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3
GND
Y=A
A4
A5
A6
13
12
Y4
Y5
Y6
Pinout: 14−Lead Packages (Top View)
Figure 1. Logic Diagram
MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
DC Supply Voltage
VCC
−0.5 to +7.0
V
DC Input Voltage
VIN
−0.5 to +7.0
V
VOUT
−0.5 to VCC +0.5 V
V
VOUT
−0.5 to 7.0
V
DC Input Diode Current
IIK
−20
mA
DC Output Diode Current
IOK
$20
mA
DC Output Source/Sink Current
IO
$25
mA
DC Supply Current per Supply Pin
ICC
$50
mA
DC Ground Current per Ground Pin
IGND
$50
mA
Storage Temperature Range
TSTG
−65 to +150
°C
TL
260
°C
DC Output Voltage
Output in HIGH or LOW State (Note 1)
VCC = 0 V
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
+150
°C
Thermal Resistance
SOIC
TSSOP
qJA
125
170
°C/W
Power Dissipation in Still Air
SOIC
TSSOP
PD
500
450
mW
VESD
>2000
>200
2000
V
ILatchup
$300
mA
Junction Temperature under Bias
ESD Withstand Voltage
Latchup Performance
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above VCC and Below GND at 85°C (Note 5)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
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2
MC74VHCT14A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
VCC
4.5
5.5
V
Input Voltage
VI
0
5.5
V
Output Voltage (Note 6)
VO
0
VCC
V
VCC = 0 V
VO
0
5.5
V
Operating Free−Air Temperature
TA
−55
+125
°C
Supply Voltage
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. IO absolute maximum rating must be observed.
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
VCC
V
Symbol
TA = 25°C
Min
Typ
Positive Threshold Voltage
VT+
4.5
5.5
Negative Threshold Voltage
VT−
4.5
5.5
0.5
0.6
Hysteresis Voltage
VH
4.5
5.5
0.40
0.40
VOH
4.5
4.4
5.5
3.94
Minimum High−Level Output Voltage
IOH = −50 mA
VIN = VIH or VIL
IOH = −50 mA
IOH = −8.0 mA
Maximum Low−Level Output Voltage
VIN = VIH or VIL
IOL = 50 mA
VOL
4.5
IOL = 8.0 mA
Max
TA ≤ 85°C
TA ≤ 125°C
Min
Min
Max
1.9
2.1
1.9
2.1
0.5
0.6
1.40
1.50
4.5
0.40
0.40
Unit
1.9
2.1
V
0.5
0.6
1.40
1.50
4.4
0.40
0.40
V
1.40
1.50
4.4
3.80
0.0
Max
V
V
3.66
0.1
0.1
0.1
V
5.5
0.36
0.44
0.52
Maximum Input Leakage Current
VIN = 5.5 V or GND
IIN
0 to 5.5
±0.1
±1.0
±1.0
Maximum Quiescent Supply Current
VIN = VCC or GND
ICC
5.5
2.0
20
40
mA
Quiescent Supply Current
Input: VIN = 3.4 V
ICCT
5.5
1.35
1.50
1.65
mA
Output Leakage Current
VOUT = 5.5 V
IOFF
0.0
0.5
5.0
10
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25°C
Parameter
Maximum Propagation Delay, A to Y
Test Conditions
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
TA ≤ 125°C
Typ
Max
Min
Max
Min
Max
tPLH,
tPHL
5.5
7.0
7.6
9.6
1.0
1.0
9.0
11.0
1.0
1.0
11.5
13.5
CIN
2.0
10
Symbol
Min
TA ≤ 85°C
Unit
ns
Maximum Input Capacitance
Power Dissipation Capacitance
(Note 7)
10
10
pF
Typical @ 25°C, VCC = 5.0 V
11
CPD
pF
7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 6 (per buffer). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25°C
Symbol
Typ
Max
Unit
Quiet Output Maximum Dynamic VOL
VOLP
0.8
1.0
V
Quiet Output Minimum Dynamic VOL
VOLV
−0.8
−1.0
V
Minimum High Level Dynamic Input Voltage
VIHD
2.0
V
Maximum Low Level Dynamic Input Voltage
VILD
0.8
V
Characteristic
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3
MC74VHCT14A
TEST POINT
3.0V
A
OUTPUT
1.5V
DEVICE
UNDER
TEST
GND
tPLH
tPHL
CL*
VOH
Y
1.5V
VOL
*Includes all probe and jig capacitance
Figure 2. Switching Waveforms
Figure 3. Test Circuit
(a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times
(b) A Schmitt-Trigger Offers Maximum Noise Immunity
VCC
VH
VT+
VT-
Vin
VCC
VH
VT+
VT-
Vin
GND
GND
VOH
VOH
Vout
Vout
VOL
VOL
Figure 4. Typical Schmitt−Trigger Applications
ORDERING INFORMATION
Device
MC74VHCT14ADR2G
NLV74VHCT14ADR2G*
Package
Shipping†
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74VHCT14ADTR2G
NLV74VHCT14ADTR2G*
TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74VHCT14A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE K
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
0.25
M
C A
S
B
S
DETAIL A
h
A
e
DIM
A
A1
A3
b
D
E
e
H
h
L
M
b
X 45 _
M
A1
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
MC74VHCT14A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
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