MP2325 High Efficiency 3A, 24V, 500kHz Synchronous Step-Down Converter DESCRIPTION FEATURES The MP2325 is a high frequency synchronous rectified step-down switch mode converter with built in internal power MOSFETs. It offers a very compact solution to achieve 3A continuous output current over a wide input supply range with excellent load and line regulation. The MP2325 has synchronous mode operation for higher efficiency over output current load range. Current mode operation provides fast transient response and eases loop stabilization. Full protection features include OCP and thermal shut down. The MP2325 requires a minimum number of readily available standard external components and is available in a space saving 8-pin TSOT23 package. Wide 4.5V to 24V Operating Input Range 90mΩ/40mΩ Low Rds(on) Internal Power MOSFETs Low Quiescent Current High Efficiency Synchronous Mode Operation Fixed 500kHz Switching Frequency Frequency Sync from 200kHz to 2MHz External Clock Power Save Mode at light load Internal Soft Start Power Good Indicator OCP Protection and Hiccup Thermal Shutdown Output Adjustable from 0.8V Available in an 8-pin TSOT-23 package APPLICATIONS Notebook Systems and I/O Power Digital Set Top Boxes Flat Panel Television and Monitors All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Products, Quality Assurance page. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 2 VIN IN C1 22µF R4 20 C4 0.1µF MP2325 6 EN/ SYNC C3 0.1µF BST 5 7 SW EN / SYNC R1 40.2k VCC FB R3 100k 1 VOUT 3.3V/3A L1 4.9µH 3 PG GND C2 44µF 8 Rt 33 k R2 12.7k 4 MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 1 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER ORDERING INFORMATION Part Number* MP2325GJ Package TSOT23-8 Top Marking AKE * For Tape & Reel, add suffix –Z (e.g. MP2325GJ–Z); PACKAGE REFERENCE TSOT23-8 ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance VIN ............................................... –0.3V to +28V VSW .......–0.3V (-5V<10ns) to +28V (30V <10ns) VBST ...................................................... VSW+6V All Other Pins ................................. -0.3V to +6V (2) Continuous Power Dissipation (TA=+25°C) ... ................................................................ 1.25W Junction Temperature .............................. 150°C Lead Temperature ................................... 260°C Storage Temperature ................. -65°C to 150°C TSOT23-8…………………...…….100…..55..°C/W Recommended Operating Conditions (3) Supply Voltage VIN ............................. 4.5 to 24V Output Voltage VOUT................. 0.8V to VIN*DMAX Operating Junction Temp (TJ). . -40°C to +125°C MP2325 Rev. 1.0 12/4/2013 (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 2 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER ELECTRICAL CHARACTERISTICS VIN = 12V, TA = 25°C, unless otherwise noted. Parameter Symbol Supply Current (Shutdown) Supply Current (Quiescent) HS Switch On Resistance HSRDS-ON VEN = 0V VEN = 2V, VFB = 1V VBST-SW =5V LS Switch On Resistance Switch Leakage (5) Current Limit Oscillator Frequency Fold-back Frequency Maximum Duty Cycle LSRDS-ON SW LKG ILIMIT fSW fFB DMAX VCC=5V VEN = 0V, VSW =12V Duty Cycle=40% VFB=750mV VFB=200mV VFB=750mV (5) Minimum On Time Sync Frequency Range Feedback Voltage Feedback Current EN Rising Threshold EN Hysteresis IIN Iq Condition TON_MIN fSYNC VFB TA=25ºC IFB VFB=820mV VEN_RISING VEN_HYS EN Input Current IEN VEN=2V Min Typ 130 5.5 180 90 Max Units 240 μA μA mΩ 40 4.5 420 90 5.5 500 0.5 95 1 6.5 620 60 mΩ μA A kHz fSW % 1.2 80 791 10 1.4 150 2 799 50 1.6 220 ns MHz mV nA V mV 1.5 2 2.5 μA 0 50 nA 10 14 μs 0.2 783 VEN=0 EN Turn Off Delay ENTd-off Power Good Rising Threshold PGVTH-Hi 0.9 VFB Power Good Falling Threshold PGVTH-LO 0.85 VFB PGTd 40 μs Power Good Delay Power Good Capability Sink Current Power Good Leakage Current VPG 6 Sink 1mA IPG-LEAK VIN Under Voltage Lockout INUVVth Threshold-Rising VIN Under Voltage Lockout INUVHYS Threshold-Hysteresis VCC Regulator VCC VCC Load Regulation ICC=5mA Soft-Start Period TSS (5) Thermal Shutdown Thermal Hysteresis (5) 0.4 V 1 μA 3.7 3.9 4.1 V 550 650 750 mV 4.65 0 0.8 4.9 1 1.5 150 5.15 3 2.2 V % ms ºC 20 ºC Notes: 5) Guaranteed by design MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 3 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER TYPICAL CHARACTERISTICS VIN = 12V, VOUT = 3.3V, L = 4.9μH, TA = 25°C, unless otherwise noted. MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 4 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 3.3V, L = 4.9μH, TA = 25°C, unless otherwise noted. MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 5 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 4.9µH, TA = 25°C, unless otherwise noted. MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 6 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER PIN FUNCTIONS Package Pin # Name 1 PG Description Power Good Output. The output of this pin is an open drain. It’s pulled up to Vcc by external resistor when the output voltage exceeds 90% of the normal voltage. There is a 40μs delay between FB≥90% to the PG pin goes high. Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The MP2325 operates from a +4.5V to +24V input rail. Requires a low-ESR, and low inductance capacitor (C1) to decouple the input rail. Place the input capacitor very close to this pin and connect it with wide PCB traces and multiple vias. Switch Output. Connect to the inductor and bootstrap capacitor. This pin is driven up to VIN by the high-side switch during the PWM duty cycle ON time. The inductor current drives the SW pin negative during the OFF time. The ON resistance of the low-side switch and the internal body diode fixes the negative voltage. Connect using wide PCB traces and multiple vias. System Ground. This pin is the reference ground of the regulated output voltage. For this reason care must be taken in PCB layout. Suggested to be connected to GND with copper and vias. 2 IN 3 SW 4 GND 5 BST Bootstrap. A capacitor and a 20Ω resistor connected between SW and BST pins are required to form a floating supply across the high-side switch driver. 6 EN/SYNC EN=1 to enable the MP2325. External clock can be applied to EN pin for changing switching frequency. For automatic start-up, connect EN pin to VIN with a 100kΩ resistor. 7 VCC Bias Supply. Decouple with 0.1μF-0.22μF cap. And the capacitance should be no more than 0.22μF FB Feedback. An external resistor divider from the output to GND, tapped to the FB pin, sets the output voltage. To prevent current limit run away during a short circuit fault condition the frequency fold-back comparator lowers the oscillator frequency when the FB voltage is below 400mV. 8 MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 7 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER FUNCTION BLOCK DIAGRAM Figure 1: Functional Block Diagram MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 8 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER OPERATION The MP2325 is a high frequency synchronous rectified step-down switch mode converter with built in internal power MOSFETs. It offers a very compact solution to achieve 3A continuous output current over a wide input supply range with excellent load and line regulation. The MP2325 operates in a fixed frequency, peak current control mode to regulate the output voltage. A PWM cycle is initiated by the internal clock. The integrated high-side power MOSFET is turned on and remains on until its current reaches the value set by the COMP voltage. When the power switch is off, it remains off until the next clock cycle starts. If, in 95% of one PWM period, the current in the power MOSFET does not reach the COMP set current value, the power MOSFET will be forced to turn off. Internal Regulator Most of the internal circuitries are powered from the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5.0V, the output of the regulator is in full regulation. When VIN is lower than 5.0V, the output decreases, a 0.1uF ceramic capacitor for decoupling purpose is required. Error Amplifier The error amplifier compares the FB pin voltage with the internal 0.8V reference (REF) and outputs a COMP voltage, which is used to control the power MOSFET current. The optimized internal compensation network minimizes the external component counts and simplifies the control loop design. Power Save Mode for Light Load Condition The MP2325 has AAM (Advanced Asynchronous Modulation) power-save mode for light load. Under the heavy load condition, the VCOMP is higher than VAAM. When the clock goes high, the high-side power MOSFET turns on and remains on until VILsense reaches the value set by the COMP voltage. The internal clock resets every time when VCOMP is higher than VAAM. MP2325 Rev. 1.0 12/4/2013 Under the light load condition, the value of VCOMP is low. When VCOMP is less than VAAM and VFB is less than VREF, VCOMP ramps up until it exceeds VAAM. During this time, the internal clock is blocked, thus the MP2325 skips some pulses for PFM (Pulse Frequency Modulation) mode and achieves the light load power save. 4 33k Figure 2: Simplified AAM Control Logic For VIN=12V, VOUT=3.3V, L=4.9μH, the inductor peak current set internally is about 500mA at light load. The AAM voltage internally is varied with duty cycle for keeping the inductor peak current constant. Figure 3: AAM Selection for Common Output Voltages (VIN=4.5V-24V) Enable/SYNC control EN is a digital control pin that turns the regulator on and off. Drive EN high to turn on the regulator, drive it low to turn it off. There is an internal 1MEG resistor from EN to GND thus EN can be floated to shut down the chip. Also EN pin voltage was clamped to around 6.5V by an internal zener-diode. Please use large enough pull up resistor connecting between VIN and EN to limit the EN input current which should be less than 100uA. Generally, around www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 9 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER 100k resistor should be large enough for all the applications. The chip can be synchronized to external clock range from 200kHz up to 2MHz through this pin 2ms right after output voltage is set, with the internal clock rising edge synchronized to the external clock rising edge. EN synchronize logic high voltage should higher than 2V. EN synchronize logic low voltage should lower than 400mV. EN logic high pulse width must less than 1.6µs. Otherwise the internal clock may come and turn on high side MOSFET again. EN logic low pulse width must less than 6µs, otherwise MP2325 may EN shutdown. Power Good Indicator The MP2325 has an open drain pin for power good indicator. When FB pin is higher than 90% of regulation voltage, PG pin is pulled up to VCC by the external resistor. If FB pin voltage drop down to 85% of the regulation voltage, PG pin is pulled down to ground by an internal MOS FET. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the chip from operating at insufficient supply voltage. The MP2325 UVLO comparator monitors the output voltage of the internal regulator, VCC. The UVLO rising threshold is about 3.9V while its falling threshold is consistent 3.25V. Internal Soft-Start The soft start is implemented to prevent the converter output voltage from overshooting during start up. When the chip starts, the internal circuitry generates a soft-start voltage (SS) ramping up from 0V. The soft-start period lasts until the voltage on the soft-start capacitor exceeds the reference voltage of 0.8V. At this point the reference voltage takes over. The softstart time is internally set to be around 1.5ms. Over-Current-Protection and Hiccup The MP2325 has cycle-by-cycle over current limit when the inductor current peak value exceeds the set current limit threshold. Meanwhile, output voltage starts to drop until FB is below the Under-Voltage (UV) threshold, typically 50% below the reference. Once a UV is triggered, the MP2325 enters hiccup mode to MP2325 Rev. 1.0 12/4/2013 periodically restart the part. This protection mode is especially useful when the output is dead-short to ground. The average short circuit current is greatly reduced to alleviate the thermal issue and to protect the regulator. The MP2325 exits the hiccup mode once the over current condition is removed. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. When the silicon die temperature is higher than 150°C, it shuts down the whole chip. When the temperature is lower than its lower threshold, typically 130°C, the chip is enabled again. Floating Driver and Bootstrap Charging The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally by VIN through D1, R5, C5, L1 and C2 (Figure 4). If (VIN-VSW) is more than 5V, U1 will regulate M1 to maintain a 5V BST voltage across C5. R5 5 Figure 4: Internal Bootstrap Charging Circuit Startup and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts. The reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. The regulator provides stable supply for the remaining circuitries. Three events can shut down the chip: EN low, VIN low and thermal shutdown. In the shutdown procedure, the signaling path is first blocked to www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 10 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER avoid any fault triggering. The COMP voltage and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 11 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER APPLICATION INFORMATION COMPONENT SELECTION Setting the Output Voltage The external resistor divider is used to set the output voltage (see Typical Application on page 1). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation capacitor (see Typical Application on page 1). R2 is then given by: R2 R1 VOUT 1 The T-type network is highly recommended, as Figure 5 shows. Figure 5: T-type Network Table 1 lists the recommended T-type resistors value for common output voltages. Table 1—Resistor Selection for Common Output Voltages VOUT(V) R1(kΩ) R2(kΩ) Rt (kΩ) L (µH) Cf (µF) 1 20.5 76.8 100 1.8 15 1.2 20.5 39.2 100 1.8 15 1.8 40.2 31.6 56 3.3 15 2.5 40.2 18.7 56 3.3 15 3.3 40.2 12.7 33 4.9 15 5 40.2 7.5 33 4.9 15 Selecting the Inductor A 1µH to 22µH inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most applications. For highest efficiency, the inductor DC resistance should be less than 15mΩ. For most designs, the inductance value can be derived from the following equation. VOUT (VIN VOUT ) VIN IL fOSC Where ΔIL is the inductor ripple current. MP2325 Rev. 1.0 12/4/2013 IL(MAX ) ILOAD IL 2 Under light load conditions below 100mA, larger inductance is recommended for improved efficiency. Selecting the Input Capacitor 0.8V L1 Choose inductor current to be approximately 30% of the maximum load current. The maximum inductor peak current is: The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 22µF capacitor is sufficient. Since the input capacitor (C1) absorbs the input switching current it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: IC1 ILOAD VOUT VOUT 1 VIN VIN The worse case condition occurs at VIN = 2VOUT, where: IC1 ILOAD 2 For simplification, choose the input capacitor whose RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1μF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: VIN V ILOAD V OUT 1 OUT fS C1 VIN VIN www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 12 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER Selecting the Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: VOUT VOUT VOUT 1 fS L1 VIN 1 RESR 8 f C2 S Where L1 is the inductor value and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ΔVOUT V VOUT 1 OUT VIN 8 fS L1 C2 2 In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ΔVOUT VOUT V 1 OUT fS L1 VIN RESR The characteristics of the output capacitor also affect the stability of the regulation system. The MP2325 can be optimized for a wide range of capacitance and ESR values. RBST MP2325 Figure 6: Add Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the BST cap is 0.1μF─1μF. PC Board Layout (6) PCB layout is very important to achieve stable operation. Please follow these guidelines and take Figure 7 as reference. 1) Keep the connection of input ground and GND pin as short and wide as possible. 2) Keep the connection of input capacitor and IN pin as short and wide as possible. 3) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 4) Route SW away from sensitive analog areas such as FB. Notes: 6) The recommended layout is based on the Figure 8 Typical Application circuit on the next page. External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator, the applicable conditions of external BST diode are: VOUT is 5V or 3.3V; Duty cycle is high: D= VOUT >65% VIN In these cases, an external BST diode is recommended from the VCC pin to BST pin, as shown in Figure 6. MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 13 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER Design Example GND C3 R1 Below is a design example following the application guidelines for the specifications: C4 SW R4 7 6 5 3 4 R3 8 2 R5 1 R6 R2 C5 VIN VOUT IO L1 C1 C1A Vin C2 Table 2: Design Example Vout 19V 5V 3A The detailed application schematics are shown in Figures 8 through 13. The typical performance and circuit waveforms have been shown in the Typical Performance Characteristics section. For more device applications, please refer to the related Evaluation Board Datasheets. C2A GND VOUT GND VCC EN/SYNC BST SW GND Figure 7: Sample Board Layout MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 14 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER TYPICAL APPLICATION CIRCUITS U1 C1A 22uF R5 100k C1 0.1uF C5 0.1uF IN BST R3 20 C4 0.1uF VCC MP2325 L1 4.9uH SW 5V/3A C2 22uF PG C2A 22uF C3 15pF R4 100k EN GND R6 33k FB R2 7.5k R1 40.2k Figure 8: Vo=5V, Io=3A U1 C1A 22uF R5 100k C1 0.1uF C5 0.1uF IN BST R3 20 C4 0.1uF VCC MP2325 L1 4.9uH SW 3.3V/3A C2 22uF PG C2A 22uF C3 15pF R4 100k EN GND R6 33k FB R2 12.7k R1 40.2k Figure 9: Vo=3.3V, Io=3A U1 C1A 22uF R5 100k C1 0.1uF C5 0.1uF IN BST R3 20 C4 0.1uF VCC MP2325 L1 3.3uH SW C2 22uF PG C2A 22uF C3 15pF R4 100k EN 2.5V/3A GND FB R6 56k R2 18.7k R1 40.2k Figure 10: Vo=2.5V, Io=3A MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 15 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER U1 C1A 22uF R5 100k C1 0.1uF C5 0.1uF IN BST R3 20 C4 0.1uF VCC MP2325 L1 3.3uH SW 1.8V/3A C2 22uF PG C2A 22uF C3 15pF R4 100k EN GND R6 56k FB R2 31.6k R1 40.2k Figure 11: Vo=1.8V, Io=3A U1 C1A 22uF R5 100k C1 0.1uF C5 0.1uF IN BST R3 20 C4 0.1uF VCC MP2325 L1 1.8uH SW 1.2V/3A C2 22uF PG C2A 22uF C3 15pF R4 100k EN GND R6 100k FB R2 39.2k R1 20.5k Figure 12: Vo=1.2V, Io=3A U1 C1A 22uF R5 100k C1 0.1uF C5 0.1uF IN BST R3 20 C4 0.1uF VCC MP2325 L1 1.8uH SW C2 22uF PG C2A 22uF C3 15pF R4 100k EN 1V/3A GND FB R6 100k R2 76.8k R1 20.5k Figure 13: Vo=1V, Io=3A MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 16 MP2325 – 24V, 3A SYNC STEP DOWN CONVERTER PACKAGE OUTLINE DRAWING FOR 8L TSOT23 PACKAGE INFORMATION MF-PO-D-0105 revision 3.0 TSOT23-8 See note 7 EXAMPLE TOP MARK PIN 1 ID IAAAA RECOMMENDED LAND PATTERN TOP VIEW SEATING PLANE SEE DETAIL ''A'' FRONT VIEW SIDE VIEW NOTE: DETAIL ''A'' 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) JEDEC REFERENCE IS MO-193, VARIATION BA. 6) DRAWING IS NOT TO SCALE. 7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK) NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2325 Rev. 1.0 12/4/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 17