Cypress CY7B9950AXCT 2.5/3.3v, 200-mhz high-speed multi-phase pll clock buffer Datasheet

RoboClock®
CY7B9950
2.5/3.3V, 200-MHz High-Speed Multi-Phase
PLL Clock Buffer
Features
Description
The CY7B9950 RoboClock® is a low-voltage, low-power,
eight-output, 200-MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance computer and communication systems.
• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• 50 ps typical matched-pair Output-output skew
• 50 ps typical Cycle-cycle jitter
• 49.5/50.5% typical output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
• Eight LVTTL outputs driving 50Ω terminated lines
• LVCMOS/LVTTL over-voltage-tolerant reference input
• Phase adjustments in 625-/1250-ps steps up to +7.5 ns
• 2x, 4x multiply and (1/2)x, (1/4)x divide ratios
• Spread-Spectrum-compatible
• Industrial temp. range: –40°C to +85°C
• 32-pin TQFP package
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature allows the user to
skew the outputs to lead or lag the reference clock. Any one
of the outputs can be connected to feedback input to achieve
different reference frequency multiplication and divide ratios
and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin
controls the synchronization of the output signals to either the
rising or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA(3.3V).
Pin Configuration
Block Diagram
3F1
REF
TEST
2F1
2F0
27
26
25
VDD
VSS
FS
30
VDDQ1
1Q0
2Q0
4Q1
4Q0
VSS
6
7
19
18
1Q1
8
17
14
15
16
VDD
2Q1
2Q0
3Q1
13
3Q0
CY7B9950
FB
2Q1
Phase
Select
and /K
3F0
21
20
12
3
4
5
VDDQ3
3
3F1:0
PE/HD
VDDQ4
11
3
1Q1
3Q0
2F1:0
Phase
Select
1F0
10
3
Phase
Select
23
22
9
3
1F1
4F0
4F1
1
2
3
24
1Q0
3Q1
3
1F1:0
31
PLL
FB
32
3
28
3
3
VSS
REF
VDDQ1
29
TEST PE/HD FS
sOE#
VSS
VSS
VDDQ3
3
4F1:0
3
4Q0
Phase
Select
and /M
4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation
Document #: 38-07338 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 15, 2006
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CY7B9950
Pin Description
Name
I/O[1]
29
REF
I
13
FB
I
LVTTL
27
TEST
I
Three-level
When MID or HIGH, Disables Phase-locked Loop (PLL) (except for conditions of note 3). REF goes to outputs of Bank 1 and Bank 2. REF goes to
outputs of Bank 3 and Bank 4 through output dividers K and M. Set LOW for
normal operation.
22
sOE#
I, PD
Two-level
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0
and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level
and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual
banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
4
PE/HD
I, PU
Three-level
Selects Positive or Negative Edge Control and High or Low output drive
strength. When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock, respectively. When at MID level,
the output drive strength is increased and the outputs synchronize with the
positive edge of the reference clock (see Table 6).
24, 23, 26,
25, 1, 32, 3,
2
nF[1:0]
I
Three-level
Select frequency and phase of the outputs (see Tables 1, 2, 3, 4, and 5).
FS
I
Three-level
Selects VCO operating frequency range (see Table 4).
O
LVTTL
Four banks of two outputs (see Tables 1, 2, and 3).
Pin
31
19, 20, 15,
nQ[1:0]
16, 10, 11, 6,
7
Type
Description
LVTTL/LVCMOS Reference Clock Input.
Feedback Input.
21
VDDQ1[2] PWR
Power
Power supply for Bank 1 and Bank 2 output buffers (see Table 7 for supply
level constraints).
12
VDDQ3[2] PWR
Power
Power supply for Bank 3 output buffers (see Table 7 for supply level
constraints).
5
VDDQ4[2] PWR
Power
Power supply for Bank 4 output buffers (see Table 7 for supply level
constraints).
14,30
8,9,17,18,28
VDD[2]
PWR
Power
Power supply for internal circuitry (see Table 7 for supply level constraints).
VSS
PWR
Power
Ground.
Device Configuration
The outputs of the CY7B9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 1 and Table 2, respectively.
Table 1. Output Divider Settings — Bank 3
3F[1:0]
K — Bank3 Output Divider
LL
2
HH
4
Other[4]
1
Table 2. Output Divider Settings — Bank 4
4F[1:0]
M — Bank4 Output Divider
LL
2
Other[4]
1
The three-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B9950 PLL operating frequency range that
corresponds to each FS level is given in Table 3.
Table 3. Frequency Range Select
FS
PLL Frequency Range
L
24 to 50 MHz
M
48 to 100 MHz
H
96 to 200 MHz
Selectable output skew is in discrete increments of time unit
(tU).The value of tU is determined by the FS setting and the
maximum nominal frequency. The equation to be used to
determine the tU value is as follows: tU = 1 / (fNOM x MF)
where MF is a multiplication factor, which is determined by the
FS setting as indicated in Table 4.
Notes:
1. “PD” indicates an internal pull-down and “PU” indicates an internal pull-up. “3” indicates a three-level input buffer
2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4. These states are used to program the phase of the respective banks (see Table 5).
Document #: 38-07338 Rev. *C
Page 2 of 10
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Table 4. MF Calculation
FS
MF
fNOM at which tU is 1.0 ns(MHz)
L
32
31.25
M
16
62.5
H
8
125
Table 5. Output Skew Settings
nF[1:0]
Skew (1Q[0:1],2Q[0:1])
Skew (3Q[0:1])
Skew (4Q[0:1])
LL[5]
–4tU
Divide By 2
Divide By 2
LM
–3tU
–6tU
v6tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
v2tU
MM
Zero Skew
Zero Skew
Zero Skew
MH
+1tU
+2tU
+2tU
HL
+2tU
+4tU
+4tU
HM
+3tU
+6tU
+6tU
HH
+4tU
Divide By 4
Inverted[6]
In addition to determining whether the outputs synchronize to
the rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as
indicated in Table 6.
The CY7B9950 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain
both 3.3V and 2.5V output signals from one device. The core
power supply (VDD) must be set a level that is equal or higher
than on any one of the output power supplies.
Table 6. PE/HD Settings
PE/HD
Synchronization
Output Drive Strength[7]
Table 7. Power Supply Constraints
VDD
VDDQ1[8]
VDDQ3[8]
VDDQ4[8]
3.3V
3.3V or 2.5V
3.3V or 2.5V
3.3V or 2.5V
2.5V
2.5V
2.5V
2.5V
Governing Agencies
The following agencies provide specifications that apply to the
CY7B9950. The agency name and relevant specification is
listed below.
Table 8.
L
Negative
Low Drive
Agency Name
M
Positive
High Drive
JEDEC
H
Positive
Low Drive
Specification
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
IEEE
1596.3 (Jitter Specs)
UL-194_V0
94 (Moisture Grading)
MIL
883E Method 1012.1 (Therma Theta JC)
Notes:
5. LL disables outputs if TEST = MID and sOE# = HIGH.
6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW.
7. Please refer to “DC Parameters” section for IOH/IOL specifications.
8. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V
and VDDQ4 = 2.5V.
Document #: 38-07338 Rev. *C
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Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Operating Voltage
Functional @ 2.5V ± 5%
2.375
2.625
V
VDD
Operating Voltage
Functional @ 3.3V ± 10%
2.97
3.63
V
VIN(MIN)
Input Voltage
Relative to VSS
VSS – 0.3
–
V
VIN(MAX)
Input Voltage
Relative to VDD
–
VDD + 0.3
V
TS
Temperature, Storage
Non-functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
–40
+85
°C
TJ
Temperature, Junction
Functional
–
155
°C
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
–
42
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
–
105
°C/W
ESDHBM
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
–
V
UL-94
Flammability Rating
MSL
Moisture Sensitivity Level
FIT
Failure in Time
@1/8 in.
V–0
1
Manufacturing Testing
10
ppm
DC Electrical Specifications @ 2.5V
Parameter
Description
Conditions
Min.
Max.
Unit
2.375
2.625
V
–
0.7
V
VDD
2.5 Operating Voltage
2.5V ± 5%
VIL
Input LOW Voltage
REF, FB and sOE# Inputs
VIH
Input HIGH Voltage
VIHH[9]
Input HIGH Voltage
VIMM[9]
Input MID Voltage
VILL[9]
Input LOW Voltage
0.4
V
IIL
Input Leakage Current
VIN = VDD/GND,
VDD = max. (REF and FB inputs)
–5
5
µA
I3
3-Level Input DC Current
HIGH, VIN = VDD
–
200
µA
1.7
VDD – 0.4
3-Level Inputs
(TEST, FS, nF[1:0], PE/HD) (These pins V /2 – 0.2
are normally wired to VDD,GND or uncon- DD
nected.)
–
MID, VIN = VDD/2
LOW, VIN = VSS
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
–
V
–
V
VDD/2 +
0.2
V
–50
50
µA
–200
–
µA
–25
–
µA
IPU
Input Pull-up Current
VIN = VSS, VDD = max.
IPD
Input Pull-down Current
VIN = VDD, VDD = max., (sOE#)
–
100
µA
VOL
Output LOW Voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
–
0.4
V
IOL = 20 mA (PE/HD = MID), (nQ[0:1])
–
0.4
V
VOH
Output HIGH Voltage
IOH = –12 mA (PE/HD = L/H), (nQ[0:1])
2.0
–
V
IOH = –20 mA (PE/HD = MID), (nQ[0:1])
2.0
–
V
–
2
mA
IDDQ
Quiescent Supply Current
VDD = max., TEST = MID, REF = LOW,
sOE# = LOW, outputs not loaded
IDD
Dynamic Supply Current
@ 100 MHz
CIN
Input Pin Capacitance
150
mA
4
pF
Note:
9. These inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
Document #: 38-07338 Rev. *C
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DC Specifications @ 3.3V
Parameter
Description
Condition
VDD
3.3 Operating Voltage
3.3V ± 10%
VIL
Input LOW Voltage
REF, FB and sOE# Inputs
VIH
Input HIGH Voltage
VIHH[9]
Input HIGH Voltage
VIMM[9]
Input MID Voltage
VILL[9]
Input LOW Voltage
IIL
Input Leakage Current
VIN = VDD/GND,VDD = max. (REF and FB
inputs)
I3
3-Level Input DC Current
HIGH, VIN = VDD
3-Level Inputs
(TEST, FS, nF[1:0], PE/HD) (These pins
are normally wired to VDD,GND or
unconected.)
MID, VIN = VDD/2
LOW, VIN = VSS
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
IPU
Input Pull-up Current
VIN = VSS, VDD = max.
Min.
Max.
Unit
2.97
3.63
V
–
0.8
V
2.0
–
V
VDD – 0.6
–
V
VDD/2 – 0.3
VDD/2 +
0.3
V
–
0.6
V
–5
5
µA
–
200
µA
–50
50
µA
–200
–
µA
–100
–
µA
IPD
Input Pull-down Current
VIN = VDD, VDD = max., (sOE#)
–
100
µA
VOL
Output LOW Voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
–
0.4
V
IOL = 24 mA (PE/HD = MID), (nQ[0:1])
–
0.4
V
VOH
Output HIGH Voltage
IOH = –12 mA (PE/HD = L/H), (nQ[0:1])
2.4
–
V
IOH = –24 mA (PE/HD = MID), (nQ[0:1])
2.4
–
V
IDDQ
Quiescent Supply Current
VDD = max., TEST = MID, REF = LOW,
sOE# = LOW, outputs not loaded
–
2
mA
IDD
Dynamic Supply Current
@ 100 MHz
CIN
Input Pin Capacitance
Document #: 38-07338 Rev. *C
230
mA
4
pF
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AC Test Loads and Waveforms
Q
Output
150Ω
20 pF
Output
20 pF
150Ω
For Lock Output
For All Other Outputs
Figure 1. AC Test Loads
tORISE
tPWH
2.0V
tORISE
tOFALL
tOFALL
tPWH
1.7V
VTH =1.25V
VTH =1.5V
tPWL
0.7V
0.8V
tPWL
2.5V LVTTL OUTPUT WAVEFORM
3.3V LVTTL OUTPUT WAVEFORM
Figure 2. Output Waveforms
≤ 1 ns
≤1 ns
≤1 ns
≤ 1 ns
2.5V
3.0V
1.7V
2.0V
VTH =1.5V
0.8V
0V
3.3V LVTTL INPUT TEST WAVEFORM
VTH =1.25V
0.7V
0V
2.5V LVTTL INPUT TEST WAVEFORM
Figure 3. Test Waveforms
Document #: 38-07338 Rev. *C
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AC Input Specifications
Parameter
Description
Condition
Min.
Max.
Unit
TR,TF
Input Rise/Fall Time
0.8V – 2.0V
–
10
ns/V
TPWC
Input Clock Pulse
HIGH or LOW
2
–
ns
TDCIN
Input Duty Cycle
%
FREF
Reference Input
Frequency
10
90
FS = LOW
6
50
FS = MID
12
100
FS = HIGH
24
200
MHz
Switching Characteristics
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
6
–
200
MHz
FOR
Output Frequency
Range
VCOLR
VCO Lock Range
200
–
400
MHz
VCOLBW
VCO Loop Bandwidth
0.25
–
3.5
MHz
tSKEWPR
Matched-Pair Skew[10]
Skew between the earliest and the latest output transitions within the same bank.
–
50
100
ps
tSKEW0
Output-Output Skew[10]
Skew between the earliest and the latest output transitions among all outputs at 0tU.
–
100
200
ps
tSKEW1
Skew between the earliest and the latest output transitions among all outputs for which the same phase delay
has been selected.
–
100
200
ps
tSKEW2
Skew between the nominal output rising edge to the
inverted output falling edge
–
–
500
ps
Skew between non-inverted outputs running at different
frequencies
–
–
500
ps
tSKEW4
Skew between nominal to inverted outputs running at
different frequencies
–
–
500
ps
tSKEW5
Skew between nominal outputs at different power
supply levels
–
–
650
ps
Skew between the outputs of any two devices under
identical settings and conditions (VDDQ,VDD,temp, air
flow, frequency, etc.)
–
–
750
ps
–250
–
+250
ps
Fout < 100 MHz, measured at VDD/2
48
49.5/
50.5
52
%
Fout > 100 MHz, measured at VDD/2
45
48/
52
55
tSKEW3
Output-Output Skew[10]
tPART
Part-Part Skew
tPD0
Ref-FB Propagation
Delay[11]
tODCV
Output Duty Cycle
tPWH
Output High Time
Deviation from 50%
Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD =
2.5V.
–
–
1.5
ns
tPWL
Output Low Time
Deviation from 50%
Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD =
2.5V.
–
–
2.0
ns
tR/tF
Output Rise/Fall Time
Measured at 0.8V – 2.0V for VDD = 3.3V and 0.7V–1.7V
for VDD = 2.5V
0.15
–
1.5
ns
tLOCK
PLL lock time[12,13]
tCCJ
Cycle-Cycle Jitter
–
–
0.5
ms
Divide by 1 output frequency, FS = L, FB = divide by
1,2,4
–
50
100
ps
Divide by 1 output frequency, FS = M/H, FB = divide by
1,2,4
–
70
150
ps
Notes:
10. Test load = 20 pF, terminated to VCC/2. All outputs are equally loaded.
11. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5 ns between 0.8V – 2.0V.
12. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
13. Lock detector circuit may be unreliable for input frequencies lower than 4 MHz, or for input signals which contain significant jitter.
Document #: 38-07338 Rev. *C
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AC Timing Definitions
tPW H
REF
tPD
t0DCV
t0DCV
FB
tCCJ1-12
Q
tSKEWPR
tSKEW0,1
tSKEW PR
tSKEW 0,1
OTHER Q
tSKEW 1
tSKEW 1
INVERTED Q
tSKEW 3
tSKEW 3
tSKEW 3
REF DIVIDED BY 2
tSKEW 1,3,4
tSKEW 1,3,4
REF DIVIDED BY 4
Figure 4. Timing Definitions
Ordering Information
Part Number
Package Type
Product Flow
CY7B9950AC
32 TQFP
Commercial, 0° to 70°C
CY7B9950ACT
32 TQFP – Tape and Reel
Commercial, 0° to 70°C
CY7B9950AI
32 TQFP
Industrial, –40° to 85°C
CY7B9950AIT
32 TQFP – Tape and Reel
Industrial, –40° to 85°C
CY7B9950AXC
32 TQFP
Commercial, 0° to 70°C
Lead-free
CY7B9950AXCT
32 TQFP – Tape and Reel
Commercial, 0° to 70°C
CY7B9950AXI
32 TQFP
Industrial, –40° to 85°C
CY7B9950AXIT
32 TQFP – Tape and Reel
Industrial, –40° to 85°C
Document #: 38-07338 Rev. *C
Page 8 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7B9950
Package Drawing and Dimension
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-07338 Rev. *C
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Document History Page
Document Title: RoboClock® CY7B9950 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
Document Number: 38-07338
Rev.
ECN No.
Issue Date
Orig. of
Change
**
121663
11/25/02
RGL
New Data Sheet
*A
122548
12/12/02
RGL
Removed the PD#/DIV and DS[1:0] pins in VIHH,VIMM and VILL for both
2.5V and 3.3V DC Electrical Specs tables
*B
124646
03/05/03
RGL
Corrected the description of Pin 27(TEST) in the Pin Description table
Corrected the description of Pin 12 (VDDQ) in the Pin Description table
Corrected the Min and Max values of VDD from 2.25/2.75 to 2.375/2.625
Volts in the Absolute Maximum Conditions table
*C
433662
See ECN
RGL
Added Lead-free devices
Added Jitter typical values
Document #: 38-07338 Rev. *C
Description of Change
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