ON MC74VHC00 Quad 2−input nand gate Datasheet

MC74VHC00
Quad 2−Input NAND Gate
The MC74VHC00 is an advanced high speed CMOS 2−input
NAND gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
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MARKING
DIAGRAMS
14
Features
•
•
•
•
•
•
•
•
•
•
•
•
High Speed: tPD = 3.7 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 32 FETs or 8 Equivalent Gates
Pb−Free Packages are Available
VCC
B4
A4
Y4
B3
A3
Y3
14
13
12
11
10
9
8
SO−14
D SUFFIX
CASE 751A
VHC00G
AWLYWW
1
14
VHC
00
ALYW G
G
TSSOP−14
DT SUFFIX
CASE 948G
1
14
74VHC00
ALYWG
EIAJ SO−14
M SUFFIX
CASE 965
1
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2
GND
A
L, WL
Y
W, WW
G, G
Figure 1. Pinout: 14−Lead Packages
(Top View)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
FUNCTION TABLE
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 5
1
Publication Order Number:
MC74VHC00/D
MC74VHC00
A1
B1
A2
B2
A3
B3
A4
B4
1
3
2
4
6
5
Y1
Y2
Y = AB
9
8
10
12
11
13
Y3
Y4
Figure 2. Logic Diagram
MAXIMUM RATINGS
Value
Unit
VCC
Symbol
Positive DC Supply Voltage
Parameter
−0.5 to +7.0
V
VIN
Digital Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
$20
mA
IOUT
DC Output Current, per Pin
$25
mA
ICC
DC Supply Current, VCC and GND Pins
$75
mA
PD
Power Dissipation in Still Air
200
180
mW
TSTG
Storage Temperature Range
−65 to +150
°C
VESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
>2000
>200
N/A
V
ILATCH−UP
Latch−Up Performance
Above VCC and Below GND at 125°C (Note 4)
$300
mA
qJA
Thermal Resistance, Junction to Ambient
143
164
°C/W
SOIC Package
TSSOP
SOIC Package
TSSOP
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
VIN
DC Input Voltage
0
5.5
V
VOUT
DC Output Voltage
0
VCC
V
TA
Operating Temperature Range, All Package Types
−55
125
°C
tr, tf
Input Rise or Fall Time
0
0
100
20
ns/V
VCC = 3.3 V + 0.3 V
VCC = 5.0 V + 0.5 V
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2
MC74VHC00
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DC ELECTRICAL CHARACTERISTICS
TA = 25°C
VCC
V
Min
High−Level Input
Voltage
2.0
3.0 to
5.5
1.50
VCC x
0.7
VIL
Low−Level Input
Voltage
2.0
3.0 to
5.5
VOH
High−Level
Output Voltage
Symbol
Parameter
VIH
Test Conditions
Vin = VIH or VIL
IOH = − 50 mA
Vin = VIH or VIL
IOH = − 4 mA
IOH = − 8 mA
VOL
Low−Level
Output Voltage
Vin = VIH or VIL
IOL = 50 mA
Typ
Max
TA = −40 to
85°C
TA = −55 to
+125°C
Min
Min
1.50
VCC x
0.7
0.50
VCC x
0.3
2.0
3.0
4.5
1.9
2.9
4.4
3.0
4.5
2.58
3.94
Max
2.0
3.0
4.5
2.0
3.0
4.5
0.0
0.0
0.0
Max
1.50
VCC x
0.7
Unit
V
0.50
VCC x
0.3
0.50
VCC x
0.3
V
V
1.9
2.9
4.4
1.9
2.9
4.4
2.48
3.80
2.40
3.70
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
IOL = 4 mA
IOL = 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.55
0.55
V
Iin
Input Leakage
Current
Vin = 5.5 V or GND
0 to 5.5
$0.1
$1.0
$2.0
mA
ICC
Quiescent Supply
Current
Vin = VCC or GND
5.5
2.0
20
40
mA
TA = −40 to
85°C
TA = −55 to
+125°C
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25°C
Symbol
Parameter
tPLH,
tPHL
Propagation
Delay, A or B to Y
Cin
Min
Test Conditions
Typ
Max
Min
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
5.5
8.0
7.9
11.4
1.0
1.0
9.5
13.0
1.0
1.0
10
14.5
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
3.7
5.2
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
7.0
9.5
4.0
10
Input
Capacitance
10
10
pF
Typical @ 25°C, VCC = 5.0 V
CPD
19
Power Dissipation Capacitance (Note 5)
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, Measured in SOIC Package)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
− 0.3
− 0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
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3
MC74VHC00
TEST POINT
A or B
VCC
50%
OUTPUT
DEVICE
UNDER
TEST
GND
tPLH
Y
tPHL
C L*
50% VCC
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
ORDERING INFORMATION
Package
Shipping †
MC74VHC00DR2
SOIC−14
2500 / Tape & Reel
MC74VHC00DR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74VHC00DT
TSSOP−14*
96 Units / Rail
MC74VHC00DTG
TSSOP−14*
(Pb−Free)
96 Units / Rail
MC74VHC00DTR2
TSSOP−14*
2500 / Tape & Reel
MC74VHC00DTR2G
TSSOP−14*
(Pb−Free)
2500 / Tape & Reel
MC74VHC00MEL
SOEIAJ−14
2000 / Tape & Reel
MC74VHC00MELG
SOEIAJ−14
(Pb−Free)
2000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MC74VHC00
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE G
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
B
M
7
1
G
F
R X 45 _
C
−T−
0.25 (0.010)
M
T B
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
D 14 PL
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE A
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
G
H
DETAIL E
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5
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74VHC00
PACKAGE DIMENSIONS
SO−14
M SUFFIX
CASE 965−01
ISSUE O
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
1.42
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.056
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