STMicroelectronics M5451Q Led display driver Datasheet

M5450
M5451
LED DISPLAY DRIVERS
Figure 1. Packages
FEATURES SUMMARY
■ M5450 34 OUTPUTS/15mA SINK
■
M5451 35 OUTPUTS/15mA SINK
■
CURRENT GENERATOR OUTPUTS (NO
EXTERNAL RESISTORS REQUIRED)
■
CONTINUOUS BRIGHTNESS CONTROL
■
SERIAL DATA INPUT
■
ENABLE (ON M5450)
■
WIDE SUPPLY VOLTAGE OPERATION
■
TTL COMPATIBILITY
40
1
PDIP40
(Plastic Package)
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Application Examples:
■ MICROPROCESSOR DISPLAYS
■
INDUSTRIAL CONTROL INDICATOR
■
RELAY DRIVER
■
INSTRUMENTATION READOUTS
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PLCC44
(Plastic Chip Carrier)
DESCRIPTION
The M5450 and M5451 are monolithic MOS integrated circuits produced with an N-channel silicon
gate technology. They are available in 40-pin dual
in-line plastic packages.
A single pin controls the LED display brightness by
setting a reference current through a variable resistor connected to VDD or to a separate supply of
13.2V maximum.
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April 2004
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M5450, M5451
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
41
40
VSS
N.C
1
42
OUTPUT BIT 17
2
OUTPUT BIT 18
OUTPUT BIT 16
3
43
OUTPUT BIT 15
4
44
OUTPUT BIT 14
5
36
OUTPUT BIT 22
OUTPUT BIT 13
7
39
OUTPUT BIT 23
OUTPUT BIT 13
6
35
OUTPUT BIT 23
OUTPUT BIT 12
8
38
OUTPUT BIT 24
OUTPUT BIT 12
7
34
OUTPUT BIT 24
OUTPUT BIT 11
9
37
OUTPUT BIT 25
OUTPUT BIT 11
8
33
OUTPUT BIT 25
OUTPUT BIT 10
10
36
OUTPUT BIT 26
OUTPUT BIT 9
11
35
OUTPUT BIT 27
OUTPUT BIT 10
9
32
OUTPUT BIT 26
N.C.
12
34
N.C.
OUTPUT BIT 9
10
31
OUTPUT BIT 27
OUTPUT BIT 8
13
33
OUTPUT BIT 28
OUTPUT BIT 8
11
30
OUTPUT BIT 28
OUTPUT BIT 7
14
32
OUTPUT BIT 29
OUTPUT BIT 6
15
31
OUTPUT BIT 30
OUTPUT BIT 7
12
29
OUTPUT BIT 29
OUTPUT BIT 5
16
30
OUTPUT BIT 31
OUTPUT BIT 6
13
28
OUTPUT BIT 30
OUTPUT BIT 4
17
29
OUTPUT BIT 32
OUTPUT BIT 5
14
27
OUTPUT BIT 31
OUTPUT BIT 4
15
26
OUTPUT BIT 32
OUTPUT BIT 3
16
25
OUTPUT BIT 33
OUTPUT BIT 2
17
24
OUTPUT BIT 34
DATA ENABLE FOR M5450
OUTPUT BIT 35 FOR M5451
Figure 3. Block Diagram
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VDD
BRIGTHNESS
CONTROL
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100kΩ
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OUTPUT
BIT 34
OUTPUT
BIT 1
24
18
23
SERIAL
DATA
22
CLOCK
21
35 OUTPUT BUFFERS
LOAD
35-BIT SHIFT REGISTER
RESET
1
CLOCK IN
N.C
OUTPUT BIT 33
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35 LATCHES
DATA ENABLE (M5450)
OUTPUT35 (5451)
VDD
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OUTPUT BIT 34
CLOCK IN
DATA IN
OUTPUT BIT 35
21
BRIGHTNESS CONTROL
DATA IN
20
OUTPUT BIT 1
22
V DD
OUTPUT BIT 3
23
19
OUTPUT BIT 2
18
28
OUTPUT BIT 21
OUTPUT BIT 14
27
37
26
4
25
OUTPUT BIT 20
OUTPUT BIT 15
24
38
23
3
22
OUTPUT BIT 19
OUTPUT BIT 16
21
OUTPUT BIT 18
39
OUTPUT BIT 1
2/12
5
40
2
19
1
18
V SS
OUTPUT BIT 17
BRIGHTNESS CONTROL
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Figure 2. Pin Connection
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M5450, M5451
Table 1. Absolute Maximum Ratings
Symbol
VDD
Parameter
VI
VO(off)
IO
PTOT
Tj
Value
Unit
Supply Voltage
– 0.3 to 15
V
Input Voltage
– 0.3 to 15
V
Off State Output Voltage
15
V
Output Sink Current
40
mA
Total Package Power Dissipation at 25°C
1
W
Total Package Power Dissipation at 85°C
560
mW
Junction Temperature
150
°C
– 25 to 85
°C
– 65 to 150
°C
TOP
Operating Temperature Range
TSTG
Storage Temperature Range
Note: Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
FUNCTIONAL DESCRIPTION
Both the M5450 and the M5451 are specially designed to operate 4 or 5-digit alphanumeric displays with minimal interface with the display and
the data source. Serial data transfer from the data
source to the display driver is accomplished with 2
signals, serial data and clock. Using a format of a
leading "1" followed by the 35 data bits allows data
transfer without an additional load signal. The 35
data bits are latched after the 36th bit is complete,
thus providing non-multiplexed, direct drive to the
display.
Outputs change only if the serial data bits differ
from the previous time.
Display brightness is determined by control of the
output current LED displays.
A 1nF capacitor should be connected to brightness control, pin 19, to prevent possible oscillations.
A block diagram is shown in Figure 3. For the
M5450 a DATA ENABLE is used instead of the
35th output. The DATA ENABLE input is a metal
option for the M5450.
The output current is typically 20 times greater
than the current into pin 19, which is set by an external variable resistor. There is an internal limiting
resistor of 400W nominal value.
Figure 4 shows the input data format. A start bit of
logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously
with the high state of the clock, which loads the 35
bits of the shift registers into the latches.
At the low state of the clock a RESET signal is
generated which clears all the shift registers for
the next set of data. The shift registers are static
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master-slave configurations. There is no clear for
the master portion of the first shift register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the
shift registers will not clear.
When power is first applied to the chip an internal
power ON reset signal is generated which resets
all registers and all latches. The START bit and the
first clock return the chip to its normal operation.
Bit 1 is the first bit following the start bit and it will
appear on Pin 18. A logical "1" at the input will turn
on the appropriate LED.
Figure 5 shows the timing relationship between
Data, Clock and DATA ENABLE.
A max clock frequency of 0.5MHz is assumed. For
applications where a lesser number of outputs are
used, it is possible to either increase the current
per output or operate the part at higher than 1V
VOUT.
The following equation can be used for calculations.
Tj = [(VOUT) (ILED) (No. of segments) + (VDD ×
7mA)] (124°C/W) + Tamb
where :
Tj = junction temperature (150°C max)
VOUT = the voltage at the LED driver outputs
ILED = the LED current
124°C/W = thermal coefficient of the package
Tamb = ambient temperature
The above equation was used to plot Figure 6, Figure 7 and Figure 8.
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M5450, M5451
Table 2. Static Electrical Characteristics
(Tamb within operating range, VDD = 4.75V to 13.2V, VSS = 0V, unless otherwise specified)
Symbol
Parameter
Test Conditions
VDD
Supply Voltage
IDD
Supply Current
VDD = 13.2V
VI
Input Voltage Logical "0" Level
± 10µA Input Bias
Min.
4.75 ≤ VDD ≤ 5.25
Logical "1" Level
VDD > 5.25
Typ.
Unit
13.2
V
7
mA
- 0.3
0.8
V
2.2
VDD
V
VDD - 2
VDD
V
IB
Brightness Input Current (note 2)
0
0.75
VB
Brightness Input Voltage (pin 19) Input Current = 750µA, Tamb = 25°C
3
4.3
VO(off)
IO
Off State Out. Voltage
13.2
V
10
µA
10
µA
VO = 3V
VO = 1V (note 4)
Segment ON
Brightness In. = 0µA
fclock
IO
Note: 1.
2.
3.
4.
mA
V
Out. Sink Current (note 3)
Segment OFF
0
Brightness In. = 100µ
2
27
Brightness In. = 750µA
12
15
Input Clock Frequency
Output Matching (note 1)
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CLOCK
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(INTERNAL)
RESET
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BIT 1
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36
BIT 34
BIT 35
mA
mA
0.5
MHz
± 20
%
Output matching is calculated as the percent variation from I MAX + IMIN/2.
With a fixed resistor on the brightness input some variation in brightness will occur from one device to another.
Absolute maximum for each output should be limited to 40mA.
The VO voltage should be regulated by the user. See Figure 7 and Figure 8 for allowable VO versus IO operation.
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Figure 4. Input Data Format
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Max.
4.75
M5450, M5451
Figure 5.
Figure 6.
Ptot (W)
1.0
15mA/segment
34 segments
VO = 1V
CLOCK
0.8
0.6
DATA
0.4
300ns (min.)
SAFE OPERATING
AREA
0.2
DATA ENABLE
T amb (˚C)
100ns (min.)
20
0
Figure 7.
3.2
40
Figure 8.
105
20 segments
30 segments
34 segments
2.8
2.4
65
1.6
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2.0
45
1.2
0.8
Tamb = 85˚C
0.4
Tj = 150˚C
˚ (max.)
4
8
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(s)
ILED (mA)
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80
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I0 (mA)
VO (V)
0
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Tamb = 85˚C
IO (max.) = 40mA
VO = 1V
VO = 1.5V
VO = 2V
25
N˚ Segm.
5
0
4
8
12
16 20
24
28 32
36 40
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M5450, M5451
TYPICAL APPLICATIONS
Figure 9. Basic Electronically Tuned Radio Or Tv System
AM
FM
34 SEGMENTS
M5450
DISPLAY
DRIVER
ELECTRONIC
TUNING
CONTROLLER
KEYBOARD
PLL
SYNTHESIZER
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STATION
DETEC. ETC.
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Figure 10. Duplexing 8 Digits With One M5450
VDD
VLED
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28 40
24 31
M5450
18
21
22
19
20
1
CLOCK IN
DATA IN
VDD
BRIGHTNESS
CONTROL
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VDD
VLED
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M5450, M5451
POWER DISSIPATION OF THE IC
The power dissipation of the IC can be limited using different configurations.
Figure 11- In the application R must be chosen
taking into account the worst operating conditions.
The total power dissipation of the IC depends, in a
first approximation, only on the number of segments activated.
Figure 12.
Figure 11.
+VC
+VC
R
ID
VD
VOUT
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R is determined by the maximum number of segments activated
V –V
–V
C
DMAX
OMIN
R = ---------------------------------------------------------------N
L
MAX D
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Figure 13 - In this configuration VOUT + VD is constant. The total power dissipation of the IC depends only on the number of segments activated.
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Figure 13.
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The worst case condition for the device is when
roughly half of the maximum number of segments
are activated.
It must be checked that the total power dissipation
does not exceed the absolute maximum ratings of
the device.
In critical cases more resistors can be used in conjunction with groups of segments.
In this case the current variation in the single resistor is reduced and Ptot limited.
Figure 12 - In this configuration the drop on the serial connected diodes is quite stable if the diodes
are properly chosen.
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+VC
VOUT +VD
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M5450, M5451
PART NUMBERING
Table 3. Order Codes
Part Number
Package
Temperature Range
M5450B7/M5451B7
PDIP40
-25 to 85 °C
M5451Q
PLCC44
-25 to 85 °C
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M5450, M5451
PACKAGE MECHANICAL
Table 4. PDIP40 - Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
a1
0.63
0.025
b
0.45
0.018
b1
0.23
b2
0.31
0.009
1.27
0.012
0.050
D
52.58
E
15.2
2.070
16.68
0.598
0.657
e
2.54
0.100
e3
48.26
1.900
F
14.1
i
4.445
0.175
L
3.3
0.130
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Figure 14. PDIP40 - Package Dimensions
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(t s)
b2
b1
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21
1
20
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0.555
Note: Drawing is not to scale
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M5450, M5451
Table 5. PLCC44 - Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
A
17.4
17.65
0.685
0.695
B
16.51
16.65
0.650
0.656
C
3.65
3.7
0.144
0.146
D
4.2
4.57
0.165
0.180
d1
2.59
2.74
0.102
0.108
d2
0.68
E
14.99
0.027
16
0.590
0.630
e
1.27
0.050
e3
12.7
0.500
F
0.46
0.018
F1
0.71
0.028
uc
0.101
M
1.16
M1
1.14
d
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0.046
P
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Figure 15. PLCC44 - Package Dimensions
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F1
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(t s)
1 44
2
E
M1
6
7
M
F
M1
17
29
18
28
d2
A
d1
G (Seating Plane Coplanarity)
Note: Drawing is not to scale.
0.045
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Max
D
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0.004
M5450, M5451
REVISION HISTORY
Table 6. Revision History
Date
Revision
Description of Changes
September-1993
1
First Issue
14-Mar-2004
2
Stylesheet update. No content change.
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M5450, M5451
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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