FAN6756— mWSaver™ PWM Controller Features Description Single-Ended Topologies, such as Flyback and Forward Converters mWSaver™ Technology The FAN6756 is a next-generation Green Mode PWM controller with innovative mWSaver™ technology, which dramatically reduces standby and no-load power consumption, enabling compliance with worldwide Standby Mode efficiency guidelines. - Achieves Low No-Load Power Consumption: < 30 mW at 230 VAC (EMI Filter Loss Included) - Eliminates X ®Capacitor Discharge Resistor Loss with AX-CAP Technology - Linearly Decreases Switching Frequency to 23 kHz - Burst Mode Operation at Light-Load Condition - Impedance Modulation in “Deep” Burst Mode - Low Operating Current (450 µA) in Deep Burst Mode - 500 V High-Voltage JFET Startup Circuit to Eliminate Startup Resistor Loss Highly Integrated with Rich Features - Proprietary Frequency Hopping to Reduce EMI - High-Voltage Sampling to Detect Input Voltage - Peak-Current-Mode Control with Slope Compensation - Cycle-by-Cycle Current Limiting with Line Compensation - Leading Edge Blanking (LEB) - Built-In 7 ms Soft-Start An innovative AX-CAP® method minimizes losses in the EMI filter stage by eliminating the X-cap discharge resistors while meeting IEC61010-1 safety requirements. “Deep” Burst Mode clamps feedback voltage and modulates feedback impedance with an impedance modulator during Burst Mode operation, which forces the system to operate in a Deep Burst Mode with minimum switching losses. Protections ensure safe operation of the power system in various abnormal conditions. A proprietary frequencyhopping function decreases EMI emission and built-in synchronized slope compensation allows more stable Peak-Current-Mode control over a wide range of input voltage and load conditions. The proprietary internal line compensation ensures constant output power limit over the entire universal line voltage range. Requiring a minimum number of external components, FAN6756 provides a basic platform that is well suited for cost-effective flyback converter designs that require extremely low standby power consumption. Applications Flyback power supplies that demand extremely low standby power consumption, such as: Advanced Protections - Brown-in / Brownout Recovery - Internal Overload / Open-Loop Protection (OLP) - VDD Under-Voltage Lockout (UVLO) - VDD Over-Voltage Protection (VDD OVP) - Over-Temperature Protection (OTP) - Current-Sense Short-Circuit Protection (SSCP) Adapters for Notebooks, Printers, Game Consoles, etc. Open-Frame SMPS for LCD TV, LCD Monitors, Printer Power, etc. Related Resources Evaluation Board: FEBFAN6756MR_T03U065A Ordering Information Part Number Protections(1) OLP OVP OTP SSCP FAN6756MRMY A/R L L A/R FAN6756MLMY L L L A/R Operating Temperature Range -40 to +105°C Package Packing Method 8-Pin, Small Outline Tape & Reel Package (SOP) Note: 1. A/R = Auto Recovery Mode protection, L = Latch Mode protection. © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com FAN6756— mWSaver™ PWM Controller January 2013 FAN6756— mWSaver™ PWM Controller Application Diagram Figure 1. Typical Application Internal Block Diagram Figure 2. Functional Block Diagram © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 2 FAN6756— mWSaver™ PWM Controller Marking Information ZXYTT 6756ML TPM Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die Run Code T - Package Type (M=SOP) P - Y: Green Package M - Manufacture Flow Code ZXYTT 6756MR TPM Figure 3. Top Mark Pin Configuration SOP-8 GND 1 8 GATE FB 2 7 VDD NC 3 6 SENSE HV 4 5 RT Figure 4. Pin Configuration (Top View) Pin Definitions Pin # Name 1 GND 2 FB Feedback. The output voltage feedback information from the external compensation circuit is fed into this pin. The PWM duty cycle is determined by comparing the FB signal with the currentsense signal from the SENSE pin. 3 NC No Connection HV High-Voltage Startup. The HV pin is typically connected to the AC line input through two external diodes and one resistor (RHV). This pin is used, not only to charge the VDD capacitor during startup, but also to sense the line voltage. The line voltage information is used for brownout protection and power-limit line compensation. This pin also is used to intelligently discharge the EMI filter capacitor when removal of the AC line voltage is detected. 5 RT Over-Temperature Protection. An external NTC thermistor is connected from this pin to GND. Once the voltage of the RT pin drops below the threshold voltage, the controller latches off the PWM. The RT pin also provides external latch protection. If the RT pin is not connected to the NTC resistor for over-temperature protection, it is recommended to place a 100 kΩ resistor to ground to prevent noise interference. 6 SENSE 7 VDD 8 GATE 4 Description Ground. Placing a 0.1 µF decoupling capacitor between VDD and GND is recommended. Current Sense. The sensed voltage is used for Peak-Current-Mode control, short-circuit protection, and cycle-by-cycle current limiting. Power Supply of IC. Typically a hold-up capacitor connects from this pin to ground. A rectifier diode, in series with the transformer auxiliary winding, connects to this pin to supply bias during normal operation. Gate Drive Output. The totem-pole output driver for the power MOSFET; internally limited to VGATE-CLAMP. © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit (2,3) VVDD DC Supply Voltage 30 V VFB FB Pin Input Voltage -0.3 7.0 V SENSE Pin Input Voltage -0.3 7.0 V -0.3 VSENSE VRT RT Pin Input Voltage 7.0 V VHV HV Pin Input Voltage 500 V PD Power Dissipation (TA＜50°C) 400 mW JA Thermal Resistance (Junction-to-Air) 150 C/W TJ Operating Junction Temperature -40 +125 C Storage Temperature Range -55 +150 C Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 C Human Body Model, JEDEC:JESD22-A114 All Pins Except HV Pin(4) 6000 Charged Device Model, JEDEC:JESD22-C101 All Pins Except HV Pin(4) 2000 TSTG TL ESD V Notes: 2. All voltage values, except differential voltages, are given with respect to the network ground terminal. 3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 4. ESD level on HV pin is CDM=1250 V and HBM=500 V. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. We does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol RHV Parameter Resistance on HV Pin © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 Min. Typ. Max. Unit 150 200 250 kΩ www.fairchildsemi.com 4 FAN6756— mWSaver™ PWM Controller Absolute Maximum Ratings VDD=15 V and TJ=TA=25°C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit VDD Section VDD-ON Threshold Voltage to Startup VDD Rising 16 17 18 V VUVLO Threshold Voltage to Stop Switching in Normal Mode VDD Falling 5.5 6.5 7.5 V Threshold Voltage to Enable HV VRESTART Startup to Charge VDD in Normal Mode VDD Falling 4.7 V VDD-OFF Threshold Voltage to Stop Operating in Protection Mode VDD Falling 10 11 12 V VDD-OLP Threshold Voltage to Enable HV Startup to Charge VDD in Protection Mode VDD Falling 6 7 8 V VDD-LH Threshold Voltage to Release Latch Mode VDD Falling 3.5 4.0 4.5 V VDD-AC Threshold Voltage of VDD pin for Enabling Brown-in VUVLO +2.5 VUVLO+3 VUVLO +3.5 V IDD-ST Startup Current VDD=VDD-ON – 0.16 V 30 µA IDD-OP1 Supply Current in PWM Operation VDD=15 V, VFB = 3 V, Gate Open 1.8 mA IDD-OP2 Supply Current when PWM Stops VDD=15 V, VFB <1.4 V, Deep Burst Mode, Gate Off IDD-OLP Internal Sink Current, VDD-OLP<VDD<VDD-OFF, Protection Mode VDD= VDD-OLP + 0.1 V ILH 450 µA FAN6756MRMY 90 140 190 µA FAN6756MLMY 160 210 260 µA Internal Sink Current, VDD<VDD-OLP, VDD = 5 V Latch-Protection Mode 30 µA VDD-OVP Threshold Voltage for VDD Over-Voltage Protection 23.5 24.5 25.5 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time 110 205 300 µs VDD-ZFBR VDD Threshold Voltage for FB-Pin Impedance Modulation in Deep Burst Mode 7 V Continued on the following page… © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 5 FAN6756— mWSaver™ PWM Controller Electrical Characteristics VDD=15 V and TJ=TA=25C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit 1.50 3.25 5.00 mA HV Section Maximum Supply Current, HV Pin VAC=90 V(VDC=120 V), VDD=0 V VAC-OFF Threshold Voltage for Brownout DC Source Series R=200 kΩ to HV Pin 90 100 110 V VAC-ON Threshold Voltage for Brown-in DC Source Series R=200 kΩ to HV Pin 100 110 120 V △VAC VAC-ON – VAC-OFF DC Source Series R=200 kΩ to HV Pin 8 12 16 V 40 65 90 ms IHV tD-AC-OFF Debounce Time for Brownout tS-WORK Work Period of HV-Sampling Circuit in Deep Burst Mode Deep Burst Mode, VFB<VFB-ZDC-DBM 95 140 185 ms tS-REST Rest Period of HV-Sampling Circuit in Deep Burst Mode Deep Burst Mode, VFB<VFB-ZDC-DBM 180 260 320 ms VHV-DIS X-Cap. Discharge Threshold RHV=200 kΩ to HV Pin VDC(5) ×0.45 VDC ×0.51 VDC ×0.56 V tD-HV-DIS Debounce Time for Triggering X-Cap. Discharge 75 115 155 ms tHV-DIS Discharge Time when X-Cap. Discharge is Triggered 360 510 660 ms 62 65 68 (5) (5) Oscillator Section Center Frequency fOSC Switching Frequency when VFB>VFB-N Hopping Range ±3.55 ±4.25 ±4.95 tHOP Hopping Period(6) VFB>VFB-G 5.12 6.40 7.68 ms fOSC-G Switching Frequency when VFB<VFB-G VFB<VFB-G 20 23 26 kHz fDV Frequency Variation vs. VDD Deviation VDD=11 to 22 V 5 % fDT Frequency Variation vs. Temperature Deviation TA=-40 to 105C 5 % kHz Continued on the following page… © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 6 FAN6756— mWSaver™ PWM Controller Electrical Characteristics (Continued) VDD=15 V and TJ=TA=25C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit 1/4.5 1/4.0 1/3.5 V/V Feedback Input Section AV Feedback Voltage to CurrentSense Attenuation ZFB Regular FB Internal Pull-High Impedance VFB-OPEN FB Internal Biased Voltage VFB-OLP 8.5 5.2 5.4 5.6 V Threshold Voltage for OLP 4.3 4.6 4.9 V tD-OLP Delay for OLP 45.0 57.5 70.0 ms VFB-N Threshold Voltage for Maximum Switching Frequency 2.6 2.8 3.0 V VFB-G Threshold Voltage for Minimum Switching Frequency 2.1 2.3 2.5 V VFB-ZDCR FB Threshold Voltage for ZeroDuty Recovery 1.9 2.1 2.3 V VFB-ZDC FB Threshold Voltage for ZeroDuty 1.8 2.0 2.2 V 2.5 2.7 2.9 V 2.35 2.55 2.75 V VFB-ZDCRDBM VFB-ZDCDBM tDBM tD-DBM VFBRECOVER FB Threshold Voltage for ZeroDuty Recovery in Deep Burst Mode FB Pin Open kΩ VDD=VUVLO+0.3 V FB Threshold Voltage for ZeroDuty in Deep-Burst Mode Condition of Triggering Deep Burst Mode VFB<VFB-ZDC Repeats 3 Times Continuously Delay time of Entering Deep Burst Mode Threshold Voltage for Leaving Deep Burst Mode Immediately 7.5 ms 600 Deep Burst Mode, VDD>VDD-ZFBR and Gate Off ms 0.9 V Current-Sense Section tPD Propagation Delay to Output tLEB Leading Edge Blanking Time 100 250 ns 200 265 330 ns VLIMIT-L Current Limit at Low Line (VAC-RMS=86 V) VDC=122 V, Series R=200 kΩ to HV 0.43 0.46 0.49 V VLIMIT-H Current Limit at High Line (VAC-RMS=259 V) VDC=366 V, Series R=200 kΩ to HV 0.36 0.39 0.42 V VSSCP-L Threshold Voltage for SSCP at Low Line (VAC-RMS=86 V) VDC=122 V, Series R=200 kΩ to HV 30 50 70 mV VSSCP-H Threshold Voltage for SSCP at High Line (VAC-RMS=259 V) VDC=366 V, Series R=200 kΩ to HV 80 100 120 mV tON-SSCP Minimum On-time of Gate to Trigger SSCP VSENSE<VSSCP-(L/H) 4.00 4.55 5.10 µs Debounce Time for SSCP VSENSE<VSSCP-(L/H) 110 170 230 µs Soft-Start Time Startup 5 7 9 ms tD-SSCP tSS Continued on the following page… © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 7 FAN6756— mWSaver™ PWM Controller Electrical Characteristics (Continued) VDD=15V and TJ=TA=25C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit 75.0 82.5 90.0 % 1.5 V GATE Section DCYMAX Maximum Duty Cycle VGATE-L Gate Low Voltage VDD=15 V, IO=5 mA VGATE-H Gate High Voltage VDD=1 V, IO=5 mA tr Gate Rising Time VDD=1 V, CL= nF 110 ns tf Gate Falling Time VDD=15 V, CL=1 nF 40 ns Gate Output Clamping Voltage VDD=22 V VGATECLAMP nSKIP 8 V 11.0 14.5 18.0 V Continuously Gate Switching Number for (6) Leaving Deep-Burst Mode 112 pulses Output Current of RT Pin 100 µA RT Section IRT VRTTH1 Threshold Voltage for Over-Temperature Protection VRTTH2 < VRT <VRTTH1, Latch Off After 14.5 ms 1.000 1.035 1.070 V VRTTH2 Threshold Voltage for Latch Triggering VRT < VRTTH2, Latch Off After 185 µs 0.65 0.70 0.75 V 9.66 10.50 11.34 kΩ ROTP Maximum External Resistance of RT Pin to Trigger Latch Protection tD-OTP1 Debounce Time for Over-Temperature Protection Triggering VRTTH2 < VRT < VRTTH1 11.0 14.5 18.0 ms tD-OTP2 Debounce Time for Latch Triggering VRT < VRTTH2 110 185 260 µs Over-Temperature Protection Section (OTP) TOTP TRESTART Protection Junction Temperature(6,7) (6) Restart Junction Temperature +135 °C TOTP-25 °C Notes: 5. VDC is VAC × √2. 6. Guaranteed by design. 7. When activated, the output is stopped until junction temperature drops below TRESTART. © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 8 FAN6756— mWSaver™ PWM Controller Electrical Characteristics (Continued) Figure 5. Startup Current (IDD-ST) vs. Temperature Figure 6. Operation Supply Current (IDD-OP1) vs. Temperature Figure 7. Start Threshold Voltage (VDD-ON) vs. Temperature Figure 8. Minimum Operating Voltage (VUVLO) vs. Temperature Figure 9. OFF-State Internal Sink Current Under Protection Mode (IDD-OLP) vs. Temperature Figure 10. Minimum Operating Voltage Under Protection Mode (VDD-OFF) vs. Temperature Figure 11. Threshold Voltage to Enable HV startup in Protection Mode (VDD-OLP)vs. Temperature Figure 12. Threshold Voltage to Release Latch Mode (VDD-LH) vs. Temperature © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 9 FAN6756— mWSaver™ PWM Controller Typical Performance Characteristics Figure 13. VDD Over-Voltage Protection (VDD-OVP) vs. Temperature Figure 14. Frequency in Normal Mode (fOSC) vs. Temperature 70 65 60 55 50 45 40 35 30 25 20 2.1 2.3 2.5 2.7 2.9 3.1 3.3 Figure 15. PWM Switching Frequency vs. Feedback Voltage (VFB) Figure 16. Maximum Duty Cycle (DCYMAX) vs. Temperature 0.56 RHV= 200kΩ 0.54 0.52 0.5 0.48 0.46 0.44 0.42 0.4 0.38 0.36 100 150 200 250 300 350 400 Figure 17. Current Limit (VLIMIT) vs. HV Voltage (VHV) Figure 18. FB-Pin Internal Bias Voltage (VFB-OPEN) vs. Temperature Figure 19. Open-Loop Protection Triggering Level (VFB-OLP) vs. Temperature Figure 20. Delay Time of Open-Loop Protection (tD-OLP) vs. Temperature © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 10 FAN6756— mWSaver™ PWM Controller Typical Performance Characteristics (Continued) Figure 21. Brown-in (VAC-ON) vs. Temperature Figure 22. Brownout (VAC-OFF) vs. Temperature Figure 23. Inherent Current Limit of HV-Pin (IHV) vs. Temperature Figure 24. Output Current from RT Pin (IRT) vs. Temperature Figure 25. Over-Temperature Protection Threshold Voltage (VRTTH1) vs. Temperature Figure 26. Over-Temperature Protection Threshold Voltage (VRTTH2) vs. Temperature © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 11 FAN6756— mWSaver™ PWM Controller Typical Performance Characteristics (Continued) fS Current Mode Control FAN6756 employs Peak-Current Mode control, as shown in Figure 27. An opto-coupler (such as the H11A817A) and a shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor makes it possible to control the switching duty cycle. The built-in slope compensation stabilizes the current loop and prevents sub-harmonic oscillation. fOSC fOSC-G VFB-ZDC1 VFB-ZDCR1 VFB-G VFB-N VFB Figure 28. VFB vs. PWM Frequency Figure 27. Current-Mode Control Circuit Diagram Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time, tLEB, is introduced. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. mWSaver™ Technology Green-Mode FAN6756 modulates the PWM frequency as a function of the FB voltage to improve the medium- and light-load efficiency, as shown in Figure 28. Since the output power is proportional to the FB voltage in Current-Mode control, the switching frequency decreases as load decreases. In heavy-load conditions, the switching frequency is fixed at 65 kHz. Once VFB decreases below VFB-N (2.8 V), the PWM frequency starts linearly decreasing from 65 kHz to 23 kHz to reduce switching losses. As VFB drops to VFB-G (2.3 V), where switching frequency is decreased to 23 kHz, the switching frequency is fixed to avoid acoustic noise. When VFB falls below VFB-ZDC (2.0 V) as load decreases further, the FAN6756 enters Burst Mode, where PWM switching is disabled. Then the output voltage starts to drop, causing the feedback voltage to rise. Once VFB rises above VFB-ZDCR (2.1 V), switching resumes. Burst Mode alternately enables and disables switching, thereby reducing switching loss for lower power consumption, as shown in Figure 29. © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 Figure 29. Burst Switching in Green Mode Deep Burst Mode & Feedback Impedance Switching Deep Burst Mode is defined as a special operational mode to minimize power consumption at extremely lightload or no-load condition where, not only the switching loss, but also power consumption of the FAN6756 itself, are reduced further than in Green Mode. Deep Burst Mode is initiated when the non-switching state of burst switching in Green Mode persists longer than tDBM (7.5 ms) for three consecutive burst switchings (as shown in Figure 30). To prevent entering Deep Burst Mode during dynamic load change, there is tD-DBM (>600 ms) delay. If there are more than 112 consecutive switching pulses during the tD-DBM delay, the FAN6756 does not go into Deep Burst Mode. Once the FAN6756 enters Deep Burst Mode, the feedback impedance, ZFB, is modulated by the impedance modulator, as shown in Figure 31. When VFB is under a threshold level, the impedance modulator clamps VFB and disables switching. When VDD drops to VDD-ZFBR (7 V, which is 0.5 V higher than VUVLO), the impedance modulator controls ZFB, allowing VFB to rise and resume switching operation. As shown in Figure 32, by clamping VFB to disable switching while modulating ZFB to enable switching, the system is forced into a “Deep” Burst Mode to reduce switching loss. Deep Burst Mode maintains VDD as low as possible so power consumption can be minimized. When the FAN6756 enters Deep Burst Mode, several blocks are disabled and the operation current is reduced from IDD-OP1 (1.8 mA) to IDD-OP2 (450 µA). www.fairchildsemi.com 12 FAN6756— mWSaver™ PWM Controller Functional Description The FAN6756 exits Deep Burst Mode after more than 112 consecutive switching pulses in Deep Burst Mode. Once the FAN6756 exits Deep Burst Mode, the feedback impedance is modulated to 8.5 k to keep the original loop response. The FAN6756 also exits Deep Burst Mode when the opto-coupler transistor current is virtually zero and VFB rises above VFB-RECOVER (0.9 V) while switching is suspended. High-Voltage Startup and Line Sensing The HV pin is typically connected to the AC line input through two external diodes and one resistor (RHV), as shown in Figure 33. When the AC line voltage is applied, the VDD hold-up capacitor is charged by the line voltage through the diodes and resistor. After VDD voltage reaches the turn-on threshold voltage (VDD-ON), the startup circuit charging the VDD capacitor is switched off and VDD is supplied by the auxiliary winding of the transformer. Once the FAN6756 starts, it continues operating until VDD drops below 6.5 V (VUVLO). IC startup time with a given AC line input voltage is given as: tSTARTUP RHV CDD ln VAC IN VAC IN 2 2 2 2 (1) VDD ON Figure 30. Entering Deep Burst Mode FAN6756 Figure 33. Startup Circuit 5.4V VDD Sensed Current Signal + PWM Comparator Impedance Modulator 3R 1R ZFB 2 VFB FB CFB Figure 31. Feedback Impedance Modulation The HV pin detects the AC line voltage using a switched voltage divider that consists of external resistor (RHV) and internal resistor (RLS), as shown in Figure 33. The internal line-sensing circuit detects line voltage using a sampling circuit and peak-detection circuit. Since the voltage divider causes power consumption when it is switched on, the switching is driven by a signal with a very narrow pulse width to minimize power loss. The sampling frequency is adaptively changed according to the load condition to minimize power consumption in light-load condition. Based on the detected line voltage, brown-in and brownout thresholds are determined as: V R VBROWN - IN (RMS) HV AC ON (2) V R VBROWNOUT (RMS) HV AC OFF (3) 200k 200k 2 2 Since the internal resistor (RLS=1.6 kΩ) of the voltage divider is much smaller than RHV, the thresholds are given as a function of RHV. Note: 8. VDD must be larger than VDD-AC to start, even though the sensed line voltage satisfies Equation (2), as shown in Figure 34. Figure 32. Operation in Deep Burst Mode © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 13 FAN6756— mWSaver™ PWM Controller The feedback voltage thresholds where FAN6756 enters and exits Burst Mode change from VFB-ZDC (2.0 V) and VFB-ZDCR (2.1 V) to VFB-ZDC-DBM (2.55 V) and VFB-ZDCRDBM (2.7 V) in Deep Burst Mode. This reduces the switching loss more by increasing the energy delivered to the load per switching operation, which eventually reduces the total switching for a given load condition. FAN6756 has pulse-by-pulse current limit as shown in Figure 35, which limits the maximum input power with a given input voltage. If the output consumes beyond this maximum power, the output voltage drops, triggering the overload protection. As shown in Figure 35, based on the line voltage, PK VLINE ; the high/low line compensation block adjusts the current limit level, VLIMIT, defined as: VLIMIT VLIMIT H VLIMIT L RLS 3V V VLINEPK LIMIT L LIMIT H 2 RHV 2 (4) To maintain the constant output power limit regardless of line voltage, the cycle-by-cycle current limit level, VLIMIT, decreases as line voltage increases. The current limit level is proportional to the RHV resistor value and power limit can be tuned using the RHV resistor. Figure 36 shows how the pulse-by-pulse current limit changes with the line voltage for different RHV resistors. Figure 34. Timing Diagram for Brown-in Function AX-CAP® Discharge The EMI filter in the front end of the switched-mode power supply (SMPS) typically includes a capacitor across the AC line connector (CX). Most of the safety regulations, such as UL 1950 and IEC61010-1, require that the capacitor be discharged to a safe level within a given time when the AC plug is abruptly removed from its receptacle. Typically, discharge resistors across the capacitor are used to make sure that capacitor is discharged naturally, which introduces power loss as long as it is connected to the receptacle. Fairchild’s innovative AX-CAP® technology intelligently discharges the filter capacitor only when the power supply is unplugged from the power outlet. Since the discharging circuit is disabled in normal operation, the power loss in the EMI filter can be virtually removed. The discharge of the capacitor is achieved through the HV pin. Once AC outlet detaching is detected, the HV pin behaves as a resistor to ground, so the charges on the capacitor can be discharged through the RHV in series with the internal resistor of the HV pin. Since the HV-pin internal resistor is much smaller than RHV, the time constant of discharging process is almost RHV•CX. © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 Figure 35. Pulse-by-Pulse Current Limit Circuit 0.5 0.48 0.46 0.44 0.42 0.4 0.38 0.36 0.34 0.32 0.3 100 150 200 250 300 350 400 Figure 36. Current Limit vs. Line Voltage Soft-Start An internal soft-start circuit progressively increases the pulse-by-pulse current-limit level of MOSFET for 7 ms during startup to establish the correct working conditions for transformers and capacitors. www.fairchildsemi.com 14 FAN6756— mWSaver™ PWM Controller High / Low Line Compensation for Constant Power Limit FAN6756 provides full protection functions, including Overload / Open-Loop Protection (OLP), VDD OverVoltage Protection (OVP), Over-Temperature Protection (OTP), and Current-Sense Short-Circuit Protection (SSCP). SSCP is implemented as Auto-Restart Mode, while OVP and OTP are implemented as Latch Mode protections. OLP is Auto-Restart Mode for FAN6756MRMY and Latch Mode for FAN6756MLMY. When an Auto-Restart Mode protection is triggered, switching is terminated and the MOSFET remains off, causing VDD to drop. When VDD drops to the VDD-OFF (11 V), the protection is reset. When VDD drops further to VDD-OLP (7 V), the internal startup circuit is enabled and the supply current drawn from HV pin charges the holdup capacitor. When VDD reaches the turn-on voltage of 17 V, normal operation resumes. In this manner, auto restart alternately enables and disables the MOSFET switching until the abnormal condition is eliminated. When a Latch Mode protection is triggered, PWM switching is terminated and the MOSFET remains off, causing VDD to drop. When VDD drops to the VDD-OLP (7 V), the internal startup circuit is enabled without resetting the protection and the supply current drawn from HV pin charges the hold-up capacitor. Since the protection is not reset, the IC does not resume PWM switching even when VDD reaches the turn-on voltage of 17 V, disabling HV startup circuit. Then VDD drops again down to 7 V. In this manner, the Latch Mode protection alternately charges and discharges VDD until there is no more energy delivered into HV pin. The protection is reset when VDD drops to 4 V, which is allowed only after power supply is unplugged from the AC line. VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents IC damage from voltage exceeding the IC voltage rating. When the VDD voltage exceeds 24.5 V, the protection is triggered. This protection is typically caused by an open circuit in the secondary-side feedback network. Over-Temperature Protection (OTP) and External Latch Triggering The RT pin provides adjustable Over-Temperature Protection (OTP) and external latch triggering function. For OTP, an NTC thermistor, RNTC, usually in series with a resistor RA, is connected between the RT pin and ground. The internal current source, IRT (100 µA), introduces voltage on RT as: VRT I RT (RNTC RA ) (5) Open-Loop / Overload Protection (OLP) Because of the pulse-by-pulse current-limit capability, the maximum peak current is limited and, therefore, the maximum input power is also limited. If the output consumes more than this limited maximum power, the output voltage (VO) drops below the set voltage. Then the currents through the opto-coupler and transistor become virtually zero and VFB is pulled HIGH. Once VFB is higher than VFB-OLP (4.6 V) for longer than tD-OLP (57.5 ms), OLP is triggered. OLP is also triggered when the feedback loop is open by soldering defect. Sense Short-Circuit Protection (SSCP) The FAN6756 provides safety protection for Limited Power Source (LPS) test. When the current-sense resistor is short circuited by a soldering defect during production, current-sensing information is not properly obtained, resulting in unstable power supply operation. To protect the power supply against a short circuit across the current-sense resistor, FAN6756 shuts down when current sense voltage is very low; even with a relatively large duty cycle. As shown in Figure 37, the currentsense voltage is sampled tON-SSCP (4.55 µs) after the gate turn-on. If the sampled voltage (VS-CS) is lower than VSSCP for 11 consecutive switching cycles (170 µs), the FAN6756 shuts down immediately. VSSCP varies linearly with line voltage. At 122 V DC input, it is typically 50 mV (VSSCP-L); at 366 V DC, it is typically 100 mV (VSSCP-H). Figure 37. Timing Diagram of SSCP Two-Level Under-Voltage Lockout (UVLO) As shown in Figure 38, as long as protection is not triggered, the turn-off threshold of VDD is fixed internally at VUVLO (6.5 V). When a protection is triggered, the VDD level to terminate PWM gate switching is changed to VDD-OFF (11 V), as shown in Figure 39. When VDD drops below VDD-OFF, the switching is terminated and the operating current from VDD is reduced to IDD-OLP to slow down the discharge of VDD until VDD reaches VDD-OLP. This delays re-startup after shutdown by protection to minimize the input power and voltage / current stress of switching devices during a fault condition. At high ambient temperature, RNTC decreases, reducing VRT. When VRT is lower than VRTTH1 (1.035 V) for longer than tD-OTP1 (14.5 ms), the protection is triggered and the FAN6756 enters Latch Mode protection. The OTP can be trigged by pulling down the RT pin voltage using an opto-coupler or transistor. Once VRT is less than VRTTH2 (0.7 V) for longer than tD-OTP2 (185 µs), the protection is triggered and the FAN6756 enters Latch Mode protection. When OTP is not used, place a 100 kΩ resistor between this pin and ground to prevent noise interference. © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 Figure 38. VDD UVLO at Normal Mode www.fairchildsemi.com 15 FAN6756— mWSaver™ PWM Controller Protections 17V The BiCMOS output stage has a fast totem-pole gate driver. The output driver is clamped by an internal 14.5 V Zener diode to protect the power MOSFET gate from over voltage. A soft driving is implemented to minimize Electromagnetic Interference (EMI) by reducing the switching noise. 11V VDD-OFF VDD-OLP 7V GATE t Figure 39. VDD UVLO at Protection Mode Typical Application Circuit Application PWM Controller Input Voltage Range Output 65 W Notebook Adapter FAN6756MRMY 85 VAC ~ 265 VAC 19 V, 3.42 A Figure 40. Schematic of Typical Application Circuit © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 www.fairchildsemi.com 16 FAN6756— mWSaver™ PWM Controller Gate Output / Soft Driving VDD VDD-ON FAN6756— mWSaver™ PWM Controller Transformer Schematic Diagram Core: Ferrite Core RM-10 Bobbin: RM-10 Figure 41. Transformer Specification Winding Specification Pin (Start --> Finish) Wire Turns Winding Method Remark 4→5 0.5φ×1 19 Solenoid Winding Enameled Copper Wire N1 Insulation: Polyester Tape, t = 0.025 mm, 1-Layer Shielding: Adhesive Tape of Copper Foil, t = 0.025×7 mm, 1.2-Layer Open Loop, Connected to Pin 4. Insulation: Polyester Tape t = 0.025 mm, 3-Layer N2 S→F 0.9φ×1 8 Solenoid Winding Triple Insulated Wire 7 Solenoid Winding Enameled Copper Wire Insulation: Polyester Tape, t = 0.025 mm, 3-Layer N3 9→7 0.4φ×1 Insulation: Polyester Tape, t = 0.025 mm, 1-Layer Shielding: Adhesive Tape of Copper Foil, t = 0.025×7mm, 1.2-Layer Open Loop, Connected to Pin 4. Insulation: Polyester Tape t = 0.025 mm, 3-Layer N4 5→6 0.5φ×1 19 Solenoid Winding Enameled Copper Wire Insulation: Polyester Tape t = 0.025 mm, 3-Layer Electrical Characteristics Pin Specification Remark Primary-Side Inductance 4－6 510 H ±5% 1 kHz, 1 V Primary-Side Effective Leakage Inductance 4－6 20 H Maximum Short All Other Pins Typical Performance Power Consumption Input Voltage 230 VAC Output Power Actual Output Power Input Power Specification No Load 0W 0.024 W Input Power < 0.03 W 0.25 W 0.232 W 0.339 W Input Power < 0.5 W 0.5 W 0.495 W 0.643 W Input Power < 1 W Efficiency Output Power 16.25 W 32.5 W 48.75 W 65 W Average 115 V, 60 Hz 88.48% 88.58% 87.45% 86.22% 87.68% 230 V, 60 Hz 88.00% 87.89% 87.92% 87.47% 87.82% © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 17 5.00 4.80 A 0.65 3.81 8 5 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45° 0.25 R0.10 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.406 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 42. 8-Pin SOP-8 Package Package drawings are provided as a service to customers considering our components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact our representative to verify or obtain the most recent revision. Package specifications do not expand the terms of our worldwide terms and conditions, specifically the warranty therein, which covers our products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 18 FAN6756— mWSaver™ PWM Controller Physical Dimensions FAN6756— mWSaver™ PWM Controller © 2011 Fairchild Semiconductor Corporation FAN6756 • Rev. 2.0.0 19 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor: FAN6756MLMY FAN6756MRMY FAN6756AMRMY FAN6756AMLMY