TI BQ29311 Three and four cell lithium ion or lithium polymer battery protection ic Datasheet

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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
FEATURES
D 3- or 4-Cell Series Protection Control
D Autonomous Overcurrent and Short Circuit
Protection
D Provides Individual Cell Voltages to Battery
Management Host
D Integrated Cell Balancing Control
D I2C Compatible User Interface Allows Access
to Battery Information
D User Control to Initiate Protection
D Integrated 3.3-V 25-mA LDO
D Programmable Shutdown and Brownout
Control
D Provides Drive for Three External FETs
D Low Supply Current of 140 µA Typical
D Programmable Threshold and Delay for
Short-Circuit Current Protection
D Provides Drive for Three External FETs
D Can Directly Interface With bq2083/5 for
Complete Battery Management Solution
DESCRIPTION
The bq29311 is a three- or four-cell lithium-ion battery
pack protection analog front end (AFE) IC that
incorporates a 3.3-V 25-mA low-dropout regulator
(LDO) and an I2C compatible interface to extract battery
parameters such as cell voltages and control output
status. Other parameters, such as overcurrent
protection threshold and delay, can also be
programmed into the bq29311 to increase the flexibility
of the battery management system.
The bq29311 provides safety protection in overcurrent,
short circuit, overvoltage, and undervoltage conditions
via control from the battery management host. In
overcurrent and short-circuit conditions the bq29311
can directly activate the FET drive as a secondary
protection level. The communications interface allows
the host to control and observe the current status of the
protection, to set overcurrent and overload levels, to set
the overcurrent and overload blanking delay time,
short-circuit threshold levels, and short-circuit blanking
delay time, and to program for the VREG shutdown
voltage and brownout-detection thresholds.
APPLICATIONS
D Notebook Computer Battery Packs
D Test Equipment
Each cell is balanced by a discharge path, which is
enabled by the internal control registers accessible
through the I2C compatible interface. The maximum
current is set by an external series resistor with an
absolute maximum value of 10 mA discharge current
per cell.
PIN ASSIGNMENTS
ORDERING INFORMATION
PW PACKAGE
(TOP VIEW)
VCC
VBAT
VC1
VC2
VC3
VC4
VC5
SR1
SR2
CNTL
GND
VCELL
1
2
3
4
5
6
7
8
9
10
11
12
TA
24
23
22
21
20
19
18
17
16
15
14
13
VPACK
DSG
PCHG
CHG
LEDOUT
VREG
TOUT
XALERT
CLKIN
SDATA
SCLK
GND
−25°C to 85°C
PACKAGED TSSOP
(PW)
bq29311PW
bq29311PWR(1)
(1) R suffix indicates tape and reel.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
! " #$%! " &$'#! (!%) ($#!"
# ! "&%##!" &% !*% !%" %+" "!$%!" "!(( ,!-)
($#! &#%"". (%" ! %#%""'- #'$(% !%"!. '' &%!%")
Copyright  2001 − 2003, Texas Instruments Incorporated
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
PW
874 mW
DERATING FACTOR
ABOVE TA = 25°C
6.99 W/°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
559 mW
454 mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
bq29311
Supply voltage range(2)
VCC, VPACK
VC1, VC2, VC3, VC4, VBAT
−0.3 V to 34 V
−0.3 V to 34 V
VC5, SR1, SR2
Input voltage range
−1 V to 1 V
VC1 to VC2, VC2 to VC3, VC3 to VC4, VC4 to VC5
−0.3 V to 8.5 V
CLK-IN, SCLK, SDATA
Output voltage range
−0.3 V to 7 V
CNTL
−0.3 V to 34 V
DSG, CHG, PCHG
−0.3 V to VCC
LEDOUT, TOUT, SCLK, SDATA, VCELL, XALERT
−0.3 V to 7 V
Current for cell balancing
10 mA
Continuous total power dissipation
ESD rating(3)
See Dissipation Rating Table
HBM
1.5 kV
CDM
250 V
MM
50 V
Operating free-air temperature range, TA
−25°C to 85°C
Storage temperature range, Tstg
−65°C to 150°C
Lead temperature (soldering, 10 s)
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground of this device except VCn-VC(n+1), where n = 1, 2, 3, 4 cell voltage.
(3) Design considerations should be made with respect to excessive ESD.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
Supply voltage (VCC or VPACK)
VBAT
VC1, VC2, VC3, VC4
SR1, SR2, VC5
Input voltage range, VI
VCn−VC(n+1), (n = 1, 2, 3, 4 )
0
Output current, IO
VIH
VIL
SCLK, SDATA, CLK−IN
0
−0.5
0.5
0
5
0.8×VREG
VREG
0
0.2×VREG
200
50
VCELL
± 10
CNTL
VREG
V
VREG
SDATA
External 3.3-V VREG capacitor, C(REG)
2
V
XALERT
Input current, II
Operating ambient temperature range, TA
UNIT
25
VCC
VCC
CNTL
Logic level input voltage
MAX
−0.5
1
µA
µA
µF
1
−25
V
85
°C
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS
TA = 25°C, CREG = 1 µF, VCC = 14 V (unless otherwise noted)
SUPPLY CURRENT
PARAMETER
I(CC1)
Supply current 1
I(CC2)
Supply current 2
TEST CONDITIONS
No load at VREG, TOUT,
LEDOUT, XALERT, SCLK,
SDATA. CLKIN not used
VBAT ≤ VSD, VPACK = 0
DSG, CHG and PCHG = off
MIN
TA = 25°C
TYP
MAX
140
190
TA = − 25°C to 85°C
220
TA = − 25°C to 85°C
1
UNIT
µA
µA
3.3 V REGULATOR
PARAMETER
V(REG)
Regulator output voltage
TEST CONDITIONS
IO ≤ 25 mA,
∆V(REGTEMP)
Regulator output change with
temperature
∆V(REGLINE)
∆V(REGLOAD)
Line regulation
V(SD) = 6.5 V ≤ VCC ≤ 25 V,
IO = 25 mA
V(SD) =6.5 V ≤ VCC ≤ 25V,
Load regulation
0.1 mA ≤ IO ≤ 25 mA,
TA = − 25°C to 85°C
TA = −25°C to 25°C
MIN
TYP
MAX
UNIT
3.135
3.3
3.465
V
± 0.2% ± 1.74%
± 0.2% ± 1.74%
TA = 25°C to 85°C
IO = 25 mA
VCC = 14 V
6
20
mV
2
20
mV
SHUTDOWN VI MONITOR
PARAMETER
TEST CONDITIONS
V(SD)
∆V(SD)
VREG shutdown threshold range(1)
Measured at VBAT
Shutdown threshold steps
Set by SDV register b0 −b3
Vhys(SD)
Hysteresis
MIN
TYP
6.475
MAX
10.975
300
35
50
UNIT
V
mV
65
mV
± 5%
Accuracy of the shutdown threshold
(1) V(SD) = V(REG) brownout threshold voltage as determined by b0 −b3 in the SDV register.
BROWNOUT VIN MONITOR
PARAMETER
TEST CONDITIONS
VBO
∆VBO
Brownout threshold range(1)
Measured at VBAT
Brownout threshold steps
Set by SDV register b4 − b7
Vhys(BO)
Hysteresis
MIN
TYP
7.975
MAX
12.475
300
35
50
65
UNIT
V
mV
± 5%
Brownout threshold accuracy
(1) VBO = V(REG) brownout threshold voltage as determined by b4 −b7 in the SDV register.
CELL VOLTAGE MONITOR
PARAMETER
TEST CONDITIONS
V(CELL_OUT)
VCELL output (see Note 4)
V(CELL_IN) = 0 V
V(CELL_IN) = 4.5 V
V(CELL_IN)
Differential Input voltage range
VC1 to VC2, VC2 to VC3,
VC3 to VC4, VC4 to VC5
K
VCELL scale factor
[0.975 −V(CELL_OUT) ]/V(CELL_IN)
R(BAL)
Cell balance internal resistance
RDS(ON) for internal FET switch at V(DS) = 2 V
MIN
TYP
MAX
0.975
V
0.3
0
0.144
4.5
0.150
500
UNIT
V
0.156
Ω
(1) The V(CELL) output is inversely proportional to the V(CELL_OUT) = −K × V(CELL_IN) + 0.975.
3
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS CONTINUED
TA = 25°C, CREG = 1 µF, VCC = 14 V (unless otherwise noted)
OVERCURRENT (OC) AND SHORT CIRCUIT (SC) DETECTION
PARAMETER
TEST CONDITIONS
MIN
205
Discharge (overload)
−50
−205
∆V(OCD)
OC detection threshold program step
Vhys(OCD)
OC detection threshold hysteresis
Charge and discharge (overcurrent and overload)
V(SC)
SC detection threshold range,
typical(2)
Charge
∆V(SC)
SC detection threshold program step
Vhys(SC)
SC detection threshold hysteresis
V(SC_acr)
Charge (overcurrent)
5
Discharge (overload)
−5
Discharge
7
mV
13
mV
mV
−100
−475
25
mV
−25
Charge and discharge
Charge and discharge
Charge and discharge
mV
475
Discharge
SC detection threshold accuracy(2)
10
UNIT
100
Charge
OC detection threshold accuracy(1)
MAX
50
V(OCD)
V(OCD_acr)
TYP
Charge (overcurrent)
OC detection threshold range,
typical(1)
40
50
60
V(OCD) = 50 mV (min)
V(OCD) = 100 mV
37.5
50
62.5
85
100
115
V(OCD) = 205 mV (max)
V(SC) = 100 mV (min)
174
205
236
75
100
125
V(SC) = 200 mV
V(SC) = 475 mV (max)
170
200
230
403
475
547
MIN
TYP
MAX
1
5
7
mV
mV
mV
(1) See OCVD and OCVC registers for setting detection threshold.
(2) See SCV register for setting detection threshold.
FET DRIVE CIRCUIT
PARAMETER
V(FETOL)
V(FETCLAMP)
TEST CONDITIONS
Output voltage
Output clamp voltage
VBAT = 16 V
DSG
VPACK = 16 V
CHG
1
5
7
VPACK = 16 V
PCHG
8.5
10.5
11.5
VPACK = 4.5 V
PCHG
3.3
3.5
3.7
10
100
DSG
tr
Rise time
CL = 4700 pF, 10% to 90%
CHG
Fall time
CL = 4700 pF, 90% to 10%
V
V
µs
10
100
170
500
DSG
15
100
CHG
15
100
170
500
TYP
MAX
UNIT
50
100
Ω
2.9
3.15
3.46
V
MIN
TYP
MAX
UNIT
60
100
140
6
10
14
PCHG
tf
UNIT
PCHG
µs
THERMISTOR DRIVE AND LED DRIVE
PARAMETER
TEST CONDITIONS
R(t)
TOUT pass-element series resistance
IO = −1 mA at TOUT pin,
R(t) = (VREG – VTOUT )/1 mA,
TA = − 25°C to 85°C
V(LEDOUT)
LEDOUT output voltage
IO = − 25 mA at LEDOUT pin,
TA = − 25°C to 85°C
MIN
LOGIC
PARAMETER
R(PUP)
VO(L)
4
Internal pullup resistance
Logic low-level output voltage
TEST CONDITIONS
XALERT, CLKIN
SDATA, SCLK
XALERT, IOUT = 200 µA
SDATA, IOUT = 50 µA
TA = − 25°C to 85°C
0.2
0.4
kΩ
V
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS CONTINUED
TA = 25°C, CREG = 1 µF, VCC = 14 V (unless otherwise noted)
AC
PARAMETER
TEST CONDITIONS
f(CLKIN)
t(CLKIN_HI)
CLKIN input frequency
External clock
CLKIN high time
External clock
f(INTERNAL)
Internal clock frequency
t(SCDDELAY)
SC delay time
TA = − 25°C to 85°C
td(SC) = 0 ms for charge and discharge
V(OCD) = 100 mV, SR(50%) to DSG/CHG(50%) delay.
No load.
MIN
TYP
MAX
32.100 32.768 33.420
2
28
26.2 32.768
39.4
1
10
UNIT
kHz
µs
kHz
µs
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
CHG
21
Push-pull output charge FET gate voltage supply
CLKIN
16
Digital input that provides an alternate clock with internal 100-kΩ pullup to VREG
CNTL
10
Active low input enables CHG, DSG and PCHG. Internal pullup
DSG
23
Push-pull output discharge FET gate voltage supply
GND
11, 13
Analog ground pin and negative pack terminal
LEDOUT
20
Provides current to drive LED capacity display
PCHG
22
Push-pull output precharge FET gate voltage supply
SCLK
14
Open-drain bidirectional serial interface clock with internal 10-kΩ pullup to VREG
SDATA
15
Open-drain bidirectional serial interface data with internal 10-kΩ pullup to VREG
SR1
8
Current sense positive terminal when charging relative to SR2
SR2
9
Current sense positive terminal when discharging relative to SR1
TOUT
18
Provides thermistor bias current
VBAT
2
Battery positive terminal sense input for regulator shutdown
VC1
3
Sense voltage input terminal for most positive cell and balance current input for most positive cell. Connected to VC2 in 3-cell
applications
VC2
4
Sense voltage input terminal for second most positive cell, balance current input for second most positive cell, and return
balance current for most positive cell
VC3
5
Sense voltage input terminal for third most positive cell, balance current input for third most positive cell and return balance
current for second most positive cell
VC4
6
Sense voltage input terminal for least positive cell, balance current input for least positive cell, and return balance current
for third most positive cell
VC5
7
Sense voltage input terminal for most negative cell, return balance current for least positive cell
VCC
1
Diode protected BAT+ terminal and primary power source
VCELL
12
Output of scaled value of the measured cell voltage
VPACK
24
Pack positive terminal and alternate power source
VREG
19
Integrated 3.3-V regulator output
XALERT
17
Open-drain output used to indicate status register changes. With internal 100 kΩ pullup to VREG
5
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
FUNCTIONAL BLOCK DIAGRAM
Pack+
VCC
CNTL
DSG
1
CNTL
CHG
VPACK
PCHG
21
23
24
22
VREG
10
1uA
CHG/DSG
Output Control
PCHG
Output Control
Thermistor Drive
18
TOUT
VBAT
2
3.3V
Regulator
EN
VC1
3
Cell
Select
VC2
VC3
5
VC4
Network Switch
4
Input
Shutdown
Monitor
CLKGEN
Delay
Control
19 VREG
To internal
Circuitry
100k
VREF
Startup
Balance
Back-Up
CLK
Input
Brownout
Monitor
6
Cell
Voltage
Monitor
VC5
20 LEDOUT
LED Drive
Status
Logic
17
XALERT
16
CLKIN
100k
7
− OC for Discharge
− OC for Charge
− SC for Discharge
SR1
8
Over-Current
Short-Current
Sensing
SR2
9
− Brownout
− SC for Charge
VCELL
12
Pack−
Cell
Select
GND
OCVD/OCVC
SCV
OCD/SCD
Control
SDV
13
VREG
VREG
11
Communication
10k
6
Status
10k
20
15
SCLK
SDATA
GND
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
AC TIMING SPECIFICATIONS (I2C COMPATIBLE SERIAL INTERFACE)
tsu(STA)
tw(H)
tf
tw(L)
tr
SCLK
tr
SDATA
Start
Condition
SDA
Input
1
SCLK
Stop
Condition
SDA
Change
th(DAT)
th(STA)
tf
2
th(ch)
tsu(DAT)
3
7
8
9
MSB
SDATA
ACK
Start Condition
tv
tsu(STOP)
SCLK
SDATA
1
2
3
MSB
7
8
9
tsu(BUF)
ACK
Stop Condition
PARAMETER
MIN
MAX
UNIT
300
ns
300
ns
300
ns
300
ns
tr
tf
Clock rise time
tr(SDA)
tf(SDA)
SDA rise time
20
SDA fall time
20
tsu(STA)
tw(H)
Clock high to input transition setup time
600
ns
Clock pulse width high
600
ns
th(STA)
th(DAT)
Input low to clock low hold time start condition
600
ns
0
µs
tw(L)
tsu(DAT)
Clock pulse width low
1.3
µs
Input transition to clock transition setup time
100
ns
tsu(STOP)
tsu(BUF)
Clock high to input high (STOP) setup time stop condition
600
ns
Input high to input low (bus free)
1.3
µs
tv
th(CH)
Clock low to data out valid time
200
Data out hold time after clock low
200
f(CLK)
Clock frequency
Clock fall time
Clock low to input transition hold time
900
ns
ns
100
kHz
7
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
APPLICATION INFORMATION
PRECHARGE MODE CURRENT LIMITING RESISTOR SELECTION
The selection of this resistor value should take into account the maximum potential charge voltage, which should include
the voltage of a failed charger to ensure that 0-V and pre-charge mode current levels are within desirable limits under all
conditions.
I(PCHG)
RDS(ON)
BAT
PACK+
R(PCHG)
I (PCHG) +
VPACK(max) * VBAT(min)
RDS(ON) ) R(PCHG)
22
PCHG
UDG−01148
Figure 1. Pre-Charge Mode Current Limiting Resistor Selection
This method ensures that the resistor is sized correctly to provide safe zero voltage charging and the optimal performance
during precharge.
8
7
6
5
4
3
10
2
1
23
SR1
8
VC5
VC4
VC3
VC2
VC1
CNTL
VBAT
DSG
VCC
CHG
21
19
24
CLKIN
XALERT
SDATA
SCLK
LEDOUT
12
16
17
15
14
20
VREG
TOUT 18
VPACK
VCELL
SR2 GND GND
9
13 11
PCHG
22
LED1 24
NC 25
LED3 22
LED2 23
VSSD VSSD VSSD VSSA
19
11
38
30
29 VSSP
5 NC
37 NC
27 SR2
4 NC
13 NC
NC 36
EVENT 18
LED5 20
LED4 21
17 DISP
35 CLKOUT
28 SR1
OC 3
TS 2
XCK2 33
XCK1 34
FILT 32
SMBC 15
SMBD 16
31
VCCA
10 SDATA
6 SCLK
7 NC
8
VCCD
1 VIN
14 NC
26 MRST
9
RBI
12 SAFE
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
Figure 2. bq29311 Application Circuit Example Including Battery Management Host Controller
9
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
FUNCTIONAL DESCRIPTION
INTEGRATED REGULATOR
The input for this regulator is derived from the battery cell
stack or the pack positive terminal, with a valid range of
VSD to 25 V. These two source inputs are ORed internally.
An external diode is required to protect uncontrolled
charging. The output is typically 3.3 V ±5% (TA = −25_C to
85_C) with a maximum output current of 25 mA. The output
capacitance for stable operation is typically 1 µF. The
output voltage line regulation is ±20 mV (max) between
VSD and 25 V. The load regulation is ±20 mV (max) over
the current range of 0. 1 mA to 25 mA.
The regulator output starts up only when VPACK reaches
the valid input voltage. After this voltage is reached, the
bios of the regulator is supplied through VBAT from the
battery, even if VPACK voltage is removed.
SHUTDOWN AND BROWNOUT
If the voltage at VBAT falls below 7.975 V± 5%(default), the
bq29311 sets the BRWO bit to 1 in STATUS (b4) and
triggers the XALERT output. The value in the SDV register
(b4−b7) determines the threshold value and this can be
programmed from 7.975 V to 12.475 V in 0.3-V steps (with
an accuracy of ±5% at the falling edge) and has 50 mV
±30% of hysteresis.
Reading the STATUS register clears XALERT in a
brownout, but OCL (CONTROL, b0) must be taken from
0 to 1 to 0; then STATUS must be read, to clear the BRWO
bit.
If the voltage at VBAT is below 6.475V ±5% (default) the
regulator can be shut down. The value in the SDV register
(b0−3) determines the threshold value, which can be
programmed from 6.475 V to 10.975 V in 0.3-V steps with
an accuracy of ±5% at the falling edge and has 50 mV
±30% of hysteresis.
When the input voltage is below the shutdown threshold
and a higher voltage at VPACK is not present, then SHDN
(STATUS, b5) is set and the bq29311 enters the sleep
mode and turns off CHG, DSG, and PCHG. The current
consumption in this mode is under 1 µA. SHDN is cleared
when the input voltage rises above the shutdown
threshold. XALERT does not respond to shutdown.
OVERCURRENT, OVERLOAD,AND
SHORT-CIRCUIT DETECTION
The overcurrent, overload, and short-circuit detection is
used to detect abnormal current in either the charge or
discharge direction. This safety feature is used to protect
the pass FETs, cells, and any other inline components
from excessive current conditions. The detection circuit
also incorporates a blanking delay before driving the
control for the pass FETs to turn off.
10
The overcurrent, overload, and short-circuit thresholds are
set in the OCVD/C and SCV registers with defaults of
50 mV and 100 mV respectively. The individual
overcurrent (charge) , and overload (discharge) thresholds
can be programmed from 50 mV to 205 mV in 5-mV steps
with a hysteresis of 10 mV ±30%. The single short-circuit
threshold can be programmed from 100 mV to 475 mV in
25-mV steps with a hysteresis of 50 mV ±20%.
OVERCURRENT, OVERLOAD AND
SHORT-CIRCUIT DELAY
The overcurrent and overload delays allow the system to
momentarily accept a high current condition. The default
overcurrent delay is 1 ms. The delay time can be increased
via the OCD register, where the overcurrent and overload
delays can be independently defined. The OCD register
can be programmed for a range of 1 ms to 31 ms with steps
of 2 ms.
The short-circuit delay has a default value of 0 ms and is
also programmable in the SCD register. This register can
be programmed from 0 to 915 µs with steps of 61 µs.
OVERCURRENT, OVERLOAD AND
SHORT-CIRCUIT RESPONSE
When an overcurrent, overload, or short-circuit condition
is detected, the CHG and DSG FETs are turned off and the
PCHG FET turned on, limiting the charge current to the
pre-charge rate. The STATUS (b0...b3) register reports the
details of discharge short circuit, charge short circuit,
overload (discharge overcurrent) and overcurrent. The
respective STATUS (b0...b3) bits are set to 1 and the
XALERT output changes state. This condition is latched
until the CONTROL (b0) is set and then reset. If a FET is
turned on by resetting CONTROL (b0) and the error
condition is still on the system, then the device again
enters the protection response state.
CELL VOLTAGE
The cell voltage is translated to allow a system host to
measure individual series elements of the battery.
The series element voltage is translated to a GND-based
voltage equal to 0.15 of the series element voltage. This
provides a range from 0 V to 4.5 V. The translation output
is inversely proportional to the input.
V(CELL_OUT) = −K × V(CELL_IN) + 0.975 (V)
Programming CELL_SEL (b0...b1) selects the individual
series element. The CELL_SEL (b2 . . . b3) selects the
measurement mode for the series elements. This allows
the offset to be determined for each element in the string.
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
CALIBRATION OF CELL VOLTAGE MONITOR
AMPLIFIER GAIN
The cell voltage monitor amplifier has an offset, which can
be calibrated to increase accuracy.
The following procedure shows how to measure and
calculate the offset:
1.
Set CAL2=0, CAL1=1, VM1=0, VM0=0
The output voltage includes the offset and is
represented by
VOUT1 = 0.975 + (1 + K) × VOS (V)
where K = VCELL scaling factor
VOS = offset voltage at input of the internal op-amp
2.
Set CAL2=1, CAL1=0, VM1=0, VM0=0
The output voltage includes the scale factor error and
offset and is represented by
VOUT2 = 0.975 + (1 + K) × VOS – K × 0.975 (V)
3.
Calculate (VOUT1 – VOUT2)/0.975
The result is the actual scaling factor, KACT and is
represented by
KACT = (VOUT1–V OUT2)/0.975 = (0.975 + (1 + K) ×
VOS) − (0.975 + (1 + K) × VOS – K × 0.975)/0.975
= K × 0.975/0.975 = K
4.
Calculate the actual offset value where
VOS(ACT) = (VOUT1 – 0.975)/(1 + KACT)
5.
Calibrated cell voltage is calculated by
VCn − VC(n+1) = [0.975 + (1 + KACT ) × VOS(ACT) –
VCELLOUT]/KACT
The default-state of the FET drive is off. A host can control
the FET drive by programming CONTROL (b1...b2) where
b1 is used to control the external discharge FET and b2 is
used to control the external charge FET. These controls
are valid only when shutdown is not active.
PCHG FET DRIVER CONTROL
The PCHG FET is used when the battery is under voltage,
allowing limited conditioning current modes such as
pre-charge and 0 V charging. At startup of the bq29311
(charger connected to battery pack), PCHG is clamped to
3.5 V when VPACK is 3.8 V to 5.25 V. Thus the actual
VPACK voltage is decided with this PCHG clamp voltage
and the VGS(gate-source voltage) of external precharge
FET. When VPACK is over 5.25 V, PCHG voltage would
be controlled to two-thirds of VPACK.
The default state of PCHG is on. There are two methods
to pull up PCHG to turn off precharge FET. One is through
the control register via serial communication. Setting b3 in
the control register to 1 turns off the precharge FET.
Another method is to use CNTL. Floating CNTL or pulling
CNTL up to VREG turns off the precharge FET and also
the CHG and DSG FETs.
Overcurrent, overload, and short-circuit detection is not
applied during precharge operations. An external resistor
located in series with the external precharge FET limits the
current flow for precharge operations.
20.0
The cell balance control allows a small discharge to be
controlled for any one series element. The purpose of this
discharge is to bring the series elements to the same
voltage. Series resistors placed between the input pins
and the positive series element nodes control the
discharge current value.
Individual series element selection is made using
CELL_SEL (b4...b7). Cell balance discharge is also
disabled if bits CELL_SEL (b4...b7) are zero. When all
CELL_SEL (b4…b7) bits are set to 1, then all series
elements are discharged.
VPCHG − Push-Pull Output Voltage − V
CELL BALANCE CONTROL
16.7
15.0
10.0
5.0
3.5
DSG AND CHG FET DRIVER CONTROL
The bq29311 drives the FET off if an OC or SC safety
threshold is breached. The host can force any FET on or
off only if the bq29311 integrated protection control allows.
The DSG and CHG FET drive gate-to-drain voltage is
clamped to 15 V (max) and 11 V (typ).
0
3.8 5.25
10
15
20
25
VPACK − Pack Positive Voltage − V
30
Figure 3. PCHG Drive Output vs. Pack Voltage
(Design Simulation)
11
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
THERMISTOR DRIVE CIRCUIT
The TOUT pin can be enabled to drive a thermistor from
VREG. The typical thermistor resistance is 10 kΩ at 25°C.
The default-state for this is OFF to conserve power. The
maximum output impedance is 100 Ω. TOUT (b6 of the
control register) enables or disables this function. TOUT
(b6 of CONTROL register) enables or disables this
feature.
LED DRIVE CIRCUIT
The LED drive provides a current source from VREG.
LEDEN (b5 of the control register) enables or disables this
function.
Transitions of the CLKIN pin hold off the internal oscillator
so if the external input stops oscillating, the internal
oscillator starts and enables all the timing functions.
COMMUNICATIONS
The I2C compatible serial communications provides read
and write access to the bq29311 data area. The data is
clocked via separate data (SDATA) and clock (SCLK) pins.
The bq29311 acts as a slave device and does not generate
clock pulses. Communication to the bq29311 can be
provided from GPIO pins or an I2C supporting port of a host
system controller. The slave address for the bq29311 is 7
bits and the value is 0100 000 (0x20).
ADDRESS (0X20)
CONTROL INPUT (CNTL)
The control input is pulled up internally to VREG, which
disables all the FET outputs. When CNTL is pulled to
GND, the bq29311 control outputs are then controlled by
safety and register control logic. An external pullup can be
added to enable a pullup to a higher voltage. This could
cause up to an extra 100 µA leakage through the CNTL
input to GND.
5
4
3
2
1
0
0
1
0
0
0
0
0
The bq29311 does not have the following functions
compatible with the I2C specification.
D
D
The bq29311 is always regarded as a slave.
D
The bq29311 does not support the address auto
increment, which allows continuous reading and
writing.
D
The bq29311 allows data to be written or read from the
same location without resending the location address.
CLOCK INPUT (CLKIN)
The clock input allows for an external time base to be used
for increased accuracy in delay timing when determining
overcurrent and short-circuit holdoff. The standard
frequency is 32.768 kHz but must be above 30 kHz. This
input is pulled up via an internal 100-kΩ resistor.
6
The bq29311 does not support the general code of the
I2C specification and therefore does not return an
ACK, but returns a NACK instead.
SCLK
SDATA
A6
A5
A4
A0 R/W
ACK
0
Start
R7
R6
R5
R0 ACK
0
D7
D6
D5
D0
0
Slave Address
ACK
0
Register Address
Data
NOTE: Slave = bq29311
Figure 4. I2C-Bus Write to bq29311
SCLK
SDATA
Start
A6
A5
A0 R/W ACK
0
Slave Address
0
R7
R6
R0 ACK
Register
Address
A6
A0
R/W ACK
1
0
Slave Address
NOTE: Slave = bq29311
Figure 5. I2C-Bus Read from bq29311: Protocol A
12
D7
D6
Slave
Drives
The Data
D0
NACK
Master
Drives
NACK
and Stop
Stop
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
SCLK
A6
SDATA
Start
A5
A0 R/W ACK
0
Slave Address
R7
R6
0
R0 ACK
Register
Address
A6
A5
Stop
Start
A0 R/W ACK D7
Slave Address
D0
Slave
Drives
The Data
NOTE: Slave = bq29311
NACK
Master
Stop
Drives
NACK
and Stop
Figure 6. I2C-Bus Read from bq29311: Protocol B
REGISTER MAP
The bq29311 has nine addressable registers. These registers provide status, control, and configuration information for the
battery-protection system. All registers except for status are read/write. All registers are reset on power up of the bq29311.
ADDRESS
TYPE
STATUS
NAME
0x00
R
DESCRIPTION
CONTROL
0x01
R/W
bq29311 control from system host
SDV
0x02
R/W
Brownout/shutdown threshold voltage
OCVD
0x03
R/W
Overcurrent threshold voltage for discharge (overload)
OCVC
0x04
R/W
Overcurrent threshold voltage for charge
OCD
0x05
R/W
Overcurrent and overload delay time
CELL_SELECT
0x06
R/W
Battery cell select for cell translation and balance discharge
SCV
0x07
R/W
Short-circuit threshold voltage for discharge and charge
SCD
0x08
R/W
Short-circuit delay time for discharge and charge
bq29311 status
STATUS register
STATUS REGISTER (0X00)
7
6
5
4
3
2
1
0
−
−
SHDN
BRWO
OCCHG
OCDSG
SCCHG
SCDSG
The status register provides information about the current state of the bq29311. Reading the status register clears the
XALERT pin after OCL (CONTROL, b0) has been cleared unless otherwise stated.
STATUS b0 (SCDSG): This bit indicates a short circuit in the discharge direction.
0 = below the short-circuit threshold in the discharge direction (default)
1 = greater than or equal to the short-circuit threshold in the discharge direction
STATUS b1 (SCCHG): This bit indicates a short-circuit in the charge direction.
0 = below the short-circuit threshold in the charge direction (default)
1 = greater than or equal to the short-circuit threshold in the charge direction
STATUS b2 (OCDSG): This bit indicates an overload condition.
0 = less than or equal to the overcurrent threshold in the discharge direction (default)
1 = greater than overcurrent threshold in the discharge direction
STATUS b3 (OCCHG): This bit indicates an overcurrent condition.
0 = less than or equal to the overcurrent threshold in the charge direction (default)
1 = greater than overcurrent threshold in the charge direction
STATUS b4 (BRWO): This bit indicates that the brownout voltage threshold has been reached.
0 = greater than the brownout threshold (default)
1 = less than or equal to the brownout threshold voltage
STATUS b5 (SHDN): This bit shows that the battery voltage has fallen below the shutdown threshold limit, indicating a
shutdown condition.
0 = greater than the shutdown threshold voltage (default)
1 = less than or equal to the shutdown threshold voltage
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
CONTROL REGISTER
CONTROL REGISTER (0X01)
7
6
5
4
3
2
1
0
SVDOFF
TOUT
LEDEN
VMOFF
PCHG
CHG
DSG
OCL
The CONTROL register controls the outputs of the bq29311 and can be used to clear certain states set by any OC, SC
or brownout condition. The OCL latch must be cleared before the STATUS register is read to clear the register.
CONTROL b0 (OCL): This bit releases the overcurrent latch when toggled from 0 to 1 back to 0 (default = 0) after the latch
has been set by any OC or SC condition.
CONTROL b1 (DSG): This bit controls the external discharge FET.
0 = discharge FET is off and is controlled by the system host (default)
1 = discharge FET is on and the bq29311 is in normal operating mode
CONTROL b2 (CHG): This bit controls the external charge FET.
0 = charge FET is off and is controlled by the system host (default)
1 = charge FET is on and the bq29311 is in normal operating mode.
CONTROL b3 (PCHG): This bit controls the external precharge FET.
0 = precharge FET is on and controlled by the system host for enabling a charge path prior to turning on the
charge FET (default)
1 = precharge FET is off.
CONTROL b4 (VMOFF): This bit enables or disables the voltage monitoring translation function and cell balance
discharge.
0 = enables voltage monitoring (default)
1 = disables voltage monitoring
CONTROL b5 (LEDEN): This bit enables or disables the LED driver function
0 = disables LED drive function (default)
1 = enables LED drive function
CONTROL b6 (TOUT): This bit controls the VCC power to the thermistor.
0 = thermistor power is off (default)
1 = thermistor power is on
CONTROL b7 (SDVOFF): This bit enables or disables the shutdown monitor function.
0 = shutdown monitor enabled (default)
1 = shutdown monitor disabled
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
SDV: SHUTDOWN VOLTAGE
SDV REGISTER (0X02)
7
6
5
4
3
2
1
0
BOV3
BOV2
BOV1
BOV0
SDV3
SDV2
SVD1
SDV0
The SDV register is used to configure the regulator shutdown and brownout thresholds. 00000000 is the default.
SDV b3...b0 With Corresponding Threshold
0000
6.475 V
0100
7.675 V
1000
8.875 V
1100
10.075 V
0001
6.775 V
0101
7.975 V
1001
9.175 V
1101
10.375 V
0010
7.075 V
0110
8.275 V
1010
9.475 V
1110
10.675 V
0011
7.375 V
0111
8.575 V
1011
9.775 V
1111
10.975 V
SDV b7...b4 With Corresponding Threshold
0000
7.975 V
0100
9.175 V
1000
10.375 V
1100
11.575 V
0001
8.275 V
0101
9.475 V
1001
10.675 V
1101
11.875 V
0010
8.575 V
0110
9.775 V
1010
10.975 V
1110
12.175 V
0011
8.875 V
0111
10.075 V
1011
11.275 V
1111
12.475 V
OCVD: OVERCURRENT (OVERLOAD) VOLTAGE THRESHOLD IN DISCHARGE
OCVD REGISTER (0X03)
7
6
5
4
3
2
1
0
−
−
−
OCVD4
OCVD3
OCVD2
OCVD1
OCVD0
OCVD b0−b4 (OCVD0−OCVD4): These five bits select the value of the overcurrent threshold in the discharge direction.
00000 is the default.
OCVD b4...b0 With Corresponding Threshold
00000
0.050 V
01000
0.090 V
10000
0.130 V
11000
0.170 V
00001
0.055 V
01001
0.095 V
10001
0.135 V
11001
0.175 V
00010
0.060 V
01010
0.100 V
10010
0.140 V
11010
0.180 V
00011
0.065 V
01011
0.105 V
10011
0.145 V
11011
0.185 V
00100
0.070 V
01100
0.110 V
10100
0.150 V
11100
0.190 V
00101
0.075 V
01101
0.115 V
10101
0.155 V
11101
0.195 V
00110
0.080 V
01110
0.120 V
10110
0.160 V
11110
0.200 V
00111
0.085 V
01111
0.125 V
10111
0.165 V
11111
0.205 V
OCVC: OVERCURRENT VOLTAGE THRESHOLD REGISTER
OCVC REGISTER (0X04)
7
6
5
4
3
2
1
0
−
−
−
OCVC4
OCVC3
OCVC2
OCVC1
OCVC0
OCVC b0−b4 (OCVC0 −OCVC4): These five bits select the value of the overcurrent threshold in the charge direction.
00000 is the default.
OCVC b4...b0 With Corresponding Threshold
00000
0.050 V
01000
0.090 V
10000
0.130 V
11000
0.170 V
00001
0.055 V
01001
0.095 V
10001
0.135 V
11001
0.175 V
00010
0.060 V
01010
0.100 V
10010
0.140 V
11010
0.180 V
00011
0.065 V
01011
0.105 V
10011
0.145 V
11011
0.185 V
00100
0.070 V
01100
0.110 V
10100
0.150 V
11100
0.190 V
00101
0.075 V
01101
0.115 V
10101
0.155 V
11101
0.195 V
00110
0.080 V
01110
0.120 V
10110
0.160 V
11110
0.200 V
00111
0.085 V
01111
0.125 V
10111
0.165 V
11111
0.205 V
15
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
OCD: OVERCURRENT/OVERLOAD BLANKING DELAY
OCD REGISTER (0X05)
7
6
5
4
3
2
1
0
OCDC3
OCDC2
OCDC1
OCDC0
OCDD3
OCDD2
OCDD1
OCDD0
This register is used to set the overcurrent and overload delay times.
OCD b0−b3 (OCDD0−OCDD3): These four bits select the value of the delay time for overcurrent triggering in the discharge
direction. 0000 is the default.
OCD b3...b0 With Corresponding Delay Time
0000
1 ms
0100
9 ms
1000
17 ms
1100
25 ms
0001
3 ms
0010
5 ms
0101
11 ms
1001
19 ms
1101
27 ms
0110
13 ms
1010
21 ms
1110
29 ms
0011
7 ms
0111
15 ms
1011
23 ms
1111
31 ms
OCD b4−b7 (OCDC0−OCDC3): These four bits select the value of the delay time for overcurrent triggering in the charge
direction. 0000 is the default.
OCD b7...b4 With Corresponding Delay Time
0000
1 ms
0100
9 ms
1000
17 ms
1100
25 ms
0001
3 ms
0010
5 ms
0101
11 ms
1001
19 ms
1101
27 ms
0110
13 ms
1010
21 ms
1110
0011
7 ms
29 ms
0111
15 ms
1011
23 ms
1111
31 ms
SCV: SHORT-CIRCUIT THRESHOLD VOLTAGE
SCV REGISTER (0X07)
7
6
5
4
3
2
1
0
−
−
−
−
SCV3
SCV2
SCV1
SCV0
This register selects the common short-circuit threshold voltage for both charge and discharge.
SCV b0−b3 (SCV0−SCV3): These four bits select the value of the short-circuit voltage threshold for both charge and
discharge. 0000 is the default.
SCV b0...b3 With Corresponding Threshold Voltage
0000
0.10V
0100
0.20V
1000
0.30V
1100
0.40V
0001
0.125V
0101
0.225V
1001
0.325V
1101
0.425V
0010
0.150V
0110
0.250V
1010
0.350V
1110
0.450V
0011
0.175V
0111
0.275V
1011
0.375V
1111
0.475V
SCD: SHORT-CIRCUIT BLANKING DELAY
SCD REGISTER (0X08)
7
6
5
4
3
2
1
0
SCDC3
SCDC2
SCDC1
SCDC0
SCDD3
SCDD2
SCDD1
SCDD0
This register selects the short-circuit blanking delay time for charge and discharge.
SCD b0−b3 (SCDD0−SCDD3): These four bits select the value of the short-circuit delay time for discharge. Exceeding
the short-circuit voltage threshold for longer than this period turns off the DSG output. 0000 is the default.
SCD b3...b0 With Corresponding Delay Time
0 µs
0100
244 µs
1000
488 µs
1100
732 µs
0001
61 µs
0101
305 µs
1001
549 µs
1101
793 µs
0010
122 µs
0110
366 µs
1010
610 µs
1110
854 µs
0011
183 µs
0111
427 µs
1011
671 µs
1111
915 µs
0000
SCD b4−b7 (SCDC0−SCDC3): These four bits select the value of the short-circuit delay time for charge. Exceeding the
short-circuit voltage threshold for longer than this period turns off the CHG output.
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
SCD b7...b4 With Corresponding Delay Time
0 µs
0100
244 µs
1000
488 µs
1100
732 µs
0001
61 µs
0101
305 µs
1001
549 µs
1101
793 µs
0010
122 µs
0110
366 µs
1010
610 µs
1110
854 µs
0011
183 µs
0111
427 µs
1011
671 µs
1111
915 µs
0000
CELL_SELECT: CELL SELECTION
CELL_SELECT REGISTER (0X06)
7
6
5
4
3
2
1
0
CELL4
CELL3
CELL2
CELL1
CAL1
CAL0
VM1
VM0
This register determines cell selection for voltage measurement and translation, cell balancing and the operational mode
of the cell voltage monitoring.
CELL_SELECT b0−b1 (VM0−VM1)
These two bits select the series cell for voltage measurement translation.
VM1
VM0
0
0
Bottom series element (default)
SELECTED CELL
0
1
Second lowest series element
1
0
Second highest series element
1
1
Top series element
CELL_SELECT b2−b3 (CAL0, CAL1): These bits determine the mode of the voltage monitor block.
CAL1
CAL0
MEASUREMENT MODE
0
0
Cell translation for selected cell (default)
0
1
Offset measurement for selected cell
1
x
Monitor the VREF value for gain calibration
CELL_SELECT b3 −b6 (CELL1 −CELL4): These four bits select the series cell for cell balance discharge. Cell balance
discharge is disabled if bits b4...b7 are set to zero (default), and all cells are discharged if bits b4...b7 are set to 1.
CELL1 =1 = bottom series element
CELL2 =1 = second lowest series element
CELL3 =1 = second highest series element
CELL4 =1 = top series element
Figure 2 shows a typical application for the bq29311 smart lithium-ion battery protector. All functions required to protect
three- or four-series lithium-ion cells from overcharge and over-discharge, as well as provide short-circuit protection, are
included in a single chip.
An R-C filter is recommended at the VCELL pin where R(VCELL) = 100 Ω (typ) and C(VCELL) = 100 nF (typ)
CELL CONNECTION ORDER
The cells should be connected in the following order: Bat− to VC5, Bat+ to VC1, top of bottom cell to VC4, top of second
cell to VC3 and top of third cell to VC2.
3 OR 4 CELL CONFIGURATION
The 4-series cell configuration is shown in Figure 1. In a 3-cell configuration, VC1 is shorted to VC2, and R3 and C13 are
removed. VC2, VC3, VC4, and VC5 pins are used for three cells.
17
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SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°−ā 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
18
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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