Infineon HYE25L256160AC-75 256-mbit mobile-ram Datasheet

Data Sheet, V1.1, April 2003
HYE25L256160AC
256-Mbit Mobile-RAM
Extended Temperature Range
Memory Products
N e v e r
s t o p
t h i n k i n g .
HYE25L256160AC
Revision History:
2003-04-16
V1.1
Previous Version:
2001-11-23
V1.0
Page
Subjects (major changes since last version)
all
applied new data sheet template Din-A4
Page 13f
Temperature Compensated Self Refresh with On-Chip Temperature Sensor
Page 15
Table Operation Definition extended by two rows “Clock Suspend Entry” and “Clock Suspend
Exit”; Note 5 extended by “When this command is asserted during a burst cycle the device …”
Page 18
“Self Refresh” description improved
Page 19
“Simplified State Diagram” added
Page 20
relaxed Absolute Maximum Ratings (+0.5/–1.0 V instead of ±0.3 V relative to VDD/VSS)
Page 20
Note 4: relaxed over-/underswing delta to 2.0 V
Page 20ff
deleted VDD and VDDQ range above tables and partly replaced by note “(Recommended
Operating Conditions unless otherwise noted)“
Page 22
PC133 replaced by –7.5
Page 23f
table operating currents updated, symbols changed from ICC to IDD, value type “max.” added, IDD6
named “self refresh current”, IDD1 description (“Single bank access cycles”) updated
tCK defined by Note 3 or set to infinity; Note 4: “assumed” replaced by “used”
Page 41
revised timing diagram SPT03919-4
Page 54
TFBGA package outline moved to end , added “tolerance ±0.1mm for length and width”
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Edition 2003-04-16
Published by Infineon Technologies AG,
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© Infineon Technologies AG 2003.
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HYE25L256160AC
256-Mbit Mobile-RAM
Table of Contents
Page
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
3.3.1
3.3.2
3.4
3.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Compensated Self Refresh with On-Chip Temperature Sensor . . . . . . . . . . . . . . . .
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
11
12
12
12
13
13
13
15
19
4
4.1
4.2
4.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
21
23
5
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Data Sheet
3
V1.1, 2003-04-16
256-Mbit Mobile-RAM
Mobile-RAM
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
HYE25L256160AC
16 Mbits × 16 organisation
Fully synchronous to positive clock edge
Four internal banks for concurrent operation
Data mask (DM) for byte control with write and read data
Programmable CAS latency: 2 or 3
Programmable burst length: 1, 2, 4, 8, or full page
Programmable wrap sequence: sequential or interleaved
Random column address every clock cycle (1-N rule)
Deep power down mode
Extended mode register for Mobile-RAM features
Temperature compensated self refresh with on-die temperature sensor
Partial array self refresh
Power down and clock suspend mode
Automatic and controlled precharge command
Auto refresh mode (CBR)
8192 refresh cycles / 64 ms
Self-refresh with programmble refresh period
Programmable power reduction feature by partial array activation during self-refresh
VDDQ = 1.8V or 2.5 V or 3.3 V
VDD = 2.5 V or 3.3 V
P-TFBGA-54 package 9-by-6-ball array with 3 depopulated rows (12 x 8 mm2)
Operating temperature range: extended (–25 °C to +85 °C)
Table 1
Performance 1)
Part Number Speed Code
max. Clock Frequency
@CL3
min. Clock Period
@CL3
min. Access Time from Clock
@CL3
min. Clock Period
@CL2
min. Access Time from Clock
@CL2
fCK3
tCK3
tAC3
tCK2
tAC2
–7.5
–8
Unit
133
125
MHz
7.5
8.0
ns
6.0
6.0
ns
9.5
9.5
ns
6.0
6.0
ns
1) for VDDQ = 2.5 V; see Table 10 for VDDQ dependent performance
1.2
Description
The 256-Mbit Mobile-RAM is a new generation of low power, four bank synchronous DRAM organized as
4 banks x 4 Mbit x 16 with additional features for mobile applications. The synchronous Mobile-RAM achieves
high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes
the output data to a system clock.
The device adds new features to the industry standards set for synchronous DRAM products. Parts of the memory
array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps
which drastically reduces the self refresh current, depending on the case temperature of the components in the
system application. In addition a “Deep Power Down Mode” is available. Operating the four memory banks in an
Data Sheet
4
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Overview
interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
The Mobile-RAM is housed in a FBGA “chip-size” package. The Mobile-RAM is available in the extended (–25 °C
to +85 °C) temperature range.
Table 2
Ordering Information
Part Number1)
Function Code
Case Temperature Range
Package
HYE25L256160AC–7.5
PC133–333–522
extended (–25 °C to +85 °C)
P-TFBGA-54
HYE25L256160AC–8
PC100–222–620
1) HYB/E: designator for memory components for commercial/extended temperature range
25L: Mobile-RAM at VDD = 2.5 V
256: 256-Mbit density
160: Product variation x16
A: Die revision A
C: Package type FBGA
–7.5/8: speed grade - see Table 1
Data Sheet
5
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Pin Configuration
2
Pin Configuration
1
2
3
7
8
9
VSS
DQ15
VSSQ
A
VDDQ
DQ0
VDD
DQ14
DQ13
VDDQ
B
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
C
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
D
VSSQ
DQ6
DQ5
DQ8
NC
VSS
E
VDD
LDQM
DQ7
UDQM
CLK
CKE
F
CAS
RAS
WE
A12
A11
A9
G
BA0
BA1
CS
A8
A7
A6
H
A0
A1
A10/AP
VSS
A5
A4
J
A3
A2
VDD
< Top-view >
Figure 1
Data Sheet
Pin Configuration P-TFBGA-54 (16 Mb × 16)
6
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Pin Configuration
Table 3
Input/Output Signals
Pin Symbol Type
Polarity Function
F2
CLK
Input
Positive Clock
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge
of the clock.
F3
CKE
Input
Active
High
Clock Enable
CKE activates the CLK signal when high and deactivates the CLK signal when
low, thereby initiates either the Power Down mode, Suspend mode, or the Self
Refresh mode.
G9 CS
Input
Active
Low
Chip Select
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
F8
RAS
Input
F7
CAS
Active
Low
F9
WE
Command Inputs
Sampled at the rising edge of the clock, RAS, CAS, and WE (along with CS)
define the command to be executed by the SDRAM.
Input
Active
High
Bank Address Inputs
BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determine if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
Input
Active
High
Address Inputs
During a Bank Activate command cycle, A12 - A0 define the row address
(RA12 - RA0) when sampled at the rising clock edge.
During a Read or Write command cycle, A8-A0 define the column address
(CA8 - CA0) when sampled at the rising clock edge.
In addition to the column address, A10/AP is used to invoke autoprecharge
operation at the end of the burst read or write cycle. If AP is high, autoprecharge
is selected and BA1, BA0 defines the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA1 and
BA0 to control which bank(s) to precharge. If AP is high, all four banks will be
precharged regardless of the state of BA0 and BA1. If AP is low, then BA1 and
BA0 are used to define which bank to precharge.
G8 BA1
G7 BA0
G1 A12
G2 A11
H9 A10/AP
G3 A9
H1 A8
H2 A7
H3 A6
J2
A5
J3
A4
J7
A3
J8
A2
H8 A1
H7 A0
Data Sheet
7
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Pin Configuration
Table 3
Input/Output Signals (cont’d)
Pin Symbol Type
A2 DQ15
Polarity Function
Input/ Active
Output High
Data Input/Output
Data bus operates in the same manner as on conventional DRAMs.
Input
Active
High
Data Input/Output Mask
UDQM and LDQM are output disable signals during read mode and input mask
signals for write data. In Read mode, U/LDQM have a latency of two clock
cycles and control the output buffers like low active output enable signals. In
Write mode, U/LDQM have a latency of zero and operate as a word mask by
allowing input data to be written if it is low but blocks the write operation if the
respective DQM is high.
UDQM controls the upper byte and LDQM controls the lower byte.
E2 NC
–
–
Not Connected
No internal electrical connection is present.
A7, VDDQ
B3,
C7,
D3
Supply –
DQ Power Supply
A3 VSSQ
B7
C3
D7
Supply –
DQ Ground
A9 VDD
E4
J9
Supply –
Power Supply
A1 VSS
E3
J1
Supply –
Ground
B1 DQ14
B2 DQ13
C1 DQ12
C2 DQ11
D1 DQ10
D2 DQ9
E1 DQ8
E9 DQ7
D8 DQ6
D9 DQ5
C8 DQ4
C9 DQ3
B8 DQ2
B9 DQ1
A8 DQ0
F1
UDQM
E8 LDQM
Data Sheet
8
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Pin Configuration
A0 - A8, AP,
BA0, BA1
A0 - A12,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Row
Decoder
Row
Decoder
Bank 0
8192 x 512
x 16 Bit
Input Buffer
Memory
Array
Bank 1
8192 x 512
x 16 Bit
Output Buffer
Memory
Array
Bank 2
8192 x 512
x 16 Bit
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Refresh Counter
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Row Addresses
Column Decoder
Sense amplifier & I(O) Bus
Column Addresses
Memory
Array
Bank 3
8192 x 512
x 16 Bit
Control Logic &
Timing Generator
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
DQ0 - DQ15
SPB04124_256M
Figure 2
Block Diagram (16 Mbit × 16, 13 / 9 / 2 Addressing)
Note:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DQM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional
DQ signals.
Data Sheet
9
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
3
Functional Description
The 256-Mbit Mobile-RAM is a new generation of low power, four bank synchronous DRAM organized as
4 banks × 4 Mbit × 16 with additional features for mobile applications. The synchronous Mobile-RAM achieves
high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes
the output data to a system clock.
The device adds new features to the industry standards set for synchronous DRAM products. Parts of the memory
array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps
which drastically reduces the self refresh current, depending on the case temperature of the components in the
system application. In addition a “Deep Power Down Mode” is available. Operating the four memory banks in an
interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Prior to normal operation, the 256-Mbit Mobile-RAM must be initialized. The following sections provide detailed
information covering device initialization, register definition, command descriptions and device operation.
3.1
Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power
on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a
conventional DRAM, the 256-Mbit Mobile-RAM must be powered up and initialized in a predefined manner. VDD
must be applied before or at the same time as VDDQ to the specified voltage when the input signals are held in the
“NOP” or “DESELECT” state. The power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDDQ
supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 ms is required
followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all
banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register.
A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming
the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.Mode Register
Definition
3.2
Mode Register
The Mode Register designates the operation mode at the read or write cycle. This register is divided into four
fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access
sequence in a burst cycle (interleaved or sequential), and a CAS Latency Field to set the access time at clock
cycle, an The mode set operation must be done before any activate command after the initial power up. Any
content of the mode register can be altered by re-executing the mode set command. All banks must be in
precharged state and CKE must be high at least one clock before the mode set operation. After the mode register
is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock
activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the
previous table. BA0 and BA1 have to be set to “0” to enter the Mode Register.
Data Sheet
10
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
MR
Mode Register Definition
BA1
BA0
0
0
A12
(BA[1:0] = 00B)
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
MODE
CL
BT
BL
w
w
w
w
reg. addr
A0
Field
Bits
Type
Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command; see Chapter 3.2.1.
Note: All other bit combinations are RESERVED.
000
001
010
011
111
1
2
4
8
full page (sequential burst type only)
BT
3
w
Burst Type
See Table 4 for internal address sequence of low order address bits; see Chapter 3.2.2.
0
Sequential
1
Interleaved
CL
[6:4]
w
CAS Latency
Number of full clocks from read command to first data valid window; see Chapter 3.2.3.
Note: All other bit combinations are RESERVED.
010 2
011 3
MODE [12:7] w
Operating Mode
See Chapter 3.2.4.
Note: All other bit combinations are RESERVED.
000000
000100
3.2.1
Burst Read/Burst Write
Burst Read/Single Write
Burst Length
Read and write accesses to the 256-Mbit Mobile-RAM are burst oriented, with the burst length being
programmable. The burst length determines the maximum number of column locations that can be accessed for
a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by Ai-A1 when the burst length is set to two, by Ai-A2 when the burst
length is set to four and by Ai-A3 when the burst length is set to eight (where Ai is the most significant column
address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. The programmed burst length applies always to Read bursts and depending on
A9 in Operating Mode also on Write bursts.
Data Sheet
11
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
3.2.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 4.
Table 4
Burst
Length
Burst Definition
Starting Column Address
A2
A1
A0
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
2
4
8
Order of Accesses Within a Burst
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Note:
1. For a burst length of two, Ai-A1 selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, Ai-A2 selects the four-data-element block; A1-A0 selects the first access within the
block.
3. For a burst length of eight, Ai-A3 selects the eight-data- element block; A2-A0 selects the first access within
the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
3.2.3
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and
the availability of the first burst of output data. The latency can be programmed 2 and 3 clocks.
If a Read command is registered at rising clock edge n, and the latency is m clocks, the data is available nominally
coincident with rising clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
3.2.4
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A12-A7 set to zero,
and bits A6-A0 set to the desired values. Burst Length for Write bursts is fixed to one by issuing a Mode Register
Set command with bits A12-A10 and A8-A7 each set to zero, bit A9 set to one, and bits A0-A6 set to the desired
values.
All other combinations of values for A12-A7 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
Data Sheet
12
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
3.3
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register. These additional
functions are unique to Mobile RAMs and includes a refresh period field (TCSR) for Temperature Compensated
Self Rrefresh and a Partial Array Self Refresh field (PASR).
The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 1)
and retains the stored information until it is programmed again or the device looses power. The Extended mode
Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating
any subsequent operation. Violating either these requirements result in unspecified operation. Unused bit A12 to
A5 have to be programmed to “0”.
3.3.1
Partial Array Self Refresh
The PASR field is a power saving feature specific to Mobile-RAMs and is used to specify whether only one quarter
or half of bank 0, one bank (bank 0), two banks (banks 0 + 1) or all four banks (default) of the SDRAM array are
enabled for Self Refresh. Disabled banks will not be refreshed in Self Refresh mode and written data will get lost
after a period defined by tREF.
3.3.2
Temperature Compensated Self Refresh with On-Chip Temperature Sensor
DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain
the stored information. This refresh requirment heavily depends on the die temperatur: high temperature
corresponds to short refresh period, and low temperature to long refresh period.
The Mobile-RAM is equipped with an on-chip temperature sensor which continuously monitors the current die
temperature and adjusts the refresh period in self refresh mode accordingly. By default the on-chip temperature
sensor is enabled (TCSR = 00, see Table "EMR" on Page 14); the other three TCSR settings use defined
temperature values to adjust the self refresh period to with the on-chip temperature sensor being disabled.
Data Sheet
13
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
EMR
Extended Mode Register Definition
BA1
BA0
1
0
A12
A11
A10
(BA[1:0] = 10B)
A9
reg. addr
A8
A7
A6
A5
A4
A3
A2
A1
MODE
TCSR
PASR
w
w
w
A0
Field
Bits
Type
Description1)
PASR
[2:0]
w
Partial Array Self Refresh
See Chapter 3.3.1
000 banks to be self refreshed: all 4 of 4
001 banks to be self refreshed: 2 of 4, BA[1:0] = 00B or 01B
010 banks to be self refreshed: 1 of 4, BA[1:0] = 00B
101 banks to be self refreshed: 0.5 of 4, BA[1:0] = 00B & RA12 = 0B
110 banks to be self refreshed: 0.25 of 4, BA[1:0] = 00B & RA[12:11] = 00B
TCSR
[4:3]
w
Temperature Compensated Self Refresh
See Chapter 3.3.2.
00 on-chip temperature sensor enabled
01 Maximum case temperature: 45°C, on-chip temperature sensor disabled
10 Maximum case temperature: 15°C, on-chip temperature sensor disabled
11 Maximum case temperature: 85°C, on-chip temperature sensor disabled
MODE
[12:5]
w
Operating Mode
00h Normal operation
1) All other bit combinations are RESERVED.
Data Sheet
14
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
3.4
Commands
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive
edge of the clock. The following list shows the truth table for the operation commands.
Table 5
Operation Definition1)
Operation
Device
State
CKE CKE DQM BA1 AP= Addr CS RAS CAS WE
n-12) n2)
BA0 A10
Bank Active
Idle3)
H
X
X
V
V
V
L
L
H
H
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
Write
Active3)
H
X
X
V
L
V
L
H
L
L
Write with Autoprecharge
Active3)
H
X
X
V
H
V
L
H
L
L
Active
3)
H
X
X
V
L
V
L
H
L
H
Read with Autoprecharge
Active
3)
H
X
X
V
H
V
L
H
L
H
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
H
X
X
X
X
X
L
H
H
L
Read
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
Auto Refresh
Idle
H
H
X
X
X
X
L
L
L
H
Self Refresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Self Refresh Exit
Idle
(Self Refresh)
H
X
X
X
L
H
X
X
X
X
L
H
H
X
H
L
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
H
X
X
X
H
L
X
X
X
X
Clock Suspend Entry
Active
Clock Suspend Exit
Active
4)
Power Down Entry
Idle
(Precharge or active standby) Active4)
Power Down Exit
L
H
H
H
H
X
X
X
X
L
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
H
L
X
X
X
X
X
X
X
X
Any
(Power Down)
L
H
X
X
X
Data Write/Output Enable
Active
H
X
L
X
Data Write/Output Disable
Active
H
X
H
Deep Power Down Entry
Idle
H
L
L
H
Deep Power Down Exit
5)
Deep Power Down
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level.
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are
provided.
3) This is the state of the banks designated by BA0, BA1 signals.
4) Power Down Mode can not be entered during a burst cycle. When this command is asserted during a burst
cycle the device enters Clock Suspend Mode.
5) After Deep Power Down mode exit a full new initialisation of the memory device is mandatory.
Data Sheet
15
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
Deselect
The Deselect function prevents new commands from being executed by the 256-Mbit Mobile-RAM. Operations
already in progress are not affected.
No Operation (NOP)
The No Operation (NOP) command is used to perform a NOP to a 256-Mbit Mobile-RAM. This prevents unwanted
commands from being registered during idle or wait states. Operations already in progress are not affected.
Mode Register Set
The mode registers are loaded via inputs A12-A0, BA1 and BA0. See mode register descriptions in Chapter 3.2.
The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A
subsequent executable command cannot be issued until tMRD is met.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. This is called
the start of a RAS cycle and occures when RAS is low and both CAS and WE are high at the positive edge of the
clock. The value on the BA1 and BA0 inputs selects the bank, and the address provided on inputs A12-A0 selects
the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge)
is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and
completed before opening a different row in the same bank.
Read and Write
A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from
the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations
are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the burst length programmed at the
mode set operation, which is one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length
and serial data accesses are done within this boundary. The first column address to be accessed is supplied at
the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and
its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest
of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O
organisation and column addressing. Full page burst operation does not self terminate once the burst length has
been reached. In other words, unlike burst length of 2, 4 and 8, full page burst continues until it is terminated using
another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column address are
possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the
number of random column accesses. A new burst access can be done even before the previous burst ends. The
interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining
addresses are overridden by the new address with the full burst length. An interrupt which accompanies an
operation change from a read to a write is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With
the programmed burst length, alternate access and precharge operations on two or more banks can realize fast
serial data access modes among many different pages. Once two or more banks are activated, column to column
interleave operation can be performed between different pages. When the partial array activation is set, data will
get lost when self-refresh is used in all non activated banks.
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA1 and BA0
inputs selects the bank, and the address provided on inputs A9-A0 for x16 selects the starting column location.
The value on input A10/AP determines whether or not Auto Precharge is used. If Auto Precharge is selected, the
row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains
open for subsequent accesses.
Data Sheet
16
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA1 and BA0
inputs selects the bank, and the address provided on inputs A9-A0 for x16 selects the starting column location.
The value on input A10/AP determines whether or not Auto Precharge is used. If Auto Precharge is selected, the
row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains
open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM
input logic level appearing coincident with the data. If a given DQM signal is registered low, the corresponding data
is written to memory; if the DQM signal is registered high, the corresponding data inputs are ignored, and a Write
is not executed to that byte/column location.
Precharge
The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all
banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge
command is issued. When RAS and WE are low and CAS is high at a clock edge, it triggers the precharge
operation. Input A10 determines whether one or all banks are to be precharged, and in the case where only one
bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care” (see
Table 6). Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write
commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that
bank, or if the previously open row is already in the process of precharging.
The precharge command can be imposed one clock before the last data out for CAS latency = 2 and two clocks
before the last data out for CAS latency = 3. Writes require a time delay tWR from the last data out to apply the
precharge command.
Table 6
Bank Selection by Address Bits with Precharge
A10
BA0
BA1
0
0
0
Bank 0
0
0
1
Bank 1
0
1
0
Bank 2
0
1
1
Bank 3
1
x
x
all Banks
Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but
without requiring an explicit command. This is accomplished by using A10/AP to enable Auto Precharge in
conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read
or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is
nonpersistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge
ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit Precharge
command was issued at the earliest possible time. The 256-Mbit Mobile-RAM automatically enters the precharge
operation after tWR (Write recovery time) following the last data in.
Burst Terminate
Once a burst read or write operation has been initiated, there are several methods used to terminate the burst
operation prematurely. These methods include using another Read or Write Command to interrupt an existing
burst operation, using a Precharge Command to interrupt a burst cycle and close the active bank, or using the
Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write
Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command
care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions
making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be
ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the
memory.
Data Sheet
17
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
Auto Refresh
Auto Refresh is used during normal operation of the 256-Mbit Mobile-RAM and is analogous to CAS Before RAS
(CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh
is required. All banks must be precharged before applying any refresh mode. An on-chip address counter
increments the word and the bank addresses. This makes the address bits “Don’t Care” during an Auto Refresh
command.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a
clock edge. The mode restores word line after the refresh and no external precharge command is necessary. A
minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to
any access command after the automatic refresh operation.
In Auto-Refresh mode all banks are refreshed, independendly of the fact that the partial array self-refresh has been
set or not.
Self Refresh
The chip has an on-chip timer that is used when the Self Refresh mode is entered. The self-refresh command is
asserted with RAS, CAS, and CKE low and WE high at a clock edge. All external control signals including the clock
are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit
command, at least one tRC delay is required prior to any access command. The use of self refresh mode introduces
the possibility that an iternally timed event can be missed when CKE is raised for exit from self refresh mode. Upon
exit from self refresh an extra auto refresh command is recommended.
Low Power SDRAMs have the possibility to program the refresh period of the on-chip timer with the use of an
appropriate extended MRS command, depending on the maximum operation case temperature in the application.
In partial array self refresh mode only the selected banks will be refreshed. Data written to the non activated banks
will get lost after a period defined by tref.
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high” at a clock edge,
data outputs are disabled and become high impedance after two clock periods (DQM Data Disable Latency tDQZ).
It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is
prohibited (DQM Write Mask Latency tDQW = zero clocks).
Suspend Mode
During normal access, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and
extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend
Latency tCSL).
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks must be precharged
before the Mobile-RAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE
low, all receiver circuits except for CLK and CKE are gated off. The Power Down mode does not perform any
refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (tREF)
of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is required for power down
mode entry and exit.
Deep Power Down Mode
The Deep Power Down Mode is an unique function on Mobile RAMs with very low standby currents.
All internal voltage generators inside the Mobile RAMs are stopped and all memory data is lost in this mode. To
enter the Deep Power Down mode all banks must be precharged.
Data Sheet
18
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
3.5
Simplified State Diagram
Power
applied
Power
On
Deep
Power
Down
DPDSX
Precharge
All
PREALL
Self
Refresh
DPDS
REFSX
REFS
Mode
Register
Set
MRS
Auto
Refresh
REFA
Idle
CKEL
CKEH
Active
Power
Down
Precharge
Power
Down
ACT
CKEH
CKEL
Row
Active
T
BS
W
R
RE
A
WRITEA
Clock
Suspend
WRITE
CKEL
CKEH
WRITE
WRITEA
Clock
Suspend
WRITEA
CKEL
CKEH
WRITE A
PRE
BS
T
E
IT
READA
WRITE
READ
WRITEA
PRE
D
PRE
CKEH
Clock
Suspend
READ
READA
READ
A
PRE
CKEL
READ
READ A
CKEL
CKEH
Clock
Suspend
READA
Precharge
Automatic Sequence
Command Sequence
PREALL = Precharge All Banks
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
DPDS = Enter Deep Power Down
DPDSX = Exit Deep Power Down
Figure 3
Data Sheet
CKEL = Enter Power Down
CKEH = Exit Power Down
READ = Read w/o Auto Precharge
READA = Read with Auto Precharge
WRITE = Write w/o Auto Precharge
WRITEA = Write with Auto Precharge
ACT = Active
PRE = Precharge
BST = Burst Terminate
MRS = Mode Register Set
Simplified State Diagram
19
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Electrical Characteristics
4
Electrical Characteristics
4.1
Operating Conditions
Table 7
Absolute Maximum Ratings
Parameter
Symbol
Voltage on I/O pins relative to VSS
VIN, VOUT
VIN, VOUT
VDD
VDDQ
TCASE
TSTG
PD
IOUT
Voltage on I/O pins relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating Case Temperature (extended)
Storage Temperature (Plastic)
Power Dissipation
Short Circuit Output Current
Values
Unit
min.
typ.
max.
Note/
Test Condition
–1.0
—
VDD + 0.5 V
—
–1.0
—
+4.6
V
—
–1.0
—
+4.6
V
—
–1.0
—
+4.6
V
—
–25
—
+85
°C
—
–55
—
+150
°C
—
—
—
0.7
W
—
—
50
—
mA
—
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Table 8
Recommended Operating Conditions and DC Characteristics1)
Parameter
Symbol
Values
Unit Note/ Test Condition
min.
max.
+2.3
+3.6
V
—
+1.65
+3.6
V
2)
0
0
V
—
0
0
V
—
0.8 x VDDQ
VDDQ + 0.3
V
3)4)
–0.3
+0.3
V
3)4)
VDDQ – 0.2 —
V
IOH = –0.1 mA
—
+0.2
V
IOH = +0.1 mA
Input Leakage Current
VDD
VDDQ
VSS
VSSQ
VIH
VIL
VOH
VOL
IIL
–5
+5
µA
Any input 0 V ≤VIN ≤VDD;
all other pins not under test VIN = 0 V
Output Leakage Current
IOZ
–5
+5
µA
DQ is disabled; 0 V ≤VOUT ≤VDDQ
Supply Voltage
I/O Supply Voltage
Supply Voltage
I/O Supply Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Output High (Logic 1) Voltage
Output Low (Logic 0) Voltage
1) –25 ° C ≤TCASE ≤+85 ° C
2) VDDQ < VDD + 0.3 V
3) All voltages referenced to VSS
4)
VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4 ns.
VIL may undershoot to – 2.0 V for pulse width < 4 ns.
Pulse width measured at 50% points with amplitude measured peak to DC reference
Data Sheet
20
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Electrical Characteristics
Table 9
Input and Output Capacitances
Parameter
Symbol
CI1
CI2
CIO
Input Capacitance: CLK
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQ
Values
Unit
Note/
Test Condition
min.
typ.
max.
–
–
3.5
pF
1)
–
–
3.8
pF
1)
4.0
–
5.0
pF
1)
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 1 MHz,
TCASE = 25 ° C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
4.2
Timing Characteristics
Table 10
AC Timing Characteristics1)2)
Parameter
Symbol
–8
–7.5
Unit Note/ Test Condition
min.
max.
min.
max.
–
7.5
–
7.5
ns
–
6
–
6
ns
–
6
–
5.4
ns
–
7.5
–
7.5
ns
–
6
–
6
ns
VDDQ < 2.3 V 3)4)5)8)
VDDQ ≥ 2.3 V 3)4)5)8)
VDDQ ≥ 3.0 V 3)4)5)8)
VDDQ < 2.3 V 3)4)5)8)
VDDQ ≥ 2.3 V 3)4)5)8)
3
–
2.5
–
ns
–
3
–
2.5
–
ns
–
8
–
7.5
–
ns
8
–
8
–
ns
VDDQ ≥ 2.3 V 3)
VDDQ < 2.3 V 3)
9.5
–
9.5
–
ns
–
125
–
133
MHz VDDQ ≥ 2.3 V 3)
–
125
–
125
MHz VDDQ < 2.3 V 3)
fCK2
tT
–
105
–
105
MHz
3)
0.5
1.5
0.3
1.2
ns
–
tIS
tIH
tCKS
tCKH
tRSC
tSB
2
–
1.5
–
ns
6)
1
–
0.8
–
ns
6)
2
–
1.5
–
ns
6)
1
–
0.8
–
ns
6)
2
–
2
–
tCK
–
0
8
0
7.5
ns
–
tRCD
tRP
tRAS
tRC
tRRD
19
–
19
–
ns
7)
19
–
19
–
ns
7)
48
100000 45
100000 ns
7)
70
–
67
–
ns
7)
16
–
15
–
ns
7)
Clock
DQ output access time from CLK
tAC3
tAC2
CK high-level width
CK low-level width
Clock cycle time
Clock frequency
Transition time
tCH
tCL
tCK3
tCK2
fCK3
3)
Setup and Hold Times
Input setup time
Input hold time
CKE setup time
CKE hold time
Mode register setup time
Power down moder entry time
Common Parameters
Active to Read or Write delay
Precharge command period
Active to Precharge command
Active bank A to Active bank A period
Active bank A to Active bank B delay
Data Sheet
21
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Electrical Characteristics
Table 10
AC Timing Characteristics1)2) (cont’d)
Parameter
Symbol
CAS to CAS command delay
–8
–7.5
Unit Note/ Test Condition
min.
max.
min.
max.
tCCD
1
–
1
–
tCK
–
tREF
tSREX
–
64
–
64
ms
–
1
–
1
–
tCK
–
3
–
3
–
ns
4)7)8)
0
–
1
–
ns
–
3
8
3
7
ns
–
–
2
–
2
tCK
–
14
–
14
–
ns
9)
0
–
0
–
tCK
–
Refresh Cycle
Refresh period
Self refresh exit time
Read Cycle
tOH
Data output from high to low impedance tLZ
Data output from low to high impedance tHZ
DQM data output disable latency
tDQZ
Data output hold time
Write Cycle
Write recovery time
DQM write data mask latency
tWR
tDQW
1) –25 ° C ≤TCASE ≤+85 ° C; recommended operating conditions unless otherwise noted
2) For proper power-up see the operation section of this data sheet.
3) Symbol index 2 and 3 refer to CL = 2 and CL = 3.
4) AC timing tests are referenced to the 0.9 V crossover point. The transition time is measured between VIH and VIL. All AC
measurements assume tT = 1 ns with the AC output load circuit (details will be defined later). Specified tAC and tOH
parameters are measured with a 30 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
(see Figure 4).
5) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.
6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
8) Access time from clock tAC is 4.6 ns for –7.5 components with no termination and 0 pF load,
Data out hold time tOH is 1.8 ns for –7.5 components with no termination and 0 pF load.
9) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when the memory
operation frequency is equal or less than 72MHz. For all memory operation frequencies higher than 72MHz two clock
cycles for tWR are mandatory. INFINEON recommends to use two clock cylces for the write recovery time in all applications.
I/O
30 pF
Figure 4
Data Sheet
Measurement Conditions for tAC and tOH
22
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Electrical Characteristics
4.3
Current Specification
Table 11
IDD Specification and Conditions1)2)
Parameter
Symbol
–8
–7.5
Unit Note/ Test Condition
typ. max. typ. max.
Operating current
Single bank access cycles
IDD1
60
65
mA
tRC = tRC,MIN 3)
Precharge standby current
Power down mode
IDD2P
0.5
0.6
mA
CS = VIH,MIN,
CKE ≤VIL,MAX 3)
Precharge standby current
Non power down mode
IDD2N
18
20
mA
CS = VIH,MIN,
CKE ≥ VIH,MIN 3)
Non operating current
Active state of 1 upto 4 banks, power down
IDD3P
3.5
3.5
mA
CS = VIH,MIN,
CKE ≤VIL,MAX 3)
Non operating current
IDD3N
Active state of 1 upto 4 banks, non power down
20
25
mA
CS = VIH,MIN,
CKE ≥ VIH,MIN 3)
3)4)
Burst operating current
Read command cycling
IDD4
60
80
mA
Auto refresh current
Auto refresh command cycling
IDD5
140
155
mA
tRC = tRC,MIN
Self refresh current
IDD6
see Table 12
µA
tCK =infinity,
CKE = 0.2 V
Deep power down mode current
IDD7
5
5
µA
1) –25 ° C ≤TCASE ≤+85 ° C; recommended operating conditions unless otherwise noted
2) For proper power-up see the operation section of this data sheet.
3) These parameters depend on the frequency. These values are measured at 133MHz for –7.5 and at 100MHz for –8 parts.
Input signals are changed once during tCK. If the devices are operating at a frequency less than the maximum operation
frequency, these current values are reduced.
4) These parameters are measured with continuous data stream during read access and all DQs toggling. CL = 3 and BL = 4
is used and the VDDQ current is excluded.
Data Sheet
23
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Electrical Characteristics
Table 12
IDD6 Programmable Self Refresh Current1)2)
Parameter
Symbol –8, –7.5 Unit TCASE
max.
Self refresh current
Self refresh mode,
full array activations = all banks
IDD6
Self refresh current
IDD6
Self refresh mode,
half array activations = bank 0 + 1
Self refresh current
IDD6
Self refresh mode,
quarter array activations = bank 0
TCSR
Note/ Test Condition
3)
t.b.d.
µA
max. 15°C
250
µA
max. 45°C
475
µA
max. 70°C
725
µA
max. 85°C
t.b.d.
µA
max. 15°C
150
µA
max. 45°C
250
µA
max. 70°C
450
µA
max. 85°C
t.b.d.
µA
max. 15°C
100
µA
max. 45°C
150
µA
max. 70°C
275
µA
max. 85°C
tCK =infinity,
CKE = 0.2 V 4)
tCK =infinity,
CKE = 0.2 V 4)
tCK =infinity,
CKE = 0.2 V 4)
1) Recommended operating conditions unless otherwise noted
2) For proper power-up see the operation section of this data sheet.
3) Extended Mode Register A4-A3, see “Temperature Compensated Self Refresh with On-Chip Temperature Sensor”
on Page 13
4) Target values to be verified on final product and may change.
Data Sheet
24
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
5
Timing Diagrams
Figure 5 Bank Activate Command Cycle
Figure 6 Burst Read Operation
Figure 7 Read Interrupted by a Read
Read to Write Interval
– Figure 8 Read to Write Interval
– Figure 9 Minimum Read to Write Interval
– Figure 10 Non-Minimum Read to Write Interval
Figure 11 Burst Write Operation
Write and Read Interrupt
– Figure 12 Write Interrupted by a Write
– Figure 13 Write Interrupted by Read
Burst Write & Read with Auto-Precharge
– Figure 14 Burst Write with Auto-Precharge
– Figure 15 Burst Read with Auto-Precharge
AC- Parameters
– Figure 16 AC Parameters for a Write Timing
– Figure 17 AC Parameters for a Read Timing
Figure 18 Mode Register Set
Figure 19 Power on Sequence and Auto Refresh (CBR)
Clock Suspension (using CKE)
–
–
–
–
Figure 20 Clock Suspension During Burst Read CAS Latency = 2
Figure 21 Clock Suspension During Burst Read CAS Latency = 3
Figure 22 Clock Suspension During Burst Write CAS Latency = 2
Figure 23 Clock Suspension During Burst Write CAS Latency = 3
Figure 24 Power Down Mode and Clock Suspend
Figure 25 Self Refresh (Entry and Exit)
Figure 26 Auto Refresh (CBR)
Random Column Read ( Page within same Bank)
– Figure 27 CAS Latency = 2
– Figure 28 CAS Latency = 3
Random Column Write ( Page within same Bank)
– Figure 29 CAS Latency = 2
– Figure 30 CAS Latency = 3
Random Row Read (Interleaving Banks) with Precharge
– Figure 31 CAS Latency = 2
– Figure 32 CAS Latency = 3
Random Row Write (Interleaving Banks) with Precharge
– Figure 33 CAS Latency = 2
– Figure 34 CAS Latency = 3
Precharge Termination of a Burst
– Figure 35 CAS Latency = 2
Deep Power Down Mode
– Figure 36 Deep Power Down Mode Entry
– Figure 37 Deep Power Down Mode Exit
Data Sheet
25
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
(CAS latency = 3)
T0
T1
T
T
T
T
T
CLK
Bank B
Row Addr.
Address
Bank B
Col. Addr.
t RCD
Command
Bank B
Activate
NOP
Bank B
Row Addr.
Bank A
Row Addr.
t RRD
NOP
Write B
with Auto
Precharge
Bank A
Activate
NOP
Bank B
Activate
t RC
"H" or "L"
Figure 5
SPT03784
Bank Activate Command Cycle
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CLK
Command
CAS
latency = 2
t CK2 , DQ’s
CAS
latency = 3
t CK3 , DQ’s
Figure 6
Data Sheet
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
SPT03712
Burst Read Operation
26
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
Read A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CLK
Command
CAS
latency = 2
t CK2 , DQ’s
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
CAS
latency = 3
t CK3 , DQ’s
Figure 7
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
SPT03713
Read Interrupted by a Read
Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Minimum delay between the Read and Write
Commands = 4 + 1 = 5 cycles
Write latency t DQW of DQMx
DQMx
t DQZ
Command
NOP
Read A
DQ’s
NOP
NOP
NOP
DOUT A0
NOP
Write B
NOP
NOP
DIN B0
DIN B1
DIN B2
Must be Hi-Z before
the Write Command
"H" or "L"
Figure 8
Data Sheet
SPT03787
Read to Write Interval
27
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
(Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
Write A
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
CLK
t DQW
DQM
t DQZ
1 Clk Interval
Command
NOP
NOP
Bank A
Activate
NOP
Read A
Must be Hi-Z before
the Write Command
CAS
latency = 2
t CK2 , DQ’s
"H" or "L"
Figure 9
Data Sheet
SPT03939
Minimum Read to Write Interval
28
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
CLK
t DQW
DQM
t DQZ
Command
NOP
Read A
NOP
NOP
Read A
NOP
Write B
Must be Hi-Z before
the Write Command
CAS
latency = 2
t CK2 , DQ’s
DOUT A0 DOUT A1
DIN B0
DIN B1
DIN B2
CAS
latency = 3
t CK3 , DQ’s
DOUT A0
DIN B0
DIN B1
DIN B2
"H" or "L"
Figure 10
SPT03940
Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Write A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
don’t care
CLK
Command
DQ’s
The first data element and the Write
are registered on the same clock edge.
Figure 11
Data Sheet
Extra data is ignored after
termination of a Burst.
SPT03790
Burst Write Operation
29
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Write and Read Interrupt
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Write A
Write B
NOP
NOP
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
CLK
Command
1 Clk Interval
DQ’s
DIN A0
DIN B0
SPT03791
Figure 12
Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Write A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
CLK
Command
CAS
latency = 2
t CK2 , DQ’s
DIN A0
don’t care
CAS
latency = 3
t CK3 , DQ’s
DIN A0
don’t care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
don’t care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ’s
at least one clock cycle before the Read data
appears on the outputs to avoid data contention.
Input data for the Write is ignored.
SPT03719
Figure 13
Data Sheet
Write Interrupted by a Read
30
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Burst Write and Read with Auto Precharge
(Burst Length = 2, CAS latency = 2, 3 )
T0
T1
B ank A
A c tive
NOP
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
T8
C LK
CAS Latency = 2:
C o m m a nd
W rite A
Auto Precharge
tWR
D IN A 0
D Q 's
NOP
NOP
NOP
t RP
*
D IN A 1
A ctiva te
CAS Latency = 3:
Bank A
A ctive
C om m and
NOP
NOP
W rite A
NOP
Auto Precharge
NOP
NOP
tWR
D IN A 0
D Q 's
tRP
*
D IN A 1
*
A ctiva te
B e g in A u to P re ch a rg e
B an k c a n b e re ac tiva te d a fte r trp
S PT03909_2
Figure 14
Burst Write with Auto-Precharge
(B u rst L e n g th = 4 , C A S la te n cy = 2 , 3 )
T0
T1
T2
T3
T4
T5
T6
T7
T8
R ead A
w ith A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
C LK
C om m and
CAS
la te n cy = 2
D Q 's
CAS
la te n cy = 3
D Q 's
*
DOUT A0
DOUT A1
DOUT A2
tRP
DOUT A3
*
DOUT A0
DOUT A1
DOUT A2
t RP
DOUT A3
* B e g in A u to P re cha rg e
B a nk ca n b e re a ctivate d a fte r trp
Figure 15
Data Sheet
SP T03721_2
Burst Read with Auto-Precharge
31
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
AC Parameters
B urst Len gth = 4, C A S La tenc y = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T 10
T 11 T 12 T 13 T 14 T 15 T 1 6 T 1 7 T 1 8 T 1 9 T 20
T 21 T 22
CLK
t CH
t CK2
t CL
CKE
t CKS
t CH
t CKH
B e gin A u to
P rech arg e
B a nk B
B e gin A u to
P recha rg e
B a nk A
t CS
CS
RAS
CAS
WE
BS
t AH
AP
RBx
RAx
RAy
RAz
RBy
RAz
RBy
t AS
A dd r.
RAx
CAx
RAy
CBx
RBx
RAy
DQM
t WR
t RCD
t DS
t RP
t DH
t RC
H i-Z
A x0 A x1 A x2 A x3 B x0 B x1
DQ
A ctiv ate
C om m an d
B ank A
A ctiva te
C om m an d
B ank B
W rite w ith
A uto P rec harge
C o m m a nd
B a nk A
Figure 16
Data Sheet
B x2 B x3
t RP
t RRD
A y0 A y1 A y 2 A y3
A ctiva te
W rite
C o m m an d C om m an d
B an k A
B an k A
W rite w ith
A u to P re cha rge
C o m m an d
B ank B
t WR
P rech arge A ctivate
A ctivate
C om m an d C o m m and C om m a nd
B ank A
B a nk A
B an k B
SPT03910_2
AC Parameters for a Write Timing
32
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Burst Length = 2, CAS Latency = 2
T0
T1
T2
T3
T4
T6
T5
T7
T8
T9
T10
T11
T12
T13
CLK
t CH
t CK2
t CL
CKE
t CKH
t CS
Begin Auto
Precharge
Bank B
t CKS
t CH
CS
RAS
CAS
WE
BS
t AH
RAx
AP
RBx
RAy
t AS
RAx
Addr.
CAx
RBx
RBx
RAy
t RRD
t RAS
t RC
DQM
t AC2
t LZ
t OH
t RCD
DQ
Hi-Z
Data Sheet
Read
Command
Bank A
t RP
t AC2
t HZ
Ax0
Activate
Command
Bank A
Figure 17
t HZ
Activate
Command
Bank B
Ax1
Read with
Auto Precharge
Command
Bank B
Bx0
Precharge
Command
Bank A
Bx1
Activate
Command
Bank A
S P T 0 39 11_ 2
AC Parameters for a Read Timing
33
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
C A S L aten c y = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T 10 T 1 1 T 1 2 T 13 T 14 T 1 5 T 1 6 T 1 7 T 18 T 19 T 2 0
T 21 T 22
CLK
CKE
t RSC
CS
RAS
CAS
WE
BS
AP
A d dres s K ey
Addr.
P re c ha rg e
C o m m an d
A ll B an k s
Any
C om m an d
M o d e R eg is te r
S et C om m an d
Figure 18
Data Sheet
SPT03912_2
Mode Register Set
34
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
T2
T3
T4
CKE
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
~
~
~
~
~
~
CLK
T1
~
~
T0
2 Clock min.
Minimum of 8 Refresh Cycles are required
~
~
~
~
High Level
is required
~
~
~ ~
~
~
AP
~
~ ~
~
BS
~
~
~
~ ~
~
WE
~ ~
~
~
~
~ ~
~
CAS
~
~ ~
~
~
~
~ ~
RAS
~
~ ~
~
~
~
~
~
CS
~ ~
~
~
~
~ ~
~
Addr.
~
~
~
~
Address Key
DQM
8th Auto Refresh
Command
Precharge
Command
All Banks
Inputs must be
stable for 200 µs
Figure 19
Data Sheet
t RC
~
~
DQ
~
~
t RP
Hi-Z
1st Auto Refresh
Command
Mode Register
Set Command
Any
Command
SPT03913
Power on Sequence and Auto Refresh (CBR)
35
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Clock Suspension (Using CKE)
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
RAx
CAx
DQM
t CSL
t CSL
DQ
Hi-Z
Ax0
Activate
Read
Command Command
Bank A
Bank A
Figure 20
Data Sheet
t HZ
t CSL
Ax1
Ax2
Ax3
Clock
Suspend
1 Cycle
Clock
Suspend
2 Cycles
Clock
Suspend
3 Cycles
SPT03914
Clock Suspension During Burst Read CAS Latency = 2
36
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
RAx
CAx
t CSL
t CSL
DQM
t CSL
t HZ
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Figure 21
Data Sheet
Read
Command
Bank A
Ax1
Ax2
Ax3
Clock
Suspend
1 Cycle
Clock
Suspend
2 Cycles
Clock
Suspend
3 Cycles
SPT03915
Clock Suspension During Burst Read CAS Latency = 3
37
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
RAx
CAx
DQM
DQ
Hi-Z
Activate
Command
Bank A
DAx0
DAx1
Clock
Suspend
1 Cycle
DAx2
Clock
Suspend
2 Cycles
DAx3
Clock
Suspend
3 Cycles
Write
Command
Bank A
Figure 22
Data Sheet
SPT03916
Clock Suspension During Burst Write CAS Latency = 2
38
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BA
A8/AP
RAx
Addr.
RAx
CAx
DQMx
DQ
Hi-Z
DAx0
Activate
Command
Bank A
DAx1
Clock
Suspend
1 Cycle
DAx2
Clock
Suspend
2 Cycles
DAx3
Clock
Suspend
3 Cycles
Write
Command
Bank A
Figure 23
Data Sheet
SPT03917
Clock Suspension During Burst Write CAS Latency = 3
39
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CKS
t CK2
t CKS
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
RAx
CAx
DQM
t HZ
DQ
Hi-Z
Ax0 Ax1
Activate
Command
Bank A
Active
Standby
Clock Suspend
Mode Entry
Read
Command
Bank A
Ax2
Clock Mask
End
Clock Mask
Start
Clock Suspend
Mode Exit
Ax3
Precharge
Command
Bank A
Precharge
Standby
Power Down
Mode Entry
Any
Command
Power Down
Mode Exit
SPT03918
Figure 24
Data Sheet
Power Down Mode and Clock Suspend
40
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12 T13 T14 T15 T16 T17 T18 T19 T20
T21 T22
~
~
CLK
~
~
CKE
t CKS
~
~
t CKS
~
~
~
~
CS
~
~
~
~
RAS
~
~
CAS
~
~
~
~
~
~
WE
~
~
BS
~ ~
~
~
AP
~
~
~
~
~
~
Addr.
tSREX
t RC
DQM
~
~
Hi-Z
~
~
DQ
All Banks
must be idle
Begin Self Refresh
Exit Command
Self Refresh
Entry
Self Refresh Exit
Command issued
(async.)
Figure 25
Data Sheet
Any
Command
SPT03919-4
Self Refresh (Entry and Exit)
41
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
B urst L e n g th = 4 , C A S L a ten c y = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T 11 T 1 2 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 2 1 T 2 2
CLK
t CK2
CKE
CS
RAS
CAS
WE
BS
AP
RAx
A dd r.
RAx
t RC
t RP
CAx
t RC
(M in im u m Interval)
DQM
H i-Z
A x0 A x1 A x2 A x3
DQ
P re cha rge A u to R e fre sh
C o m m an d C om m an d
A ll B a nks
A u to R e fre sh
C om m an d
A ctiva te
C o m m an d
B a nk A
R ea d
C o m m a nd
B an k A
SPT03920_2
Figure 26
Data Sheet
Auto Refresh (CBR)
42
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Random Column Read (Page within same Bank)
Burst Length = 4, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BS
AP
RAw
Addr.
RAw
RAz
CAw
CAx
CAy
RAz
CAz
DQM
DQ
Hi Z
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
Activate
Command
Bank A
Figure 27
Data Sheet
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Az0 Az1 Az2 Az3
Read
Command
Bank A
SPT03921
CAS Latency = 2
43
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BS
AP
RAw
Addr.
RAw
RAz
CAw
CAx
CAy
RAz
CAz
DQM
DQ
Hi Z
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
Activate
Command
Bank A
Figure 28
Data Sheet
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A SPT03922
CAS Latency = 3
44
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Random Column write (Page within same Bank)
B u rst Le n gth = 4, C A S La ten cy = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T 10
T 1 1 T 1 2 T 1 3 T 1 4 T 1 5 T 16 T 17 T 18 T 19 T 2 0
T21 T22
CLK
t CK2
CKE
CS
RAS
CAS
WE
BS
AP
RBw
A dd r.
RBw
RBz
CBw
CBy
CBx
RBz
CBz
DQM
Hi Z
DQ
DBw0
DBw1 DBw2 DBw3
A ctiva te
W rite
C o m m an d C o m m a n d
Bank B
B an k B
DBx0
DBx1
DBy0
DBy1
DBy2
W rite
W rite
C om m a nd C o m m an d
B an k B
Bank B
DBy3
DBz0
DBz1
DBz2
DBz3
P re cha rg e A ctiva te
R e ad
C o m m a n d C o m m an d C o m m an d
B a nk B
B a nk B
B a nk B
SPT03923_2
Figure 29
Data Sheet
CAS Latency = 2
45
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
BS
AP
RBz
Addr.
RBz
RBz
CBz
CBx
CBy
RBz
CBz
DQM
DQ
Hi Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank B
Figure 30
Data Sheet
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
DBz0 DBz1
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B SPT03924
CAS Latency = 3
46
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Random Row Read (Interleaving Banks) with Precharge
B u rst L e n g th = 8 , C A S L a te n c y = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T 1 1 T 1 2 T 1 3 T1 4 T 1 5 T 1 6 T1 7 T 1 8 T 1 9 T 2 0
T2 1 T 2 2
C LK
t CK2
CKE
H ig h
CS
RAS
CAS
WE
BS
AP
RBx
A d d r.
RBx
RBy
RAx
CBx
RAx
CAx
RBy
CBy
t RP
t RCD
DQM
t AC2
H i-Z
B x 0 B x 1 B x 2 B x3 B x4 B x 5 B x6 B x 7 A x 0 A x 1 A x2 A x 3 A x4 A x 5 A x 6 A x7
DQ
R ead
A ctiva te
C om m and C om m and
Bank B
Bank B
A c tiv a te
C om m and
B ank A
P re c h a rg e A c tiv a te
C om m and C om m and
Bank B
Bank B
R ead
C om m and
Bank A
Figure 31
Data Sheet
B y0 B y1
R ead
C om m and
B ank B
SPT03925_2
CAS Latency = 2
47
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Burst Length = 8, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
BS
AP
RBx
Addr.
RBx
RAx
CBx
RBy
RAx
CAx
RBy
t AC3
t RCD
CBy
t RP
DQM
DQ
Hi-Z
Activate
Command
Bank B
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank A
SPT03926
Figure 32
Data Sheet
CAS Latency = 3
48
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Random Row Write (Interleaving Banks) with Precharge
B u rst L e n g th = 8 , C A S L ate n cy = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T 1 1 T 1 2 T 1 3 T 1 4 T 1 5 T 1 6 T 1 7 T 1 8 T 1 9 T 20
T21 T22
CLK
t CK2
CKE
H igh
CS
RAS
CAS
WE
BS
AP
RAx
A d d r.
RAx
RBx
CAx
RAy
RBx
CBx
t RCD
RAy
t WR
CAy
t WR
t RP
DQM
H i-Z
DQ
DAx0
DAx1
DAx2
A ctiv ate
W rite
C om m and C om m and
Bank A
Bank A
DAx3
DAx4
DAx5
DAx6
DAx7
DBx0
DBx1
DBx2
A ctiva te
W rite
C o m m a n d C o m m a nd
B a nk B
B a nk B
P re ch a rg e
C om m and
Bank A
Figure 33
Data Sheet
DBx3
DBx4
A ctiva te
C o m m an d
B an k A
DBx5
DBx6
DBx7
DAy0
DAy1
DAy2
DAy3
DAy4
P rec ha rg e
C o m m a nd
B a nk B
W rite
C om m and
Bank A
SPT03927_2
CAS Latency = 2
49
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Burst Length = 8, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
RAx
RAy
RBx
CAx
RBx
CBx
t RCD
RAy
t WR
t RP
CAy
t WR
DQM
DQ
Hi-Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
SPT03928
Figure 34
Data Sheet
CAS Latency = 3
50
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Precharge termination of a Burst
Burst Length = 8 or Full Page, CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
RAx
RAz
RAy
CAx
RAy
CAy
t RP
RAz
CAz
t RP
t RP
Ay0 Ay1 Ay2
Az0 Az1 Az2
DQM
DQ
Hi Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3
Write
Command
Bank A
Precharge Termination
of a Write Burst.
Write Data is masked.
Precharge
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Read Burst.
SPT03933
Figure 35
Data Sheet
CAS Latency = 2
51
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
Deep Power Down Mode
CLK
CKE
CS
WE
CAS
RAS
Addr.
DQM
DQ
input
DQ
output
High-Z
t RP
Precharge Command
Deep Power Down Entry
Deep Power Down Mode
Normal Mode
DP1.vsd
Figure 36
Deep Power Down Mode Entry
Note: The deep power down mode has to be maintained for a minimum of 100µs.
Data Sheet
52
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
CLK
CK E
CS
RAS
CAS
WE
200
Deep Power Do wn
exi t
Figure 37
s
tRP
All banks
prec harge
tRC
Au to
refresh
Auto
refresh
Mode
Register
Set
Exte nded
Mode
Regis ter
Set
New
Com mand
Accepted
Here
Deep Power Down Exit
Note: The deep power down mode is exited by asserting CKE high. After the exit, the following sequence is needed
to enter a new command:
1.
2.
3.
4.
5.
Maintain NOP input conditions for a minimum of 200 µs
Issue precharge commands for all banks of the device
Issue eight or more autorefresh commands
Issue a mode register set command to initialize the mode register
Issue an extended mode register set command to initialize the extende mode register
Data Sheet
53
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Package Outline
6
Package Outline
P-TFBGA-54
(Plastic Thin Small Outline Package Type II)
tolerance ±0.1mm for length and width
Figure 38
Package Outline
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
54
V1.1, 2003-04-16
http://www.infineon.com
Published by Infineon Technologies AG